Patent Grant
10665201
The present invention relates to a display device and a display method.
In
Consequently, the voltage for displaying is applied only once within a single frame period. In
In the current frame, since the amount of change in the voltage applied to the pixel electrodes is small in the region 112, the alignment is not disturbed much in the locations of weak alignment-restricting force inside the pixels. Consequently, in the region 112, an afterimage does not occur, and white is displayed correctly. On the other hand, in the current frame, since the amount of change in the voltage applied to the pixel electrodes is large in the region 111, the alignment is disturbed greatly in the locations of weak alignment-restricting force inside the pixels. Because of this, in the current frame, a phenomenon occurs in which the brightness of the pixels in the region 112 becomes different than the brightness of the pixels in the region 111. As a result, the display color of the region 112 is influenced by the black in the previous frame, and is no longer displayed as white. Because of this, an afterimage of the color of the previous frame occurs in the region 111.
PTL 1 discloses a drive circuit of an active-matrix liquid-crystal display device provided with a plurality of video signal lines for respectively transmitting a plurality of video signals expressing an image to be displayed, a plurality of scan signal lines that intersect with the plurality of video signal lines, and a plurality of pixel-forming parts disposed in a matrix, each corresponding to an intersection point between the plurality of video signal lines and the plurality of scan signal lines, the drive circuit comprising: a scan signal line drive circuit that selectively drives the plurality of scan signal lines such that each scan signal line is selected during a preliminary charging period preset for each scan signal line and during a main charging period preset as a period after the preliminary charging period; and a video signal line drive circuit that applies a voltage obtained by adding a predetermined voltage to a voltage for expressing the image to be displayed to the plurality of video signal lines in an overlapping charging period that, in the main charging period for each scan signal line, overlaps with the preliminary charging period for a scan signal line other than each scan signal line, and applies the voltage for expressing the image to be displayed to the plurality of video signal lines in a period other than the overlapping charging period in the main charging period for each scan signal line, wherein the overlapping charging period for each scan signal line is a partial period in the main charging period for a scan signal line other than each scan signal line, and corresponds to a predetermined period from the start of the main charging period. Furthermore, PTL 1 also discloses that, according to the drive circuit, it is possible to provide a highly responsive liquid-crystal display device capable of achieving greater power savings, reduced size, and lowered costs.
PTL 2 discloses a liquid-crystal display device provided with: a plurality of pixels arranged in a matrix, each including a pixel electrode for applying a voltage to a liquid crystal placed between the pixel electrode and a counter electrode, and a switching element connected to the pixel electrode; a plurality of scan lines arranged in a column direction, which are commonly connected to the switching elements in a row direction; and a vertical scan circuit that supplies a scan signal controlling the switching elements between a conducting state and a non-conducting state to scan the pixels sequentially by each scan line. The scan signal includes a first conducting signal that sets the switching elements to the conducting state; a second conducting signal that sets the switching elements to the conducting state later than the first conducting signal, and a non-conducting signal that sets the switching elements to the non-conducting state between the first conducting signal and the second conducting signal. During a period in which the second conducting signal is being applied to a predetermined scan line, the vertical scan circuit applies the first conducting signal and the non-conducting signal to the scan line to be scanned next after the predetermined scan line. Furthermore, PTL 2 also discloses that, according to the liquid-crystal display device, it is possible to suppress the degradation of image quality caused by parasitic capacitance coupling between pixel electrodes and feed-through between pixels, and suppress the degradation of image quality caused by the occurrence of pixel defects over a plurality of rows.
[PTL 1]
Japanese Unexamined Patent Application Publication No. 2007-248536
[PTL 2]
Japanese Unexamined Patent Application Publication No. 2009-180826
However, with the technology according to Patent Literature 1 and 2, it is not possible to suppress the occurrence of an afterimage on the display screen.
An objective of one aspect of the present invention is to suppress the occurrence of an afterimage on the display screen.
(1) One embodiment of the present invention is a display device comprising: a display unit including a plurality of gate lines, a plurality of source lines intersecting the plurality of gate lines, and a plurality of pixels formed at each intersection between the gate lines and the source lines; a gate driver that selects the plurality of gate lines individually, and in a first period within a single frame period stipulated for the selected gate line, outputs a first gate voltage to the selected gate line, and additionally, in a second period coming after the first period within the single frame period and also longer than the first period stipulated for the selected gate line, outputs a second gate voltage equal to the first gate voltage to the selected gate line; and a source driver that, in the first period, outputs an unchanged plurality of first source voltages expressing information to be displayed by one row of the pixels corresponding to the selected gate line or an unchanged plurality of second source voltages expressing information to be displayed by one row of the pixels corresponding to any other gate line disposed before the selected gate line to the plurality of source lines, and additionally, in the second period, outputs the unchanged plurality of first source voltages to the plurality of source lines.
(2) Another embodiment of the present invention is a display device comprising: a display unit including a plurality of gate lines, a plurality of source lines intersecting the plurality of gate lines, and a plurality of pixels formed at each intersection between the gate lines and the source lines; a gate driver that selects the plurality of gate lines individually, and in a first period within a single frame period stipulated for the selected gate line, outputs a first gate voltage to the selected gate line, and additionally, in a second period coming after the first period within the single frame period stipulated for the selected gate line, outputs a second gate voltage higher than the first gate voltage to the selected gate line; and a source driver that, in the first period, outputs an unchanged plurality of first source voltages expressing information to be displayed by one row of the pixels corresponding to the selected gate line or an unchanged plurality of second source voltages expressing information to be displayed by one row of the pixels corresponding to any other gate line disposed before the selected gate line to the plurality of source lines, and additionally, in the second period, outputs the unchanged plurality of first source voltages to the plurality of source lines.
(3) Also, in one embodiment of the present invention, in addition to the configuration of the above (1) or (2), the source driver outputs the plurality of first source voltages of the same polarity as the plurality of first source voltages or the plurality of second source voltages output in the first period to the plurality of source lines in the second period.
(4) Also, in one embodiment of the present invention, in addition to the configuration of any of the above (1) to (3), in a case in which the second period stipulated for the selected gate line overlaps with the first period stipulated for any other gate line disposed before the selected gate line, the gate driver additionally selects the other gate line during the second period.
(5) Also, in one embodiment of the present invention, in addition to the configuration of any of the above (1) to (4), in a case in which the first period corresponding to the selected gate line does not overlap with the second period stipulated for any of the gate lines disposed before the selected gate line, the source driver outputs the unchanged plurality of first source voltages to the plurality of source lines in the first period.
(6) One embodiment of the present invention is a display method executed by a display device provided with a display unit including a plurality of gate lines, a plurality of source lines intersecting the plurality of gate lines, and a plurality of pixels formed at each intersection between the gate lines and the source lines, the display method comprising: a first output step of selecting the plurality of gate lines individually, and in a first period within a single frame period stipulated for the selected gate line, outputting a first gate voltage to the selected gate line, and additionally, in a second period coming after the first period within the single frame period and also longer than the first period stipulated for the selected gate line, outputting a second gate voltage equal to the first gate voltage to the selected gate line; and a second output step of, in the first period, outputting an unchanged plurality of first source voltages expressing information to be displayed by one row of the pixels corresponding to the selected gate line or an unchanged plurality of second source voltages expressing information to be displayed by one row of the pixels corresponding to any other gate line disposed before the selected gate line to the plurality of source lines, and additionally, in the second period, outputting the unchanged plurality of first source voltages to the plurality of source lines.
(7) Another embodiment of the present invention is a display method executed by a display device provided with a display unit including a plurality of gate lines, a plurality of source lines intersecting the plurality of gate lines, and a plurality of pixels formed at each intersection between the gate lines and the source lines, the display method comprising: a first output step of selecting the plurality of gate lines individually, and in a first period within a single frame period stipulated for the selected gate line, outputting a first gate voltage to the selected gate line, and additionally, in a second period coming after the first period within the single frame period stipulated for the selected gate line, outputting a second gate voltage higher than the first gate voltage to the selected gate line; and a second output step of, in the first period, outputting an unchanged plurality of first source voltages expressing information to be displayed by one row of the pixels corresponding to the selected gate line or an unchanged plurality of second source voltages expressing information to be displayed by one row of the pixels corresponding to any other gate line disposed before the selected gate line to the plurality of source lines, and additionally, in the second period, outputting the unchanged plurality of first source voltages to the plurality of source lines.
According to an embodiment of the present invention, it is possible to suppress the occurrence of an afterimage on the display screen.
(Configuration of Liquid-Crystal Display Device 1)
The display unit 2 includes n gate lines GL1 to GLn, m source lines SL1 to SLm, n storage capacitor lines CS1 to CSn, and (m×n) pixels 6.
The gate lines GL1 to GLn are disposed parallel to each other. The source lines SL1 to SLm are disposed parallel to each other and orthogonally to the gate lines GL1 to GLn. The gate lines GL1 to GLn and the source lines SL1 to SLm intersect at (m×n) locations. The (m×n) pixels 6 are disposed near the intersections of the gate lines GL1 to GLn and the source lines SL1 to SLm. The storage capacitor lines CS1 to CSn are disposed parallel to the gate lines GL1 to GLn.
Each pixel 6 includes a transistor Tw, a liquid-crystal capacitor Clc, and a storage capacitor Ccs. The gate electrode of the transistor Tw is connected to the corresponding gate line GL. The source electrode of the transistor Tw is connected to the corresponding source line SL. The drain electrode of the transistor Tw is connected to an electrode of both the liquid-crystal capacitor Clc and the storage capacitor Ccs. One electrode of the liquid-crystal capacitor Clc serves as a pixel electrode. The other electrode of the liquid-crystal capacitor Clc is connected to a common electrode (not illustrated). The other electrode of the storage capacitor Ccs is connected to the corresponding storage capacitor line. The storage capacitor lines CS1 to CSn are driven by a storage capacitor line driver (not illustrated) provided on the outside of the display unit 2.
The gate driver 4 and the source driver 5 are driver circuits of the liquid-crystal display device 1. The gate driver 4 drives the gate lines GL1 to GLn, and the source driver 5 drives the source lines SL1 to SLm. The display control circuit 3 outputs a control signal CA to the gate driver 4, and outputs a control signal CB and a data signal DT to the source driver 5. On the basis of the control signal CA, the gate driver 4 individually selects at least one gate line GL from among the gate lines GL1 to GLn, and outputs a gate voltage to the selected gate line GL. With this arrangement, one row of m pixels 6 corresponding to the selected gate line GL is selected collectively. On the basis of the control signal CB, the source driver 5 applies m source voltages according to the data signal DT to the source lines SL1 to SLm, respectively. With this arrangement, the m voltages are written to the selected m pixels 6, respectively.
(Configuration of Liquid-Crystal Display Device 1)
In the array substrate 11, in the pixel electrode 14, a slit 23 where part of the pixel electrode 14 is missing is formed. In the color filter substrate, a rib is formed at a position facing opposite the pixel electrode 14. The liquid-crystal layer 16 includes negative liquid crystals 24. In the state in which a voltage is not applied to the pixel electrode 14, the liquid crystals 24 are oriented vertically with respect to the array substrate 11 and the color filter substrate 22.
In the liquid-crystal display device 1, the polarizer included in the first polarizing plate and the polarizer included in the second polarizing plate are orthogonal to each other. In the state in which a voltage is not applied to the pixel electrode 14, since birefringence does not occur in the liquid crystals 24, the light of a backlight not illustrated is unable to be transmitted through the liquid-crystal layer 16. If a voltage is applied to the pixel electrode 14 and a common voltage is applied to the common electrode, the liquid crystals 24 are oriented in parallel with the array substrate 11 and the color filter substrate 22. In this way, by applying a voltage to change the orientation direction of the liquid crystals 24 from the vertical direction to the horizontal direction, birefringence occurs in the liquid-crystal layer 16. As a result, since the polarization direction of light in the liquid-crystal layer 16 changes, light from the backlight becomes able to be transmitted through the liquid-crystal layer 16.
The liquid-crystal display device 1 is not limited to a liquid-crystal display device 1 with a configuration corresponding to the multidomain vertical alignment (MVA) mode as illustrated in
(Driving of Liquid-Crystal Display Device 1)
In the liquid-crystal display device 1, for each gate line GL, a period A (first period) and a period B (second period) in which the gate line GL is driven within a single frame period are stipulated. For example, a period A1 and a period B1 are stipulated in advance for the gate line GL1, a period A2 and a period B2 are stipulated in advance for the gate line GL2, and a period A3 and a period B3 are stipulated in advance for the gate line GL3. Both the period A and the period B are included in a single frame period. The period B is disposed after the period A within a single frame period. The lengths of the periods A are equal to each other, and the lengths of the periods B are equal to each other. The period B is longer than the period A. In the example of
In a single frame period, the gate driver 4 individually selects the gate lines GL1 to GLn. In the example of
More specifically, the source driver 5 outputs multiple source voltages directly to the source lines SL1 to SLm, without adding a predetermined voltage to the multiple source voltages according to the data signal. Consequently, in the case in which the color of one row of the pixels 6 corresponding to the gate line GL1 is defined as white in the data signal of the current frame, during the first driving on the gate line GL1, a 5V source voltage expressing white is output directly to the source lines SL1 to SLm.
After the end of the period A1, the gate driver 4 selects the gate line GL2. In the period A2 stipulated for the selected gate line GL2, the gate driver 4 outputs the voltage Vgh to the selected gate line GL2. The period A2 stipulated for the gate line GL2 does not overlap the period B stipulated for any other gate line GL disposed after the gate line GL2. With this arrangement, in the period A2, the source driver 5 outputs multiple unchanged source voltages expressing information to be displayed by one row of the pixels 6 corresponding to the selected gate line GL2 to the source lines SL1 to SLm.
After the end of the period A2, the gate driver 4 sequentially selects the gate line GL3 and each gate line GL thereafter, and the drives the selected gate line GL similarly to the gate line GL1. In the example of
After the period A99, the gate driver 4 selects the gate line GL1 again. In the period B1 stipulated for the selected gate line GL1, the gate driver 4 outputs a voltage Vgh equal in magnitude to the voltage Vgh output in the period A1 to the gate line GL1. With this arrangement, the gate line GL1 is driven (second driving). In the period B1, the source driver 5 outputs multiple unchanged source voltages (first source voltages) expressing information to be displayed by one row of the pixels 6 corresponding to the selected gate line GL1 to the source lines SL1 to SLm. In this way, in the period A1 and the period B1, the same multiple source voltages corresponding to the same pixels 6 are output to the source lines SL1 to SLm.
The period B1 stipulated for the gate line GL1 overlaps with the period A100 stipulated for the gate line GL100 disposed after the gate line GL1. With this arrangement, the gate driver 4 additionally selects the gate line GL100 in the period A100. In other words, while the period B1 and the period A100 overlap, the gate driver 4 is selecting the gate line GL1 and the gate line GL100 simultaneously. In the period A100 stipulated for the selected gate line GL100, the gate driver 4 outputs the voltage Vgh to the gate line GL100. In this way, while the period B1 and the period A100 overlap, the liquid-crystal display device 1 is driving the gate line GL1 and the gate line GL100 simultaneously. Since this arrangement makes it possible to decrease the total number of drivings of the gate lines GL1 to GLn within a single frame period, the power consumption of the liquid-crystal display device 1 can be reduced.
From another perspective, the period A100 stipulated for the gate line GL100 overlaps with the period B1 stipulated for the gate line GL1 disposed before the gate line GL100. With this arrangement, in the period A100, the source driver 5 continues to output the multiple source voltages already output. In other words, at the start point of the period A100, the source driver 5 has already output multiple unchanged source voltages (second voltages) expressing information to be displayed by one row of the pixels 6 corresponding to the gate line GL1 disposed before the selected gate line GL100 to the source lines SL1 to SLm. With this arrangement, the source driver 5 uses the multiple source voltages output in the period B1 to charge each of the pixels 6 corresponding to the gate line GL1 with a second drain voltage (charging in the period B1), while also charging each of the pixels 6 corresponding to the gate line GL100 with a first drain voltage (charging in the period A100). In other words, the source driver 5 uses common source voltages to execute the second charging of each of the pixels 6 on the 1st row and the first charging of each of the pixels 6 on the 100th row simultaneously in the period (the first half of the period B1) during which the period B1 and the period A100 overlap. With this arrangement, the multiple source voltages for charging each of the pixels 6 corresponding to the gate line GL100 with the first drain voltage are already output without outputting source voltages separately in the period A100. Consequently, the power consumption of the liquid-crystal display device 1 can be reduced.
In the example of
Since the first driving and the second driving targeting each of the gate lines GL3 to GLn in the period B2 stipulated for the gate line GL3 and thereafter are all substantially the same as the driving in the period A100 or A101 (first driving) and the driving in the period B1 (second driving), a detailed description is omitted.
As illustrated in
Since the period A1 is shorter than the period B1, the time during which the transistor Tw is on in the first driving is shorter than the second driving. With this arrangement, the first driving has a smaller charge rate of the drain electrode of the transistor Tw than the second driving. In the example of
In the example of
In the current frame, since the amount of change in the voltage applied to the pixel electrodes 14 is small in the region 32, the alignment is not disturbed much in the locations of weak alignment-restricting force inside the pixels 6. Consequently, in the region 32, an afterimage does not occur, and white is displayed correctly in the current frame. On the other hand, in the current frame, since the amount of change in the voltage applied to the pixel electrodes 14 is also small in both the first driving and the second driving in the region 32, the alignment is not disturbed much in the locations of weak alignment-restricting force inside the pixels 6. Consequently, an afterimage likewise does not occur in the region 31, and white is displayed correctly after displaying a neutral color in the current frame. With this arrangement, the occurrence of an afterimage is suppressed throughout the entire display screen.
In the example illustrated in
The source driver 5 preferably outputs multiple source voltages of the same polarity as the multiple source voltages output to the source lines SL1 to SLm in the period A to the source lines SL1 to SLm in the period B. For example, in the case in which the source driver 5 outputs multiple source voltages of positive polarity (5V) to the source lines SL1 to SLm in the period A1, the source driver 5 also outputs multiple source voltages of positive polarity (5V) to the source lines SL1 to SLm in the period B1. For example, in the case in which the source driver 5 outputs multiple source voltages of negative polarity (−5V) to the source lines SL1 to SLm in the period A2, the source driver 5 also outputs multiple source voltages of negative polarity (−5V) to the source lines SL1 to SLm in the period B2. In these cases, the voltage applied to the same pixel electrode 14 in a single frame period does not change from positive polarity to negative polarity or from negative polarity to positive polarity. As a result, since the change in the voltage applied to the same pixel electrode 14 in a single frame period is small, the occurrence of an afterimage can be suppressed effectively.
In the example illustrated in
Since the lengths of the period A1 and the period B1 are the same, in both the first driving and the second driving, the transistor Tw is turned on for the same amount of time. In the present embodiment, the voltage Vgh2 applied to the gate electrode of the transistor Tw during the first driving is lower than the voltage Vgh applied to the gate electrode of the transistor Tw during the second driving. With this arrangement, the first driving has a smaller charge rate of the drain electrode of the transistor Tw than the second driving. In the example of
As above, in the liquid-crystal display device 1 according to the present embodiment, since a neutral color is inserted partway through when the color of the pixels 6 changes within a single frame period, the occurrence of an afterimage on the display screen can be suppressed similarly to Embodiment 1.
Although omitted from illustration, in the present embodiment, there may also be several microseconds between the period A and the period B stipulated for each gate line GL, similarly to Embodiment 1. Even in this case, an effect of suppressing an afterimage is obtained.
The present disclosure is not limited to the embodiments discussed above, and various modifications are possible within the scope indicated by the claims. Embodiments obtained by appropriately combining the technical means respectively disclosed in different embodiments are also included within the technical scope of the present disclosure. Furthermore, new technical features may be formed by combining the technical means respectively disclosed in each of the embodiments.
| Number | Name | Date | Kind |
|---|---|---|---|
| 20090190047 | Oomura | Jul 2009 | A1 |
| 20140253531 | Lee | Sep 2014 | A1 |
| 20160171933 | Takahara | Jun 2016 | A1 |
| 20180068615 | Imai | Mar 2018 | A1 |
| 20180113564 | Takahashi | Apr 2018 | A1 |
| Number | Date | Country |
|---|---|---|
| 2007-248536 | Sep 2007 | JP |
| 2009-180826 | Aug 2009 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20200013366 A1 | Jan 2020 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62693544 | Jul 2018 | US |
