Patent Grant
10460694
A high-resolution display device displays video by a division display method, for example. The division display method is a display method of dividing a display area into a plurality of division display areas, and simultaneously driving those division display areas separately by signal line drivers.
In a display device of a division drive method, if there is a potential difference in the voltage which serves as a reference of a gradation voltage between the respective signal line drivers, a difference in level of the brightness between the division display areas and non-uniformity in display may occur.
Embodiments described herein relate generally to a display device.
Embodiments of the present application will be described below in detail with reference to the drawings.
In general, according to one embodiment, a display device which includes a plurality of signal line drivers which drive a display area of a display panel by dividing the display area into a plurality of division display areas is provided. The plurality of signal line drivers include a master signal line driver and a slave signal line diver. Each of the master signal line driver and the slave signal line driver drives at least one of the plurality of division display areas. The display device includes an outward path and a return path. The outward path outputs a direct-current voltage from the master signal line driver to the slave signal line driver. The return path is electrically connected to and is contiguous with the outward path that has entered the slave signal line driver, and returns the direct-current voltage to the master signal line driver.
Embodiments will be described hereinafter with reference to the accompanying drawings. The disclosure is merely an example, and proper changes within the spirit of the invention, which are easily conceivable by a skilled person, are included in the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are schematically illustrated in the drawings, compared to the actual modes. However, the schematic illustration is merely an example, and adds no restrictions to the interpretation of the invention. Furthermore, in the description and figures of the present application, structural elements having the same or similar functions will be referred to by the same reference numbers and detailed explanations of them that are considered redundant may be arbitrarily omitted.
A display device DSP includes a processor PRO, a circuit board (PCB) 100, a scanning line driver GD, a signal line driver SD, and a display panel PNL. The processor PRO includes a control module CM and a power source voltage supply module SM. The scanning line driver GD includes a scanning line driver circuit GIC, and the signal line driver SD includes a signal line driver circuit. The display panel PNL is a liquid crystal display panel including pixels PX arranged in a matrix in a display area DA which displays an image, for example. In the example illustrated, the display panel PNL includes, in each pixel PX, a scanning line G, a signal line D, a pixel switching element PSW, a pixel electrode PE, a liquid crystal layer LQ, a common electrode CE, etc. Note that as will be described later referring to
Note that the display panel PNL is not limited to a liquid crystal display panel. The display panel PNL may be a mechanical display panel, etc., which controls luminance of each pixel by a micro-electromechanical systems (MEMS) shutter, for example, or a self-luminous display panel which uses an organic light-emitting diode (OLED), for example. A display mode of the liquid crystal display panel is also not particularly limited, and may be one which uses a lateral electric field or one which uses a longitudinal electric field.
The control module CM supplies an input signal SIN to the scanning line driver GD and the signal line driver SD. The input signal SIN includes display data of an image, a clock signal, a vertical synchronization signal, a horizontal synchronization signal, or a display timing signal, etc. The power source voltage supply module SM supplies an input voltage VIN to the scanning line driver GD and the signal line driver SD. The scanning line driver circuit GIC generates a scan signal SS based on the supplied input signal SIN and input voltage VIN, and supplies the generated scanning signal SS to each pixel PX. A signal line driver circuit SIC also generates a data signal DS in the same way, and supplies the generated data signal DS to each pixel PX.
The signal line driver SD is connected to i signal lines D (D1 to Di) extending in the first direction X, respectively, and which are arranged in the second direction Y. The scanning line driver GD is connected to j scanning lines G (G1 to Gj) extending in the second direction Y, respectively, and which are arranged in the first direction X. The signal line D and the scanning line G are connected to the pixel switching element PSW at a position where the two cross each other. The pixel electrode PE is connected to the pixel switching element PSW, and forms a liquid crystal capacitance CLQ between the pixel electrode PE and the common electrode CE. Also, a retaining capacitance CST is formed between the pixel electrode PE and the common electrode CE. All of the common electrodes CE are electrically connected to each other, and a common potential VCOM is supplied to the common electrodes.
The scanning line driver GD sequentially selects a scanning line from a first scanning line G1 to a jth scanning line Gj, and supplies a scan voltage to each of the scanning lines G during one horizontal scan time. The scan voltage, which is a positive or negative bias voltage, is supplied to each of the pixel switching elements PSW connected to the first scanning line G1, and controls electrical connection between each of the signal lines D and the pixel electrode PE (i.e., the on state and off state) via the corresponding pixel switching element PSW. The signal line driver SD supplies a data signal to each of the pixel switching elements PSW connected to the first scanning line G1 via the signal line D during the horizontal scan time of the first scanning line G1. When the pixel switching element PSW is in the on state, a data signal, which is a gradation signal, is written to the pixel electrode PE via the corresponding pixel switching element PSW, and is retained by the liquid crystal capacitance CLQ and the retaining capacitance CST. Similarly, the signal line driver SD writes a data signal to the corresponding pixel electrode PE during the respective horizontal scan times of a second scanning line G2 to the jth scanning line Gj. A potential difference between the common electrode CE and the pixel electrode PE formed in this way controls alignment of liquid crystal molecules in the liquid crystal layer LQ.
Meanwhile, when the display device DSP includes a plurality of signal line drivers SD, an error in a potential level of the data signal generated in each one of the signal line drivers SD may be caused by a difference in analog voltages supplied to gradation power sources of the signal line drivers SD. In such a case, a capacitance error according to the potential error of the data signal is caused in each of the liquid crystal capacitances CLQ, and non-uniformity in display of the display device DSP occurs. Hence, the present inventors have found an embodiment as described below as the display device DSP capable of suppressing non-uniformity in display. This embodiment will be described with reference to
The display panel PNL includes a first division display area DA1, a second division display area DA2, a third division display area DA3, and a fourth division display area DA4 in the display area DA. In the example illustrated, the display area DA is rectangular, and each of the division display areas is also rectangular. The first division display area DA1 is located diagonally to the third division display area DA3, and the second division display area DA2 is located diagonally to the fourth division display area DA4. The first division display area DA1 and the fourth division display area DA4 are both adjacent to the second division display area DA2 and the third division display area DA3. The first division display area DA1 to the fourth division display area DA4 display an image, for example, in cooperation with each other.
The signal line driver SD includes a first signal line driver 10, a second signal line driver 20, a third signal line driver 30, and a fourth signal line driver 40. The scanning line driver GD includes a first scanning line driver 1 and a second scanning line driver 2. The first signal line driver 10 to the fourth signal line driver 40 include a first signal line driver circuit SIC1 to a fourth signal line driver circuit SIC4, respectively. The first scanning line driver 1 and the second scanning line driver 2 include a first scanning line driver circuit GIC1 and a second scanning line driver circuit GIC2. The first signal line driver 10 is connected to a non-display area NDA near the first division display area DA1. Similarly, the second signal line driver 20 to the fourth signal line driver 40 are connected to the non-display area NDA near the second division display area DA2 to the fourth division display area DA4. The first scanning line driver 1 is connected to the non-display area NDA near the first division display area DA1 and the fourth division display area DA4, and the second scanning line driver 2 is connected to the non-display area NDA near the second division display area DA2 and the third division display area DA3.
For example, the first division display area DA1 and the fourth division display area DA4 are driven by the first scanning line driver 1, the first signal line driver 10, and the fourth signal line driver 40. For example, a scan voltage is supplied from the first scanning line driver 1 to pixels R, G, and B which are arranged in the second direction Y in the first division display area DA1 and the fourth division display area DA4. In addition, a data signal is supplied from the first signal line driver 10 and the fourth signal line driver 40 alternately to the pixels R, G, and B arranged in the second direction Y. At this time, the second division display area DA2 and the third division display area DA3 are driven by the second scanning line driver 2, the second signal line driver 20, and the third signal line driver 30. Note that the division display areas DA1 to DA4 may be driven by the signal line drivers 10 to 40 different from each other. That is, the first division display area DA1 may be driven by the first signal line driver 10, the second division display area DA2 may be driven by the second signal line driver 20, the third division display area DA3 may be driven by the third signal line driver 30, and the fourth division display area DA4 may be driven by the fourth signal line driver 40. As described above, each of the signal line drivers drives at least one of the division display areas.
As long as a plurality of division display areas and signal line drivers are provided, the numbers of division display areas and signal line drivers are not particularly limited. That is, the numbers of division display areas and signal line drivers may be five or more, or three or less.
In the example illustrated in
The signal line driver SD includes an outward path 91 and a return path 92. The outward path 91 is formed throughout the master signal line driver 10 to the third slave signal line driver 40. In the example illustrated, the outward path 91 is an electrical line of a single system which outputs a direct-current voltage Vdc from the master signal line driver 10 to the first slave signal line driver 20 to the third slave signal line driver 40. The return path 92 is formed throughout the third slave signal line driver 40 to the master signal line driver 10. In the example illustrated, the return path 92 is electrically connected to the outward path 91 in the third slave signal line driver 40, and is an electrical line of a single system which is contiguous with the outward path 91. The return path 92 returns the direct-current voltage Vdc from the third slave signal line driver 40 to the master signal line driver 10. That is, the direct-current voltage Vdc which is output from the master signal line driver 10 is returned to the master signal line driver 10 by way of all of the slave signal line drivers.
The signal line driver SD includes inter-driver conductive lines 50, 60, and 70. The inter-driver conductive line 50 is arranged between the master signal line driver 10 and the first slave signal line driver 20. The inter-driver conductive line 60 is arranged between the first slave signal line driver 20 and the second slave signal line driver 30. The inter-driver conductive line 70 is arranged between the second slave signal line driver 30 and the third slave signal line driver 40. Each of the inter-driver conductive lines 50, 60, and 70 is, for example, a flexible flat cable (FFC). In the example illustrated in
The direct-current voltage Vdc of the outward path 91 which is output from the master signal line driver 10 is conducted through the inter-driver conductive line 50 and is supplied to the first slave signal line driver 20, is conducted through the inter-driver conductive line 60 and is supplied to the second slave signal line driver 30, and is further conducted through the inter-driver conductive line 70 and is supplied to the third slave signal line driver 40. That is, the direct-current voltage Vdc of the outward path 91 is supplied to all of the slave signal line drivers 20, 30, and 40 through the inter-driver conductive line 50. The direct-current voltage Vdc of the return path 92, which is output from the third slave signal line driver 40, is conducted through the inter-driver conductive line 70, the second slave signal line driver 30, the inter-driver conductive line 60, the first slave signal line driver 20, and the inter-driver conductive line 50 in this order, and is returned to the master signal line driver 10. It is assumed that the length of the inter-driver conductive line 50 is equal to that of the inter-driver conductive line 70, and is less than that of the inter-driver conductive line 60. Further, in each of the inter-driver conductive lines 50 to 70, it is assumed that the length of the outward path 91 is equal to that of the return path 92.
The potential of the direct-current voltage Vdc of the outward path 91 and the return path 92 is lowered by a voltage drop VF1 (VF1f, VF1r) caused by the interconnection resistance when the direct-current voltage Vdc is conducted through the inter-driver conductive line 50. The potential is also lowered by a voltage drop VF2 (VF2f, VF2r) caused by the interconnection resistance when the direct-current voltage Vdc is conducted through the inter-driver conductive line 60. The potential is also lowered by a voltage drop VF3 (VF3f, VF3r) caused by the interconnection resistance when the direct-current voltage Vdc is conducted through the inter-driver conductive line 70.
A value of the voltage drop can be obtained by the product of a value of a current and a value of resistance. In the outward path 91, since the current is consumed in each of the slave signal line drivers 20 to 40, values of the currents that flow through the inter-driver conductive lines 50, 60, and 70 are different from one another. Also, in the return path 92, since no current is consumed in the first slave signal line driver 20 and the second slave signal line driver 30, the values of the currents that flow through the inter-driver conductive lines 50, 60, and 70 are substantially the same. It is assumed that a consumption current is substantially the same in each of the signal line drivers 10 to 40. The resistance of inter-driver conductive line 50 is substantially equal to the resistance of the inter-driver conductive line 70, and is smaller than the resistance of the inter-driver conductive line 60. Accordingly, if a value or ratio of the interconnection resistance of each of the inter-driver conductive lines 50, 60, and 70, and the consumption current of each of the signal line drivers 10 to 40 are known, the ratio of the voltage drops VF1f to VF3f of the outward path 91 to the voltage drops VF1r to VF3r of the return path 92 can be determined. That is, the values of the voltage drops VF1f to VF3f of the outward path 91 can be calculated from a difference of the direct-current voltage Vdc.
The master signal line driver 10 includes a direct-current voltage generation circuit (DC/DC) 12, a gradation power source (GVG) 11, a voltage comparator (COMP) 13, and a host circuit (HOST) 14. The first slave signal line driver 20 includes a gradation power source 21, the second slave signal line driver 30 includes a gradation power source 31, and the third slave signal line driver 40 includes a gradation power source 41. The direct-current voltage generation circuit 12 is electrically connected to the outward path 91. The direct-current voltage generation circuit 12 generates a direct-current voltage Vdc, and outputs the direct-current voltage Vdc to the outward path 91. The direct-current voltage Vdc of the outward path 91 is diverged to the gradation power source 11 as an analog voltage Va1 in the master signal line driver 10, and is diverged to the gradation power sources 21 to 41 as analog voltages Va2 to Va4 in the first slave signal line driver 20 to the third slave signal line driver 40. Because of the voltage drops VF1f to VF3f of the outward path 91, the potential of the direct-current voltage Vdc is different in each of the signal line drivers 10 to 40. Accordingly, the potential of each of the analog voltages Va1 to Va4 is different.
The voltage comparator 13 compares between the direct-current voltage Vdc input from the outward path 91 and the direct-current voltage Vdc input from the return path 92. The host circuit 14 calculates the potential of the direct-current voltage Vdc of the outward path 91 in each of the slave signal line drivers 20 to 40, on the basis of a result of comparison of the direct-current voltage Vdc input from the voltage comparator 13. That is, the host circuit 14 calculates the potential of each of the analog voltages Va1 to Va4. The host circuit 14 generates voltage control signals Sc1, Sc2, Sc3, and Sc4 which perform control so that gradation voltages Vg1 to Vg4 generated in the respective signal line drivers 10 to 40 are equalized, on the basis of the potentials of the respective analog voltages Va1 to Va4. Next, the host circuit 14 transmits the voltage control signals Sc1 to Sc4 to the corresponding gradation power sources 11 to 41 via a bus line 93. Note that the bus line 93 is a serial data communication path (I2C), for example, and is formed throughout the master signal line driver 10 to the third slave signal line driver 40. Here, an address is assigned to each of the master signal line driver 10 and the slave signal line drivers 20 to 40. In this way, items of address data corresponding to the respective signal line drivers, and voltage control signals corresponding to the respective items of address data are output to the bus line 93 as a sequence of serial data.
In the master signal line driver 10, the gradation power source 11 outputs the gradation voltage Vg1, on the basis of the input analog voltage Va1 and voltage control signal Sc1. In the first slave signal line driver 20, the gradation power source 21 outputs the gradation voltage Vg2, on the basis of the input analog voltage Va2 and voltage control signal Sc2. In the second slave signal line driver 30, the gradation power source 31 outputs the gradation voltage Vg3, on the basis of the input analog voltage Va3 and voltage control signal Sc3. In the third slave signal line driver 40, the gradation power source 41 outputs the gradation voltage Vg4, on the basis of the input analog voltage Va4 and voltage control signal Sc4.
As described above, the display device DSP includes a plurality of signal line drivers 10, 20, 30, and 40 which drive a screen of the display area DA of the display panel PNL by dividing it into the division display areas DA1, DA2, DA3, and DA4. The plurality of signal line drivers 10, 20, 30, and 40 include the master signal line driver 10 and at least one of the slave signal line drivers 20, 30, and 40. The master signal line driver 10 and the at least one of the slave signal line drivers 20, 30, and 40 drive at least one of the division display areas DA1, DA2, DA3, and DA4. The display device DSP includes the outward path 91 which outputs a direct-current voltage Vdc from the master signal line driver 10 to the slave signal line drivers 20, 30, and 40, and the return path 92, which is electrically connected to and is contiguous with the outward path 91 that has entered the slave signal line drivers 20, 30, and 40, and returns the direct-current voltage Vdc to the master signal line driver 10.
The display device DSP further includes the direct-current voltage generation circuit 12, which is arranged in the master signal line driver 10 and generates the direct-current voltage Vdc, and a plurality of gradation power sources 11, 21, 31, and 41, which are arranged in the signal line drivers 10, 20, 30, and 40, respectively, and generate the gradation voltages Vg1, Vg2, Vg3, and Vg4 by using the analog voltages Va1, Va2, Va3, and Va4 diverged from the direct-current voltage Vdc of the outward path 91.
Also, the master signal line driver 10 includes the voltage comparator 13 which compares the direct-current voltage Vdc returned via the return path 92 with the direct-current voltage Vdc output to the outward path 91, and the host circuit 14 which calculates the direct-current voltage Vdc in the slave signal line drivers 20, 30, and 40, on the basis of the result of comparison given by the voltage comparator 13.
Further, in the display device DSP, between the master signal line driver 10 and the slave signal line driver 20 which is adjacent to the master signal line driver 10, the inter-driver conductive line 50 is arranged as an electrical connecting member which constitutes the outward path 91 and the return path 92. The direct-current voltage Vdc is conducted through the inter-driver conductive line 50 and is supplied to all of the slave signal line drivers 20, 30, and 40, and the same is conducted through the inter-driver conductive line 50 and is returned to the master signal line driver 10.
Next, the operation of a voltage and a signal in the master signal line driver 10 will be described.
The input voltage VIN is input to the master signal line driver 10 via a connector 101, and is supplied to the direct-current voltage generation circuit 12. The direct-current voltage generation circuit 12 is a conversion circuit which converts the input voltage VIN, which is a direct-current voltage, into a direct-current voltage which is different from the input voltage VIN, and includes a logic power source 111, a panel power source 113, and a driver power source 115, for example.
The logic power source 111 is a power source which supplies a voltage to a logic circuit of the master signal line driver 10, and generates a logic voltage VL1 which is input to, for example, a timing controller (T-CON) 14 (corresponding to the host circuit 14 described above). The panel power source 113 is a power source which generates a voltage to be supplied to the display panel PNL, and outputs, for example, scanning line control voltages VGH and VGL, and the common potential VCOM. The driver power source 115 generates the direct-current voltage Vdc.
The input signal SIN, which is, for example, a synchronization signal of video data supplied from the outside, is input to the master signal line driver 10 via a connector 102, and is supplied to the timing controller 14. Note that as the timing controller 14, a computer or a central processing unit (CPU), etc., in which a processing function can be switched by an application may be used. The timing controller 14 is a logic circuit which generates a pulse signal for controlling output timing of various control signals. The timing controller 14 outputs, for example, a scanning line control signal Sgc and a signal line control signal Ssc which are synchronized with each other. The scanning line control signal Sgc is supplied to the scanning line driver GD via a connector 107, and controls the output timing of a scan voltage described with reference to
Further, the timing controller 14 inputs a comparison result Sd1 from the voltage comparator 13, and outputs the voltage control signal Sc1 to the gradation power source 11. That is, the timing controller 14 corresponds to a host circuit. Accordingly, the signal line driver 10 does not need to prepare a circuit block for arranging a host circuit. This means that upsizing of the signal line driver 10 or complication of a circuit can be prevented. The timing controller 14 reads an operating parameter stored in a writable memory (EEPROM) 120 at start-up, and starts the operation.
Since the inter-driver conductive line 50 is electrically connected to the master signal line driver 10 via a connector 108, the direct-current voltage Vdc and the voltage control signals Sc2 to Sc4 are output to the inter-driver conductive line 50 via the connector 108.
Note that each of the second signal line driver 20, the third signal line driver 30 and the fourth signal line driver 40 (that is, the slave signal line drivers) are similar in construction to the signal line driver 10 (that is, the master signal line driver) shown in
Next, the operation of the gradation power source will be described.
The gradation power source 11 includes a digital-to-analog conversion circuit 3 and a buffer amplifier 4. The buffer amplifier 4 includes operational amplifiers serving as voltage followers whose number corresponds to the number of gradations of an output voltage. The digital-to-analog conversion circuit 3 outputs the gradation voltage Vg1 of n-level gradation with reference to the analog voltage Va1. At this time, on the basis of the voltage control signal Sc1 input by way of a system different from the one of the analog voltage Va1, the digital-to-analog conversion circuit 3 adjusts each of gradation potentials V1 to Vn of the gradation voltage Vg1. For example, the voltage control signal Sc1 is a logic signal, and adjusts each of the gradation potentials V1 to Vn by a logic process within the digital-to-analog conversion circuit 3. Note that the gradation potentials V1 to Vn are buffered by the operational amplifiers of the buffer amplifier 4, respectively, and are output.
A gradation power source 11 shown in
The analog voltage Va1 and the voltage control signal Sc1 are input to the analog buffer 5. The analog buffer 5 is a voltage amplifier circuit, and can vary the resistance of a feedback loop according to the voltage control signal Sc1. Thereby, the analog buffer 5 adjusts the analog voltage Va1, and outputs an analog voltage which is different from the analog voltage Va1. In the example illustrated, the analog buffer 5 inputs the analog voltage Va4 to the digital-to-analog conversion circuit 3.
As described above, in the gradation power source 11 illustrated in
Next, the operation of the above-described gradation power sources 11 to 41 will be described with reference to a timing chart.
First, the operation in the master signal line driver m-SD will be described. At time t1, the direct-current voltage Vdc of the master signal line driver m-SD is raised. Simultaneously with that, the analog voltage Va1 of the master signal line driver m-SD is raised. This time, the analog voltage Va1 is equal to the direct-current voltage Vdc. Next, the gradation power source 11 starts to output the gradation voltage Vg1 after a lapse of output delay time TD1 from time t1. At this time, the analog voltage Va1 is input to the gradation power source 11 as an auxiliary voltage. The gradation power source 11 outputs the gradation voltage Vg1 with reference to the auxiliary voltage Va1 during an auxiliary operation period TM1 until the output of all the gradation voltages Vg1 to Vg4 is sufficiently stabilized. After that, at time t2 when the output of the gradation voltage Vg1 is stabilized, the voltage control signal Sc1 is input. In a generation operation period TM2 after time t2, a reference voltage of the gradation voltage Vg1 is reduced from the auxiliary voltage Va1 by an adjustment amount corresponding to VF1f+VF2f+VF3f, and becomes equivalent to the analog voltage Va4. That is, the following equation is satisfied:
Vg1=Va1−(VF1f+VF2f+VF3f)=Va4
Time t2 when the period is switched from the auxiliary operation period TM1 to the generation operation period TM2 corresponds to initialization time. Note that the adjustment amount corresponding to VF1f+VF2f+VF3f is the sum of the voltage drops caused in the outward path from the master signal line driver m-SD to the third slave signal line driver s3-SD. That is, the signal line drivers adjust their own gradation voltages such that they are less than or equal to the analog voltage Va4, which is the lowest analog voltage in these signal line drivers. Further, the adjustment amount is not particularly limited and may include margin α, as long as the adjustment makes the gradation voltages of all the signal line drivers in the generation operation period TM2 the same. That is, Vg1 may be expressed as follows:
Vg1=Va1−(VF1f+VF2f+VF3f+α)=Va4−α
Next, in the first slave signal line driver s1-SD, the analog voltage Va2 is reduced from the analog voltage Va1 because of the voltage drop VF1f caused by the inter-driver conductive line 50. That is, the following equation is satisfied:
Va2=Va1−VF1f
The gradation power source 21 starts to output the gradation voltage Vg2 after a lapse of output delay time TD2 from time t1. In the auxiliary operation period TM1, the gradation power source 21 outputs the gradation voltage Vg2 by using the analog voltage Va2 as the auxiliary voltage. At the initialization time t2, the voltage control signal Sc2 is input, and the gradation voltage Vg2 is reduced by an adjustment amount corresponding to VF2f+Vf3f. That is, the following equation is satisfied:
Vg2=Va1−(VF1f+VF2f+VF3f)=Va4
Note that as in the master signal line driver m-SD, a reference voltage of the gradation voltage Vg2 may include margin α, so that Vg2 may be equal to Va4−α (i.e., Vg2=Va4−α).
In the second slave signal line driver s2-SD, the analog voltage Va3 is expressed as Va3=Va1−(VF1f+VF2f) because of the voltage drop corresponding to VF1f+VF2f caused by the inter-driver conductive lines 50 and 60. In the auxiliary operation period TM1, the gradation power source 31 starts output after a lapse of output delay time TD3 from time t1, and outputs the gradation voltage Vg3 by using the analog voltage Va3 as the auxiliary voltage. After that, at the initialization time t2, the voltage control signal Sc3 is input, and gradation voltage Vg3 is expressed as follows:
Vg3=Va1−(VF1f+VF2f+VF3f)=Va4
Note that as in the master signal line driver m-SD, a reference voltage of the gradation voltage Vg3 may include margin α, so that Vg3 may be equal to Va4−α (i.e., Vg3=Va4−α).
In the third slave signal line driver s3-SD, the analog voltage Va4 is expressed as Va4=Va1−(VF1f+VF2f+VF3f) because of the voltage drop corresponding to VF1f+VF2f+VF3f caused by the inter-driver conductive lines 50 to 70. In the auxiliary operation period TM1, the gradation power source 41 starts output after a lapse of output delay time TD4 from time t1, and outputs the gradation voltage Vg4 by using the analog voltage Va4 as the auxiliary voltage. After that, at the initialization time t2, the voltage control signal Sc4 is input. However, in the example illustrated, the gradation voltage Vg4 is not adjusted, and the following equation is maintained:
Vg4=Va1−(VF1f+VF2f+VF3f)=Va4
In the third slave signal line driver s3-SD, the voltage control signal Sc4 may be omitted. Note that as in the master signal line driver m-SD, a reference voltage of the gradation voltage Vg4 may include margin α, so that Vg4 may be equal to Va4−α (i.e., Vg4=Va4−α).
As described above, the master signal line driver m-SD measures a difference of the direct-current voltage Vdc between the outward path 91 and the return path 92 at time t1 of power-on by the voltage comparator 13, inputs the comparison result Sd1 to the host circuit 14, and calculates the voltage drops VF1f to VF3F. Further, at the initialization time t2, because the voltage control signals Sc1 to Sc4 are supplied to gradation power sources 11 to 41, respectively, all of the gradation voltages Vg1 to Vg4 are equalized in the generation operation period TM2. Note that the output delay times TD1 to TD4 can be different values because they are caused by the performance errors of the respective signal line drivers. However, all of the output delay times TD1 to TD4 are shorter than the auxiliary operation period TM1. Note that the comparison result Sd1 may be updated regularly during the generation operation period TM2, and input to the host circuit 14. Here, the voltage control signals Sc1 to Sc4 may be input to the respective gradation power sources 11 to 41 regularly, on the basis of the updated comparison result Sd1, to adjust the gradation voltages Vg1 to Vg4. In this way, the display device DSP can correct a change in the analog voltages Va2 to Va4 caused by temporal change of the interconnection resistance or change of an environmental temperature, and continue adjusting the gradation voltages so that the respective gradation voltages Vg1 to Vg4 become the same.
As described above, in the auxiliary operation period TM1 before the voltage control signal Sc1 is output from the host circuit 14 to the gradation power source 11 within the master signal line driver 10, the display device DSP supplies auxiliary voltages to the gradation power sources 11, 21, 31, and 41 within the signal line drivers 10, 20, 30, and 40, respectively. Further, in the generation operation period TM2 when the gradation voltage Vg1 within the master signal line driver 10 is adjusted based on the voltage control signal Sc1, the voltage comparator 13 within the master signal line driver 10 compares the direct-current voltage Vdc which has been returned by way of the return path 92 with the direct-current voltage Vdc output to the outward path 91.
According to the present embodiment, the display device includes the outward path which outputs a direct-current voltage from the master signal line driver, and the return path which is electrically connected to and is contiguous with the outward path, and returns the direct-current voltage to the master signal line driver. Thus, even if the potential of the direct-current voltage of the outward path is different in each of the signal line drivers because of the interconnection resistance, for example, by comparing the direct-current voltage of the outward path with that of the return path, it is possible to calculate the potential of the direct-current voltage of the outward path or the return path in each of the signal line drivers.
Further, the display device includes the direct-current voltage generation circuit arranged in the master signal line driver, and the gradation power source arranged in each of the signal line drivers. Accordingly, the display device is capable of driving the gradation power sources of all the signal line drivers by one direct-current voltage output from the maser signal line driver. That is, the input timing of the reference voltage input to all of the signal line drivers can be controlled by an output timing of the direct-current voltage generation circuit of the master signal line driver.
Since the display device includes the voltage comparator and the host circuit within the master signal line driver, a difference between the analog voltages input to the respective gradation power sources can be calculated in the master signal line driver. That is, the display device can calculate a difference between gradation voltages generated by using the analog voltages. Since the gradation voltages are used to generate data signals which drive the division display areas, by correcting a difference in the calculated gradation voltages, it is possible to suppress a difference in level of the brightness caused between different division drive regions and non-uniformity in display.
The display device has the auxiliary operation period in which auxiliary voltages are supplied to the respective gradation power sources of the signal line drivers before the generation operation period in which the direct-current voltages of the outward path and the return path are compared. In the display device, a transitional period in which an overcurrent may flow overlaps the auxiliary operation period, and since the output of each of the gradation power sources is stabilized in the generation operation period, occurrence of latch-up can be suppressed.
As described above, according to the present embodiment, a display device capable of improving the display quality can be provided.
Further, in the display device, for example, the master signal line driver and at least one slave signal line driver are electrically connected by one inter-driver conductive line. That is, the display device achieves electrical connection by the outward path and the return path of a single system which are formed throughout all the signal line drivers. With such a structural example, it is possible to reduce a total line length of the outward path and the return path as compared to a structure in which the respective slave signal line drivers are electrically connected to the master signal line driver by separate outward and return paths, and a voltage loss by the interconnection resistance can be reduced.
Next, a modification of the present embodiment will be described. Also in various modifications which will be described below, an advantage similar to that of the above-described embodiment can be obtained.
The present modification is different from the structural example illustrated in
In the present modification, each of the signal line drivers 10 to 40 includes the direct-current voltage generation circuit DC/DC, the gradation power source GVG, the voltage comparator COMP, the host circuit HOST, a first switch SW1, a second switch SW2, and a third switch SW3. The first switch SW1 controls electrical connection between the outward path 91 and the return path 92. The second switch SW2 controls input from the return path 92 to the voltage comparator COMP. The third switch SW3 controls output from the direct-current voltage generation circuit DC/DC to the outward path 91. That is, control of the switches SW1 to SW3 determines which of the signal line drivers is to be set as the master signal line driver m-SD. Note that a control method and control timing of each of the switches SW1, SW2, and SW3 are not particularly limited, and the control may be digital or analog. In the case of analog control, on/off control of each of the switches SW1 to SW3 may be completed before the operation of the signal line driver SD. For example, each of the switches SW1 to SW3 is a DIP (Dual In-line Package) switch, and is fixed to the on state or off state when the signal line driver SD is incorporated into the display device DSP, and the switching of on (i.e., closed) and off (i.e., open) is not performed thereafter. In the case of digital control, on/off control of each of the switches SW1 to SW3 may be performed by a signal from the processor when the display device DSP is powered on, for example.
The state of each of the signal line drivers in the generation operation period TM2 after time t2 described with reference to
In the master signal line driver 10, a first switch 15 is open (off state). Further, a second switch 16 is closed (on state), so that direct-current voltages Vdc of the outward path 91 and the return path 92 are input to the voltage comparator 13, and the comparison result Sd1 is input to the host circuit 14. Furthermore, a third switch 17 is closed (on state), and the direct-current voltage generation circuit 12 outputs the direct-current voltage Vdc to the outward path 91.
In the first slave signal line driver 20 and the second slave signal line driver 30, first switches 25 and 35 are open (off state). Also, second switches 26 and 36 are open (off state), so that the direct-current voltage Vdc of the return path 92 is not input to voltage comparators 23 and 33. Accordingly, the voltage comparators 23 and 33 do not function. Host circuits 24 and 34 also do not function. Furthermore, third switches 27 and 37 are open (off state), so that direct-current voltage generation circuits 22 and 32 do not input a direct-current voltage to the outward path 91.
In the third slave signal line driver 40, a first switch 45 is closed (on state), so that the outward path 91 and the return path 92 are electrically connected to each other. Note that a second switch 46 and a third switch 47 are open (off state) as in the other slave signal line drivers 20 and 30. Accordingly, a voltage comparator 43 and a host circuit 44 do not function.
As described above, the master signal line driver 10 and the slave signal line drivers 20, 30, and 40 may include the voltage comparators (COMP) 13, 23, 33, and 43, the direct-current voltage generation circuits (DC/DC) 12, 22, 32, and 42, and the gradation power sources (GVG) 11, 21, 31, and 41, respectively.
Also, in the present modification, the master signal line driver 10 and the slave signal line drivers 20, 30, and 40 include the host circuits (HOST) 14, 24, 34, and 44, the voltage comparators (COMP) 13, 23, 33, and 43, the direct-current voltage generation circuits (DC/DC) 12, 22, 32, and 42, and the gradation power sources (GVG) 11, 21, 31, and 41, respectively. The voltage comparator 13 within the master signal line driver 10 compares the direct-current voltage Vdc returned via the return path 92 with the direct-current voltage Vdc output to the outward path 91, and the host circuit 14 within the master signal line driver 10 transmits the voltage control signals Sc1, Sc2, Sc3, and Sc4 for controlling the gradation voltages Vg1, Vg2, Vg3, and Vg4 generated in the respective gradation power sources 11, 21, 31, and 41 to the signal line drivers 10, 20, 30, and 40, on the basis of the comparison result Sd1 of the comparator 13.
Further, the host circuits (HOST) 14, 24, 34, and 44 within the respective signal line drivers 10, 20, 30, and 40 may control the input to the voltage comparators (COMP) 13, 23, 33, and 43, and the output from the direct-current voltage generation circuits (DC/DC) 12, 22, 32, and 42 within the respective signal line drivers 10, 20, 30, and 40.
In the modification as described above, since all of the signal line drivers have the same structure, the master signal line driver and the slave signal line driver can use the same member. Accordingly, procurement of members for the display device DSP can be simplified. Also, there is no risk of mixing up the master signal line driver and the slave signal line driver in a manufacturing process. That is, a mounting error in the manufacturing process can be prevented.
The present modification is different from the structural example illustrated in
The second slave signal line driver 30 and the third slave signal line driver 40 constitute a first system. The inter-driver conductive lines 60 and 70 correspond to the inter-driver conductive lines of the first system. The first slave signal line driver 10 constitutes a second system. The inter-driver conductive line 50 corresponds to an inter-driver conductive line of the second system. The outward path 91 of the first system is formed throughout the inter-driver conductive line 60 of the first system, the slave signal line driver 30 of the first system, the inter-driver conductive line 70 of the first system, and the slave signal line driver 40 of the first system, and is electrically connected to the return path 92 of the first system in the slave signal line driver 40 of the first system. The return path 92 of the first system is formed throughout the slave signal line driver 40 of the first system, the inter-driver conductive line 70 of the first system, and the slave signal line driver 30 of the first system. An outward path 94 of the second system is formed throughout the inter-driver conductive line 50 of the second system and the slave signal line driver 10 of the second system, and is electrically connected to a return path 95 of the second system in the slave signal line driver 10 of the second system. The return path 95 of the second system is formed throughout the slave signal line driver 10 of the second system and the inter-driver conductive line 50 of the second system. Note that bus lines are separately provided as a bus line 93 of the first system and a bus line 96 of the second system.
The direct-current voltage generation circuit 22 outputs a direct-current voltage Vdc1 of the first system to the outward path 91 of the first system. Also, the direct-current voltage generation circuit 22 outputs a direct-current voltage Vdc2 of the second system to the outward path 94 of the second system. The analog voltages Va2 to Va4 are supplied from the direct-current voltage Vdc1 of the first system. The analog voltage Va1 is supplied from the direct-current voltage Vdc2 of the second system. The voltage comparator 23 sequentially performs comparison between the direct-current voltages Vdc1 in the outward path 91 and the return path 92 of the first system, and comparison between the direct-current voltages Vdc2 in the outward path 94 and the return path 95 of the second system, and inputs the respective comparison results to the host circuit 24. The host circuit 24 transmits the voltage control signals Sc2 to Sc4 via the bus line 93 of the first system. The host circuit 24 transmits the voltage control signal Sc1 via the bus line 96 of the second system. In the example illustrated, although the gradation power source 21 of the master signal line driver 20 is electrically connected to the first system, it may be electrically connected to the second system.
As described above, more than one slave signal line driver, i.e., the slave signal line drivers 10, 30, and 40, are provided, and such slave signal line drivers constitute the first system and the second system. Further, as an electrical connecting member between the master signal line driver 20 and the slave signal line drivers 30 and 40 which belong to the first system, the first system inter-driver conductive line 60 is arranged. Furthermore, as an electrical connecting member between the master signal line driver 20 and the slave signal line driver 10 which belongs to the second system, the second system inter-driver conductive line 50 is arranged. The first system direct-current voltage Vdc1, which is output from the master signal line driver 20 to the first system, is conducted through the first system inter-driver conductive line 60 and is supplied to both of the slave signal line drivers 30 and 40 belonging to the first system, and the same is conducted through the first system inter-driver conductive line 60 and is returned to the master signal line driver 20. The second system direct-current voltage Vdc2, which is output from the master signal line driver 20 to the second system, is conducted through the second system inter-driver conductive line 50 and is supplied to the slave signal line driver 10 belonging to the second system, and the same is conducted through the second system inter-driver conductive line 50 and is returned to the master signal line driver 20.
In the modification as described above, the outward path of the first system and the outward path of the second system are shorter than the outward path of the structural example illustrated in
The present modification is different from the structural example illustrated in
In the present modification, the inter-driver conductive line 80 is arranged outside the first scanning line driver 1 with reference to the display area DA. The inter-driver conductive line 80 may be opposed to the first scanning line driver 1 in a normal direction of the display panel PNL, for example, and disposed outside the first scanning line driver circuit GIC1 with reference to the display area DA. The inter-driver conductive line 60 may also be opposed to the second scanning line driver 2, for example, and disposed outside the second scanning line driver circuit GIC2.
As described above, the display panel PNL may include the scanning line driver circuits GIC1 and GIC2 outside the display area DA, and the outward path 91 or the return path 92 may be arranged outside the scanning line driver circuits GIC1 and GIC2.
In the present modification, the return path 92 is constituted by the inter-driver conductive line 80. That is, the return path 92 is electrically connected to the outward path 91 in the third slave signal line driver 40, and is formed throughout the third slave signal line driver 40, the inter-driver conductive line 80, and the master signal line driver 10. The return path 92 may be returned to the master signal line driver 10 in a different route from the outward path 91.
As described above, as electrical connecting members between the master signal line driver 10 and the slave signal line drivers 20, 30, and 40, a first inter-driver conductive line, i.e., the inter-driver conductive line 50, and a second inter-driver conductive line, i.e., the inter-driver conductive line 80, may be arranged, and the direct-current voltage Vdc may be supplied to all of the slave signal line drivers 20, 30, and 40 by conducting through the first inter-driver conductive line 50, and returned to the master signal line driver 10 by conducting through the second inter-driver conductive line 80.
The present modification is different from the structural example illustrated in
As described above, the display panel PNL may include the scanning line driver circuit GIC2 outside the display area DA, and the outward path 91 or the return path 92 may be arranged on the upper side of the scanning line driver circuit GIC2.
The present modification is different from the structural example illustrated in
As described above, the display panel PNL may include the scanning line driver circuit GIC2 outside the display area DA, and the outward path 91 or the return path 92 may pass through the interior of the scanning line driver circuit GIC2.
Also, the outward path 91 or the return path 92 may be formed on a substrate which constitutes the display panel PNL.
According to such a modification, the outward path and the return path can be formed simultaneously with the other conductive lines of the display panel such as a scanning line and a signal line. Also, since a circuit board, a cable, and the like which constitute the outward path and the return path become unnecessary, as a result of reduction of members and cut-down in manufacturing man-hours, the manufacturing costs of the display device can be reduced.
Each of the signal line drivers 10 to 40 includes a main substrate MB, a drive substrate DB, and a flexible printed circuit FPC. The main substrate MB is connected to the drive substrate DB, the drive substrate DB is connected to the flexible printed circuit FPC, and the flexible printed circuit FPC is connected to the display panel PNL. On the main substrate MB, the direct-current voltage generation circuit DC/DC and the timing controller T-CON are arranged. The first signal line driver circuit SIC1 to the fourth signal line driver circuit SIC4 are mounted on the corresponding flexible printed circuits FPC, respectively. Each of the inter-driver conductive lines 60 and 70 is arranged between the adjacent drive substrates DB.
Here, by taking the first signal line driver 10 corresponding to the master signal line driver as an example, the structure of the signal line driver in the present modification will be described.
The first signal line driver 10 includes the gradation power source 11, the direct-current voltage generation circuit 12, the voltage comparator 13, and the timing controller (host circuit) 14 on a main substrate 130. The gradation power source 11 inputs the gradation voltage Vg1 to the first signal line driver circuit SIC1 provided in a flexible printed circuit 150 through a drive substrate 140. The host circuit 14 outputs address data allocated to the first signal line driver 10 and the voltage control signal Sc1 to the first signal line driver circuit SIC1 via the bus line 93. The outward path 91, the return path 92, and the bus line 93 pass through the drive substrate 140 and the inter-driver conductive line 50, and extend to the other signal line drivers.
From the structural example and the modifications thereof, the following is understood. That is, in the display device DSP, the master signal line driver 10, for example, includes the voltage comparator 13, the host circuit 14 which receives the comparison result Sd1 from the voltage comparator 13, the direct-current voltage generation circuit 12, and the gradation power source 11. The slave signal line driver includes the first slave signal line driver 20, the second slave signal line driver 30, and the third slave signal line driver 40. The first slave signal line driver 20, the second slave signal line driver 30, and the third slave signal line driver 40 include at least the gradation power sources 21, 31, and 41, respectively. As the electrical connecting member, a first inter-driver conductive line, i.e., the inter-driver conductive line 50, is provided between the master signal line driver 10 and the first slave signal line driver 20. As the electrical connecting member, a second inter-driver conductive line, i.e., the inter-driver conductive line 60, is provided between the first slave signal line driver 20 and the second slave signal line driver 30. As the electrical connecting member, a third inter-driver conductive line, i.e., the inter-driver conductive line 70, is provided between the second slave signal line driver 30 and the third slave signal line driver 40. The first inter-driver conductive line 50, the second inter-driver conductive line 60, and the third inter-driver conductive line 70 constitute the outward path 91 and the return path 92. The first inter-driver conductive line 50, the second inter-driver conductive line 60, and the third inter-driver conductive line 70 also constitute the bus line 93 for allowing the host circuit 14 to transmit the voltage control signals Sc2, Sc3, and Sc4 to the gradation power sources 21, 31, 41 of the first slave signal line driver 20, the second slave signal line driver 30, and the third slave signal line driver 40, respectively.
Further, for example, the master signal line driver 10, the first slave signal line driver 20, the second slave signal line driver 30, and the third slave signal line driver 40 include the main substrates MB, the drive substrates DB, and the signal line driver circuits SIC1, SIC2, SIC3, and SIC4, respectively. The voltage comparator 13, the host circuit 14, the direct-current voltage generation circuit 12, and the gradation power source 11 are provided on the main substrate MB. Each of the first inter-driver conductive line 50, the second inter-driver conductive line 60, and the third inter-driver conductive line 70 is arranged between the adjacent drive substrates DB.
Furthermore, for example, each of the master signal line driver 10, the first slave signal line driver 20, the second slave signal line driver 30, and the third slave signal line driver 40 has an address, and the host circuit 14 specifies the address via the bus line 93 to enable transmission of the voltage control signals Sc1, Sc2, Sc3, and Sc4 to the signal line drivers.
Moreover, for example, the second inter-driver conductive line 60 is longer than the first inter-driver conductive line 50 and the third inter-driver conductive line 70.
As has been described above, according to the present embodiment, a display device capable of improving the display quality can be provided.
It should be understood that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and scope of the present subject matter and without diminishing its intended advantages. It is therefore intended that such changes and modifications be covered by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-201973 | Oct 2015 | JP | national |
This application is a continuation application of U.S. patent application Ser. No. 15/291,739, filed on Oct. 12, 2016, which application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-201973, filed Oct. 13, 2015, the entire contents of which are incorporated herein by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 7898514 | Kim | Mar 2011 | B2 |
| 8823616 | Kim | Sep 2014 | B2 |
| 9607560 | Kim | Mar 2017 | B2 |
| 20070247409 | Nishimura et al. | Oct 2007 | A1 |
| 20150124006 | Ura | May 2015 | A1 |
| 20150248865 | Lim et al. | Sep 2015 | A1 |
| 20150302815 | Marushima | Oct 2015 | A1 |
| 20150356951 | Wang | Dec 2015 | A1 |
| 20150364105 | Pyun | Dec 2015 | A1 |
| 20160133178 | Oh | May 2016 | A1 |
| 20160133212 | Jung | May 2016 | A1 |
| 20170069268 | Tokunaga | Mar 2017 | A1 |
| 20170097649 | Lee | Apr 2017 | A1 |
| 20170193954 | Wu | Jul 2017 | A1 |
| 20180020540 | Nakaminami | Jan 2018 | A1 |
| Number | Date | Country |
|---|---|---|
| 6-230338 | Aug 1994 | JP |
| 7-302066 | Nov 1995 | JP |
| 3110339 | Nov 2000 | JP |
| 2001-281686 | Oct 2001 | JP |
| 2003-216127 | Jul 2003 | JP |
| 2005-221527 | Aug 2005 | JP |
| 2007-286525 | Nov 2007 | JP |
| 2010-026138 | Feb 2010 | JP |
| 2015-079187 | Apr 2015 | JP |
| 0157839 | Aug 2001 | WO |
| Entry |
|---|
| Japanese Office Action dated Feb. 5, 2019 in corresponding Japanese Application No. 2015-201973. |
| Number | Date | Country | |
|---|---|---|---|
| 20190122632 A1 | Apr 2019 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15291739 | Oct 2016 | US |
| Child | 16223253 | US |
