Patent Application
20080018578
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The storage capacitors CSC in Mth and M+1th rows of pixels share two supplemental lines. For example, in the first row of pixels, such as PU11˜PU13, control terminals of the transistors T0 are coupled to the first gate line GL1, first terminals of the transistors T0 are coupled to the data lines DL1˜DL3 respectively, the storage capacitors in the odd-numbered pixels, such as PU11 and PU13, are coupled to the supplemental line VSC1, and the storage capacitors CSC in the even-numbered pixel, such as PU12 is coupled to the supplemental line VSC2. In the second row of pixels, such as PU21˜PU23, control terminals of the transistors T0 are coupled to the second gate line GL2, first terminals of the transistors T0 are coupled to the data lines DL2˜DL4 respectively, the storage capacitors CSC in the odd-numbered pixels, such as PU21 and PU23, are coupled to the supplemental line VSC2, and the storage capacitors CSC in the even-numbered pixels, such as PU22, is coupled to the supplemental line VSC1.
In the third row of pixels, such as PU31˜PU33, control terminals of the transistors T0 are coupled to the third gate line GL3, first terminals of the transistors T0 are coupled to the data lines DL1˜DL3 respectively, the storage capacitors in the odd-numbered pixels, such as PU31 and PU33, are coupled to the supplemental line VSC4, and the storage capacitors CSC in the even-numbered pixel, such as PU32, are coupled to the supplemental line VSC3. In the fourth row of pixels, such as PU41˜PU43, control terminals of the transistors T0 are coupled to the second gate line GL4, first terminals of the transistors T0 are coupled to the data lines DL2˜DL4 respectively, the storage capacitors CSC in the odd-numbered pixels, such as PU41 and PU43, are coupled to the supplemental line VSC3, and the storage capacitors CSC in the even-numbered pixels, such as PU42, is coupled to the supplemental line VSC4.
The driver IC 30 directs the vertical driver 10 and the horizontal driver 20 to drive the pixels in the pixel array 40. For example, the horizontal driver 20 provides data signals, such as voltage signals, to the pixels in the pixel array 40 through the data lines DL1˜DL4 when gate lines GL1˜GL5 are scanned in sequence by the vertical driver 10.
In this embodiment, the horizontal driver 20 provides first (negative) polarity data through the data lines DL1 and DL3 and second (positive) polarity data through the data lines DL2 and DL4 in a Nth frame, and provides the second (positive) polarity data through the data lines DL1 and DL3 and the first (negative) polarity data through the data lines DL2 and DL4 in a N+1th frame. Due to connection of the pixels in the pixel array 40, the negative polarity data on the data lines DL1 and DL3 can be output to the pixels PU11, PU13, PU22, PU31, PU33 and PU42, and the positive polarity data on the data lines DL2 and DL4 can be output to pixels PU12, PU21, PU23, PU32, PU41 and PU43 during the Nth frame. During the N+1th frame, the positive polarity data on the data lines DL1 and DL3 can be output to the pixels PU11, PU13, PU22, PU31, PU33 and PU42, and the negative polarity data on the data lines DL2 and DL4 can be output to pixels PU12, PU21, PU23, PU32, PU41 and PU43. Thus, pixels in the display device 100 can be driven using dot-inversion.
The vertical driver 10 scans the gate lines GL1˜GL5 in sequence and provides voltage signals to the supplemental lines VSC1˜VSC4 during a frame period. The vertical driver 10 further switches the polarity of the voltage signals on the supplemental lines VSCn and VSCn+1 after the corresponding two gate lines are scanned in sequence, such that the polarity on the supplemental lines VSCn and VSCn+1 is changed.
The signal supply circuit 12 generates voltage signals with negative polarity and positive polarity, changing the polarity of the voltage signals on the supplemental lines VSC1˜VSC4 according to the output pulses out2 and out4 from even-numbered shift registers VSR2 and VSR4. The signal supply circuit 12 comprises a plurality of generation units 121 and 122, each comprising a D-type flip-flop DFF, an inverter NV, and four transistors T1˜T4.
In generation unit 121, the D-type flip-flop DFF comprises an input terminal coupled to the output pulses out2 from the shifter register VSR2, and the inverter INV comprises an input terminal coupled to an output terminal of the D-type flip-flop DFF. Transistor T1 comprises a control terminal coupled to the output terminal of the D-type flip-flop DFF, a first terminal coupled to a logic signal VSCL, and a second terminal coupled to the supplemental line VSC1. The transistor T2 comprises a control terminal coupled to the output terminal of the inverter INV, a first terminal coupled to a logic signal VSCH, and a second terminal coupled to the supplemental line VSC1. The transistor T3 comprises a control terminal coupled to the output terminal of the inverter INV, a first terminal coupled to the logic signal VSCL, and a second terminal coupled to the supplemental line VSC2. The transistor T4 comprises a control terminal coupled to the output terminal of the D-type flip-flop DFF, a first terminal coupled to the logic signal VSCH, and a second terminal coupled to the supplemental line VSC2. For example, the logic signal VSCL may be a negative polarity voltage signal, and the logic signal VSCH may be a positive polarity voltage signal.
Generation unit 122 is similar to the generation unit 121, except that the input terminal of the D-type flip-flop DFF is coupled to the output pulse out4 of the shift register VSR4, second terminals of the transistors T1 and T2 are coupled to the supplemental line VSC3 and second terminals of the transistors T3 and T4 are coupled to the supplemental line VSC4.
For example, in the beginning, the transistors T1 and T4 may be turned on by the output of the D-type flip-flop DFF and the transistors T2 and T3 may be turned off by the output of the inverter INV in the generation units 121 and 122, such that the logic signal VSCL (negative polarity) serves as signals SVSC1 and SVSC3, output to the supplemental lines VSC1 and VSC3 respectively and the logic signal VSCH (positive polarity) serves as the signals SVSC2 and SVSC4, output to the supplemental lines VSC2 and VSC4 respectively.
When receiving the output pulse out2, the D-type flip-flop DFF in the generation unit 121 inverts output signal thereof, such that transistors T1 and T4 are turned off and transistors T2 and T3 are turned on. Thus, the logic signal VSCH (positive polarity) serves as the signal SVSC1, output to the supplemental line VSC1, and the logic signal VSCL (negative polarity) serves as the signal SVSC2, output to the supplemental line VSC2. Similarly, when receiving the output pulse out4, the D-type flip-flop DFF in the generation unit 122 inverts output signal thereof, such that the transistors T1 and T4 are turned off and the transistors T2 and T3 are turned on. Thus, the logic signal VSCH (positive polarity) serves as the signal SVSC3, output to the supplemental line VSC3, and the logic signal VSCL (negative polarity) serves as the signal SVSC4, output to the supplemental line VSC4. It should be noted that the polarity of the signals SVSC1 and SVSC2 should be inverted after the gate line GL2 is scanned. Similarly, the polarity of the signals SVSC3 and SVSC4 should be inverted after the gate line GL4 is scanned, and so on.
In the invention, two rows of pixels in the display device 100 share a pair of signal lines, for example, the first and second rows of pixels share supplemental lines VSC1 and VSC2, and third and fourth rows of pixels share supplemental lines VSC3 and VSC4 and so on. Namely, in the display device 100, one row of pixels requires one supplemental line VSC and conductive lines on the pixel array 40 is reduced, such that the display device 100 has a higher aperture ratio. Furthermore, the display device 100 can be driven by dot-inversion, polarity switching on the data lines is reduced, and thus, power consumption can be reduced.
Electronic device 200 comprises a housing 110, a display device 100 and a power supply 120, although it is to be understood that various other components can be included, not shown or described here for ease of illustration and description. In operation, the power supply 120 powers the display device 100 to display color images.
While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
