Display drive integrated circuit and method for generating system clock signal

Abstract

A display drive integrated circuit is for driving a display panel. The display drive integrated circuit includes a division rate output unit which outputs as a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number, and a system clock generating unit which generates a system clock signal by dividing the dot clock signal using the division rate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and advantages of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a conventional display device;

FIG. 2 is a block diagram of a display drive integrated circuit for generating a system clock signal according to an embodiment of the present invention;

FIG. 3A is a timing diagram for describing the counting of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal;

FIG. 3B is a table illustrating examples of a division rate corresponding to the bit value of a total number of clock cycles of a dot clock signal, excluding the lower K bits thereof;

FIG. 4 is a timing diagram for describing a process of generating system clock signals having various frequencies by using various division rates, according to an embodiment of the present invention;

FIG. 5 is a flowchart for describing a method of generating a system clock signal according to an embodiment of the present invention; and

FIG. 6 is a table illustrating division rates obtained by dividing by 16 the total number of clock cycles of dot clock signals having various frequencies.

Claims

1. A display drive integrated circuit for driving a display panel, comprising: a division rate output unit which outputs as a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number; anda system clock generating unit which generates a system clock signal by dividing the dot clock signal using the division rate.

2. The display drive integrated circuit of claim 1, wherein the division rate output unit comprises: a counter which counts the clock cycles of the dot clock signal during a clock cycle of the horizontal synchronization signal; anda division rate output device which outputs the division rate corresponding to the quotient obtained by dividing by M the total counted number of clock cycles of the dot clock signal.

3. The display drive integrated circuit of claim 2, wherein M=2K, where K is a natural number.

4. The display drive integrated circuit of claim 2, wherein the total counted number of dot clock signals is output as L bits by the counter, and wherein the division rate output device outputs L−K bits as the division rate by excluding lower K bits from the L bits output by the counter, where L and K are natural numbers, and K is less than L.

5. The display drive integrated circuit of any one of claims 3 and 4, wherein M=16 and K=4.

6. The display drive integrated circuit of claim 2, wherein, when the quotient obtained by dividing by M the total number of clock cycles of the dot clock signal is an odd number, the division rate output device outputs as the division rate a value obtained by adding 1 to the quotient or subtracting 1 from the quotient, and when the quotient obtained by dividing by M the total number of clock cycles of the dot clock signal is an even number, the division rate output device outputs the quotient as the division rate.

7. The display drive integrated circuit of claim 2, wherein, when the quotient obtained by dividing by M the total number of clock cycles of the dot clock signal is an even number, the division rate output device outputs as the division rate a value obtained by adding 1 to the quotient or subtracting 1 from the quotient, and when the quotient obtained by dividing by M the total number of clock cycles of the dot clock signal is an odd number, the division rate output device outputs the quotient as the division rate.

8. The display drive integrated circuit of claim 1, wherein the system clock generating unit generates system clock signals having various frequencies by dividing the dot clock signal by an integral multiple of the division rate.

9. The display drive integrated circuit of claim 1, wherein the horizontal synchronization signal has a constant frequency.

10. A method of generating a system clock signal for a display drive integrated circuit which drives a display panel, the method comprising: outputting a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number; andgenerating the system clock signal by dividing the dot clock signal using the division rate.

11. The method of claim 10, wherein the outputting of the division rate comprises: counting the total number of clock cycles of the dot clock signal during the clock cycle of the horizontal synchronization signal; andoutputting the division rate corresponding to the quotient obtained by dividing the total number of clock cycles of the dot clock signal by M.

12. The method of claim 11, wherein M=2K, where K is a natural number.

13. The method of claim 11, wherein the total counted number of dot clock signals is output as L bits, and wherein L−K bits are output as the division rate by excluding lower K bits from the L bits, where L and K are natural numbers, and K is less than L.

14. The method of any one of claims 12 and 13, wherein M=16 and K=4.

15. The method of claim 11, wherein, when the quotient obtained by dividing by M the total number of clock cycles of the dot clock signal is an odd number, the division rate is output as a value obtained by adding 1 to the quotient or subtracting 1 from the quotient, and when the quotient obtained by dividing by M the total number of clock cycles of the dot clock signal is an even number, the quotient is output as the division rate.

16. The method of claim 11, wherein, when the quotient obtained by dividing by M the total number of clock cycles of the dot clock signal is an even number, the division rate is output as a value obtained by adding 1 to the quotient or subtracting 1 from the quotient, and when the quotient obtained by dividing by M the total number of clock cycles of the dot clock signal is an odd number, the quotient is output as the division rate.

17. The method of claim 10, wherein the generating of the system clock signal comprises generating system clock signals having various frequencies by dividing the dot clock signal using integral multiples of the division rate.

18. The method of claim 10, wherein the horizontal synchronization signal has a constant frequency.

19. The method of claim 10, wherein a vertical synchronization signal applied to the display drive integrated circuit has a constant frequency.