BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display driver and a display driving method, and particularly relates to a display driver and a display driving method which can avoid thermal energy generation via pre-charging.
2. Description of the Prior Art
A driving chip for a LCD (liquid crystal display) always comprises two main parts: a source driver and a gate driver. The gate driver controls turning on/off operations for the TFT (thin film transistor) in the LCD. Also, the source driver transmits image data (the gray level necessary for displaying an image) to the LCD after the TFT is conductive.
FIG. 1 is a circuit diagram illustrating a source driver for prior art. As shown in FIG. 1, the source driver 100 comprises an amplifier OP1 and a switch device SW1. The equivalent resistor R1 and the equivalent capacitor C1 indicate the equivalent resistance and the equivalent capacitance for the LCD. The amplifier OP1 outputs the image data signal IS1 to the LCD. However, for such structure, if an output terminal of the amplifier OP1 is pulled up or pulled down to a voltage that the image data needs (ex. VT1 or VT2 in FIG. 2), all current generated by the pulling up or pulling down operation must flow through the resistor for the amplifier OP1 itself and the switch device SW1 at the output terminal of the amplifier OP1. Therefore, larger thermal energy is generated.
SUMMARY OF THE INVENTION
Therefore, one objective of the present invention is to generate a display driver that can generate less thermal energy.
Another objective of the present invention is to provide a display driving method that can generate less thermal energy.
One embodiment of the present invention discloses a display driver, which comprises: a first predetermined voltage level providing apparatus, for providing a first predetermined voltage level group comprising at least one first predetermined voltage level; a first image data providing apparatus, for outputting a first image data; and a detection controlling circuit, for determining if an output terminal of the first image data providing apparatus is pre-charged to the first predetermined voltage level according to a relation between an absolute value of a voltage level of the first image data and an absolute value of the first predetermined voltage level.
Another embodiment of the present invention discloses a display driver, which comprises: a first predetermined voltage level providing apparatus, for providing a first predetermined voltage level group comprising at least one first predetermined voltage level; a second predetermined voltage level providing apparatus, for providing a second predetermined voltage level group comprising at least one second predetermined voltage level, wherein a polarity of the second predetermined voltage level is opposite to which of the first predetermined voltage level, or an absolute value of the second predetermined voltage level is smaller than which of the first predetermined voltage level; a first image data providing apparatus, for outputting a first image data; and a detection controlling circuit, for determining if an output terminal of the first image data providing apparatus is pre-charged to the second predetermined voltage level according to a relation between an absolute value of a voltage level of the first image data and an absolute value of the first predetermined voltage level.
At least one display driving method can be acquired according to above-mentioned embodiments. The detail steps thereof are omitted for brevity here.
In view of above-mentioned embodiments, the output terminal of the image data providing apparatus can be pre-charged to a predetermined level before the image data providing apparatus outputs the data according to the characteristic of the image data. By this way, the current generated via the charging operation can only flow through a switch rather than flow through a plurality of resistors such as the prior art, thus the generation for thermal energy can be decreased. Also, the charge sharing operation can be performed via the detection controlling circuit, even the polarity inversing is not performed. Thereby not only the power can be saved but also the range for pre-charging or charging can be decreased, such that the generation for thermal energy can be decreased as well.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram illustrating a source driver for prior art.
FIG. 2 is a schematic diagram illustrating the operation for the source driver shown in FIG. 1.
FIG. 3 is a circuit diagram illustrating a single channel source driver according to one embodiment of the present invention.
FIG. 4-FIG. 31 are schematic diagrams illustrating the operation for the single channel source driver according to one embodiment of the present invention when the single channel source driver performs polarity inversing.
FIG. 32-FIG. 37 are schematic diagrams illustrating the operation for the single channel source driver according to one embodiment of the present invention when the single channel source driver does not perform polarity inversing.
FIG. 38 is a circuit diagram illustrating a source driver according to another embodiment of the present invention.
FIG. 39 is a schematic diagram illustrating the operation for the two channel source driver according to one embodiment of the present invention when the two channel source driver performs polarity inversing.
FIG. 40 is a schematic diagram illustrating the operation for the two channel source driver according to one embodiment of the present invention when the two channel source driver does not perform polarity inversing but performs a charge sharing operation.
FIG. 41 and FIG. 42 are schematic diagrams illustrating the operation for the two channel source driver according to one embodiment of the present invention when the two channel source driver does not perform polarity inversing.
FIG. 43-FIG. 45 are source drivers according different embodiments of the present invention, which have detection controlling circuits at different locations.
FIG. 46 is a flow chart illustrating a display driving method according to one embodiment of the present invention.
DETAILED DESCRIPTION
FIG. 3 is a circuit diagram illustrating a single channel source driver 300 according to one embodiment of the present invention. As shown in FIG. 3, the single channel source driver 300 comprises: a first predetermined voltage level providing apparatus 301 (an amplifier in this example), a predetermined voltage level providing apparatus 303, a predetermined voltage level providing apparatus 305 and a detection controlling circuit 307. The first image data providing apparatus 301 outputs a first image data IS1. The predetermined voltage level providing apparatus 303 provides a high predetermined voltage level VPH, and the predetermined voltage level providing apparatus 305 provides a low predetermined voltage level VPL. The polarity of the high predetermined voltage level VPH is opposite to which of the low predetermined voltage level VPL. For example, the high predetermined voltage level VPH is +1.8V, and the low predetermined voltage level VPH is −1.8V (not limited). The detection controlling circuit 307 determines if an output terminal of the first image data providing apparatus 301 is pre-charged to the high predetermined voltage level VPH or the low predetermined voltage level VPL (i.e. control the switches of the predetermined voltage level providing apparatus 303 or the predetermined voltage level providing apparatus 305) according to a relation between a voltage level of the first image data IS1 and the high predetermined voltage level VPH or the low predetermined voltage level VPL. Please note the source driver 300 is not limited to comprise both the high predetermined voltage level VPH and the low predetermined voltage level VPL. The source driver 300 can comprise only one of the high predetermined voltage level VPH and the low predetermined voltage level VPL. Additionally, the detection controlling circuit 307 can further determine if an output terminal of the first image data providing apparatus 301 is pre-charged to the high predetermined voltage level VPH, the low predetermined voltage level VPL or the reference voltage level Vref according to a relation between a voltage level of the first image data IS1 and the reference voltage level Vref. Many circuits can be applied for the detection controlling circuit 307. For example, the detection controlling circuit 307 can comprise a plurality of logic gates such that the detection controlling circuit 307 can automatically generate different control signals to perform the control operation according to received signals. Alternatively, firmware can be written to a device such as the micro processor to perform the control operation. Besides, the predetermined voltage level providing apparatus 303 is not limited to provide a single voltage level, it can provide a voltage level group comprising at least one high predetermined voltage level VPH. Similarly, the predetermined voltage level providing apparatus 305 is not limited to provide a single voltage level, it can provide a single voltage level comprising at least one low predetermined voltage level VPL.
The operation for the source driver 300 is described for more detail as below. In a LCD, the polarities of the liquid crystal devices are sometimes inversed for avoid breaking for the liquid crystal devices. In such situation, the image data level varies from positive to negative, or negative to positive. FIG. 4-FIG. 31 are schematic diagrams illustrating the operation for the single channel source driver according to one embodiment of the present invention when the single channel source driver performs polarity inversing. In the following embodiment, the high predetermined voltage level VPH is positive and the low predetermined voltage level VPL. Also, the reference voltage level Vref, which can be 0 or other values, is between the high predetermined voltage level VPH and the low predetermined voltage level VPL. The device for providing the reference voltage level Vref shown in FIG. 3 is only for example. Persons skilled in the art can easily understand other structures for providing the reference voltage level Vref according to the teaching of the present invention while processing image data. Please note the source driver of the present invention can only comprise one of the reference voltage level Vref, the high predetermined voltage level VPH, and the low predetermined voltage level VPL.
The embodiments shown in FIG. 4 to FIG. 31 comprise different characteristics, which comprise: which voltage is the first predetermined voltage for determining if pre-charging operation should be performed or not? (can be one of the high predetermined voltage level VPH, the low predetermined voltage level VPL and the reference voltage level Vref); which voltage is the output terminal of the source driver pre-charged to, it can be the first predetermined voltage level or the second predetermined voltage level different; if the output terminal is charged to another voltage after pre-charged to the first predetermined voltage level or the second predetermined voltage level, and then charged to a target voltage level; the value of the target voltage level VT.
In the embodiment of FIG. 4, the voltage level for the first image data IS1 is positive, and the absolute value thereof is larger than which of the high predetermined voltage level VPH. Also, the voltage level for the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore the voltage level which is pre-charged to may be the voltages between the first image data IS1 and the target voltage level VT. That is, the high predetermined voltage level VPH, the low predetermined voltage level VPL, or the reference voltage level Vref. Please note, the voltage level which is pre-charged to can vary corresponding to the target voltage level VT. For example, the voltage level which is pre-charged to can be determined according to “how to generate minimum thermal energy for the switch device SW1 in FIG. 1”, but not limited. For example, of the target voltage level VT is between the reference voltage level Vref and the low predetermined voltage level VPL, it does not need to pre-charge the output terminal of the source driver to the low predetermined voltage level VPL. The high predetermined voltage level VPH is utilized as the first predetermined voltage level in the embodiment of FIG. 4, if the voltage level of the first image data IS1 is determined to be higher than the high predetermined voltage level VPH, the output terminal of the source driver is pre-charged to the high predetermined voltage level VPH. Also, the output terminal is charged to the reference voltage level Vref after being pre-charged to the high predetermined voltage level VPH, then charged to the low predetermined voltage level VPL and then charged to the target voltage level VT. The embodiment shown in FIG. 5 has inversed phase but the same logic as which of the embodiment shown in FIG. 4. That is, the low predetermined voltage level VPL is utilized as the first predetermined voltage level in FIG. 5, but FIG. 5 has an operation logic the same as which of FIG. 4. The figures for FIG. 4 and FIG. 5 are symmetric, but the positive/negative for the first image data IS1 and the target voltage level VT in FIG. 5 are opposite as which in FIG. 4.
In the embodiment shown in FIG. 6, the voltage level for the first image data IS1 is positive, and the absolute value thereof is larger than which of the high predetermined voltage level VPH. Also, the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore, the voltage level that is possibly to be pre-charged to is the same as the embodiment of FIG. 4. The embodiment in FIG. 6 also utilizes the high predetermined voltage level VPH as the first predetermined voltage level. However, after pre-charges to the high predetermined voltage level VPH, the embodiment in FIG. 6 charges to the reference voltage level Vref rather than the low predetermined voltage level VPL and then charges to the target voltage level VT. The phase of the embodiment in FIG. 7 is opposite to which of FIG. 6. However, the embodiment in FIG. 7 has logic the same as which of FIG. 6. Therefore, the description for FIG. 11 is omitted for brevity here.
In the embodiment shown in FIG. 8, the voltage level for the first image data IS1 is positive, and the absolute value thereof is larger than which of the high predetermined voltage level VPH. Also, the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore, the voltage level that is possibly to be pre-charged to is the same as the embodiment of FIG. 4. The embodiment in FIG. 8 also utilizes the high predetermined voltage level VPH as the first predetermined voltage level. However, the embodiment of FIG. 8 pre-charges the output terminal to the reference voltage level Vref rather then the high predetermined voltage level VPH (i.e. pre-charges to a second predetermined voltage level different from the first predetermined voltage level) after determines that the absolute value of the voltage level for the first image data IS1 is larger than which of the high predetermined voltage level VPH. After that, the output terminal is charged to the low predetermined voltage level VPL, and then charged to the target voltage level VT. The phase of the embodiment in FIG. 9 is opposite to which of FIG. 8. However, the embodiment in FIG. 9 has logic the same as which of FIG. 8. Therefore, the description for FIG. 11 is omitted for brevity here.
In the embodiment shown in FIG. 10, the voltage level for the first image data IS1 is positive, and the absolute value thereof is larger than which of the high predetermined voltage level VPH. Also, the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore, the voltage level that is possibly to be pre-charged to is the same as the embodiment of FIG. 4. The embodiment in FIG. 10 also utilizes the high predetermined voltage level VPH as the first predetermined voltage level. However, after determine that the absolute value of the voltage level for the first image data IS1 is larger than which of the high predetermined voltage level VPH and pre-charges the output terminal to the high predetermined voltage level VPH, the embodiment in FIG. 10 only charges the output terminal to the low predetermined voltage level VPL and then directly charges the output terminal to the target voltage level VT. Therefore, the embodiment in FIG. 10 does not charge to the reference voltage level Vref. The phase of the embodiment in FIG. 11 is opposite to which of FIG. 10. However, the embodiment in FIG. 11 has logic the same as which of FIG. 10. Therefore, the description for FIG. 11 is omitted for brevity here.
In the embodiment shown in FIG. 12, the voltage level for the first image data IS1 is positive, and the absolute value thereof is larger than which of the high predetermined voltage level VPH. Also, the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore, the voltage level that is possibly to be pre-charged to is the same as the embodiment of FIG. 4.
The embodiment in FIG. 12 also utilizes the high predetermined voltage level VPH as the first predetermined voltage level. However, after determine that the absolute value of the voltage level for the first image data IS1 is larger than which of the high predetermined voltage level VPH and pre-charges the output terminal to the high predetermined voltage level VPH, the embodiment in FIG. 12 directly charges the output terminal to the target voltage level VT. Therefore, the embodiment in FIG. 12 does not charge the output terminal to other voltage levels. The phase of the embodiment in FIG. 13 is opposite to which of FIG. 12. However, the embodiment in FIG. 13 has logic the same as which of FIG. 12. Therefore, the description for FIG. 13 is omitted for brevity here.
In the embodiment shown in FIG. 14, the voltage level for the first image data IS1 is positive, and the absolute value thereof is larger than which of the high predetermined voltage level VPH. Also, the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore, the voltage level that is possibly to be pre-charged to is the same as the embodiment of FIG. 4. The embodiment in FIG. 14 also utilizes the high predetermined voltage level VPH as the first predetermined voltage level. However, the embodiment of FIG. 14 pre-charges the output terminal to the reference voltage level Vref rather then the high predetermined voltage level VPH (i.e. pre-charges to a second predetermined voltage level different from the first predetermined voltage level) after determines that the absolute value of the voltage level for the first image data IS1 is larger than which of the high predetermined voltage level VPH. After that, the output terminal is charged to the target voltage level VT. The phase of the embodiment in FIG. 15 is opposite to which of FIG. 14. However, the embodiment in FIG. 15 has logic the same as which of FIG. 14. Therefore, the description for FIG. 15 is omitted for brevity here.
In the embodiment shown in FIG. 16, the voltage level for the first image data IS1 is positive, and the absolute value thereof is larger than which of the high predetermined voltage level VPH. Also, the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore, the voltage level that is possibly to be pre-charged to is the same as the embodiment of FIG. 4. The embodiment in FIG. 16 also utilizes the high predetermined voltage level VPH as the first predetermined voltage level. However, the embodiment of FIG. 16 pre-charges the output terminal to the low predetermined voltage level VPL rather then the high predetermined voltage level VPH (i.e. pre-charges to a second predetermined voltage level different from the first predetermined voltage level) after determines that the absolute value of the voltage level for the first image data IS1 is larger than which of the high predetermined voltage level VPH. After that, the output terminal is charged to the target voltage level VT. The phase of the embodiment in FIG. 17 is opposite to which of FIG. 16. However, the embodiment in FIG. 17 has logic the same as which of FIG. 16. Therefore, the description for FIG. 17 is omitted for brevity here.
In the embodiment of FIG. 18, the voltage level for the first image data IS1 is positive and the absolute value thereof is larger than which of the high predetermined voltage level. However, the target voltage level VT in FIG. 18 is different from which of the above-mentioned embodiment. The target voltage level VT of FIG. 18 is positive and the absolute value thereof is between absolute values of the low predetermined voltage level VPL and the reference voltage level Vref. Therefore, the voltage level that can be pre-charged to can be the high predetermined voltage level VPH or the reference voltage level Vref, which are both between the voltage levels of the first image data IS1 and the target voltage level VT. The embodiment in FIG. 18 also utilizes the high predetermined voltage level VPH as the first predetermined voltage level. In this embodiment, the output terminal is sequentially pre-charged to the high predetermined voltage VPH, charged to the reference voltage level Vref, and then charged to the target voltage level VT, after determines that the absolute value of the voltage level for the first image data IS1 is larger than which of the high predetermined voltage level VPH. The phase of the embodiment in FIG. 19 is opposite to which of FIG. 18. However, the embodiment in FIG. 19 has logic the same as which of FIG. 18. Therefore, the description for FIG. 19 is omitted for brevity here.
In the embodiment of FIG. 20, the voltage level for the first image data IS1 is positive. The target voltage level VT in FIG. 20 is the same which in FIG. 18. That is, the target voltage level VT is positive and the absolute value thereof is between absolute values of the low predetermined voltage level VPL and the reference voltage level Vref. Therefore, the voltage level that can be pre-charged in FIG. 20 is the same as which of FIG. 18. The embodiment in FIG. 20 also utilizes the high predetermined voltage level VPH as the first predetermined voltage level, and the target voltage level VT is also between the low predetermined voltage level VPL and the reference voltage level Vref. In this embodiment, the output terminal is pre-charged to the high predetermined voltage VPH and then directly charged to the target voltage level VT, after determines that the absolute value of the voltage level for the first image data IS1 is larger than which of the high predetermined voltage level VPH. The phase of the embodiment in FIG. 21 is opposite to which of FIG. 20. However, the embodiment in FIG. 21 has logic the same as which of FIG. 20. Therefore, the description for FIG. 21 is omitted for brevity here.
In the embodiment of FIG. 22, the voltage level for the first image data IS1 is positive. The target voltage level VT in FIG. 22 is the same which in FIG. 18. That is, the target voltage level VT is positive and the absolute value thereof is between absolute values of the low predetermined voltage level VPL and the reference voltage level Vref. Therefore, the voltage level that can be pre-charged in FIG. 22 is the same as which of FIG. 18. The embodiment in FIG. 22 also utilizes the high predetermined voltage level VPH as the first predetermined voltage level. However, this embodiment pre-charges the output terminal to the reference voltage level Vref rather than the high predetermined voltage VPH, and then directly charges to the target voltage level VT, after determines that the absolute value of the voltage level for the first image data IS1 is larger than which of the high predetermined voltage level VPH. Also, the target voltage level VT is between the low predetermined voltage level VPL and the reference voltage level Vref. The phase of the embodiment in FIG. 23 is opposite to which of FIG. 22. However, the embodiment in FIG. 23 has logic the same as which of FIG. 22. Therefore, the description for FIG. 23 is omitted for brevity here.
In the embodiment of FIG. 24, the voltage level for the first image data IS1 is positive and the absolute value thereof is between absolute values of the high predetermined voltage level VPH and the reference voltage level Vref. Also, the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore, the voltage level that can be pre-charged to can be the low predetermined voltage level VPH or the reference voltage level Vref, which are both between the voltage levels of the first image data IS1 and the target voltage level VT. The embodiment in FIG. 24 utilizes the reference voltage level Vref as the first predetermined voltage level. In this embodiment, the output terminal is sequentially pre-charged to the reference voltage level Vref, pre-charged to the low predetermined voltage level and then charged to the target voltage level VT, after determines that the absolute value of the voltage level for the first image data IS1 is larger than the reference voltage level Vref. The target voltage level VT is larger than which of the low predetermined voltage level VPL. The phase of the embodiment in FIG. 25 is opposite to which of FIG. 24. However, the embodiment in FIG. 25 has logic the same as which of FIG. 24. Therefore, the description for FIG. 25 is omitted for brevity here.
In the embodiment of FIG. 26, the voltage level for the first image data IS1 is positive and the absolute value thereof is between absolute values of the high predetermined voltage level VPH and the reference voltage level Vref. Also, the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore, the voltage level that can be pre-charged to is the same as which of the embodiment shown in FIG. 24. The embodiment in FIG. 26 utilizes the reference voltage level Vref as the first predetermined voltage level. In this embodiment, the output terminal is pre-charged to the reference voltage level Vref and then charged to the target voltage level VT, after determines that the absolute value of the voltage level for the first image data IS1 is larger than the reference voltage level Vref. The phase of the embodiment in FIG. 27 is opposite to which of FIG. 26. However, the embodiment in FIG. 27 has logic the same as which of FIG. 26. Therefore, the description for FIG. 27 is omitted for brevity here.
In the embodiment of FIG. 28, the voltage level for the first image data IS1 is positive and the absolute value thereof is between absolute values of the high predetermined voltage level VPH and the reference voltage level Vref. Also, the target voltage level VT is negative and the absolute value thereof is larger than which of the low predetermined voltage level VPL. Therefore, the voltage level that can be pre-charged to is the same as which of the embodiment shown in FIG. 24. The embodiment in FIG. 26 utilizes the reference voltage level Vref as the first predetermined voltage level. In this embodiment, the output terminal is pre-charged to the low predetermined voltage level VPL rather than the reference voltage level Vref (i.e. a second predetermined voltage level different from the first predetermined voltage level) and then charged to the target voltage level VT, after determines that the absolute value of the voltage level for the first image data IS1 is larger than the reference voltage level Vref. The phase of the embodiment in FIG. 29 is opposite to which of FIG. 28. However, the embodiment in FIG. 29 has logic the same as which of FIG. 28. Therefore, the description for FIG. 27 is omitted for brevity here.
In the embodiment of FIG. 30, the voltage level for the first image data IS1 is positive and the absolute value thereof is between absolute values of the high predetermined voltage level VPH and the reference voltage level Vref. Also, the target voltage level VT is negative and the absolute value thereof is between absolute values of the low predetermined voltage level VPL and the reference voltage level Vref. Therefore, the voltage level that can be pre-charged to is the reference voltage level Vref, which is between the voltage levels of the first image data IS1 and the target voltage level VT. The embodiment in FIG. 30 utilizes the reference voltage level Vref as the first predetermined voltage level. In this embodiment, the output terminal is sequentially pre-charged to the reference voltage level Vref and then charged to the target voltage level VT, after determines that the absolute value of the voltage level for the first image data IS1 is larger than the reference voltage level Vref. The phase of the embodiment in FIG. 31 is opposite to which of FIG. 30. However, the embodiment in FIG. 31 has logic the same as which of FIG. 30. Therefore, the description for FIG. 31 is omitted for brevity here.
FIG. 32-FIG. 37 are schematic diagrams illustrating the operation for the single channel source driver according to one embodiment of the present invention when the single channel source driver does not perform polarity inversing. In the following embodiment, the high predetermined voltage level VPH is positive and the low predetermined voltage level VPL is negative. Also the reference voltage level Vref is between VPH and VPL, which can be 0 or other values. If the LCD does not perform polarity inversing, data for two adjacent pixels is all negative or positive. In such case, the detection controlling circuit charges the output terminal of the first image data providing apparatus 301 to the high predetermined voltage level VPH, low predetermined voltage level VPL or the reference voltage level Vref, according to a relation between absolute values for the voltage level of the image data for two adjacent pixel line, and absolute values of the high predetermined voltage level VPH/low predetermined voltage level VPL. In the embodiments shown in FIGS. 32-37, the output terminal is determined to charged or pre-charged to a voltage level according to the voltage levels of the image data for a previous pixel line and a current pixel line.
As shown in FIG. 32, if an absolute value for a voltage level of image data of a previous pixel line (LN-1) is larger than which of the high predetermined voltage level VPH (the first predetermined voltage level), and an absolute value for a voltage level of the image data of a current pixel line (LN) is smaller than which of the high predetermined voltage level VPH, the detection controlling circuit 307 pre-charges the output terminal of the first image data providing apparatus 301 to the high predetermined voltage level VPH and then charges to the target voltage level VT (i.e. the image pixel line voltage level for the current pixel line). The phase of the embodiment in FIG. 33 is opposite to which of FIG. 32. However, the embodiment in FIG. 33 has logic the same as which of FIG. 32. Therefore, the description for FIG. 33 is omitted for brevity here.
In the embodiment shown in FIG. 34, an absolute value for a voltage level of image data of a previous pixel line is larger than which of the high predetermined voltage level VPH, and an absolute value for a voltage level of the image data of a current pixel line is smaller than which of the high predetermined voltage level VPH. There is some difference between the embodiments of FIG. 32 and FIG. 34, however. In the embodiment of FIG. 34, the absolute value for the voltage level of the image data of the current pixel line is closer to the reference voltage level Vref rather than the high predetermined voltage level VPH. Therefore, the detection controlling circuit 307 pre-charges the output terminal of the first image data providing apparatus 301 to the reference voltage level Vref rather than the high predetermined voltage level VPH and then charges to the target voltage level VT (i.e. the image pixel line voltage level for the current pixel line). The phase of the embodiment in FIG. 35 is opposite to which of FIG. 34. However, the embodiment in FIG. 35 has logic the same as which of FIG. 34.
In the embodiment shown in FIG. 36, if an absolute value for a voltage level of image data of a previous pixel line (LN-1) is smaller than which of the high predetermined voltage level VPH (the first predetermined voltage level), and an absolute value for a voltage level of the image data of a current pixel line (LN) is larger than which of the high predetermined voltage level VPH, the detection controlling circuit 307 pre-charges the output terminal of the first image data providing apparatus 301 to the high predetermined voltage level VPH and then charges to the target voltage level VT (i.e. the image pixel line voltage level for the current pixel line). The phase of the embodiment in FIG. 37 is opposite to which of FIG. 36. However, the embodiment in FIG. 37 has logic the same as which of FIG. 36.
Please note that the embodiment shown in FIG. 4 to FIG. 37 further comprise a data reading signal LD, which indicates that the first image data providing apparatus 301 will output data. In one embodiment, the pre-charging operation is performed when the data reading signal LD has a high logic value, and the image data providing apparatus 301 outputs the image data when the data reading signal LD has a low logic value. It does not mean to limit, however. The pre-charge operation can be performed at other timings. For example, the falling edge of the data reading signal LD.
Please refer to FIG. 3 again. In FIG. 3, the detection controlling circuit 307 only controls the image data transmitting for one channel. However, the detection controlling circuit 307 can control image data transmitting for two or more channels. As shown in FIG. 38, besides the first image data providing apparatus 301, the predetermined voltage level providing apparatuses 303, 305, the detection controlling circuit 307 can further control another channel, which comprises the second image data providing apparatus 1201, the predetermined voltage level providing apparatuses 1203, 1205. The two channels respectively transmit the first image data IS1 and the second image data IS2. The pre-charge mechanism of multi-channels is the same as which of the single channel. Accordingly, the detection controlling circuit 307 can control the second image data providing apparatus 1201, the predetermined voltage level providing apparatuses 1203, 1205 to perform the pre-charging operation shown in FIG. 4-FIG. 37. In such embodiment, the detection controlling circuit 307 generate control signals to control the switch device SW1, and switches devices in the predetermined voltage level providing apparatuses 303, 305, 1203, 1205.
The operation for the two channel source driver will be described as below. Please note that the following embodiments only correspond to some of the above-mentioned embodiments, since there are plenty of embodiments for the single channel source driver. However, it does not mean the two channel source driver according to the present invention is limited to following embodiments. The two channel source driver according to the present invention can be any combination for above-mentioned embodiments. FIG. 39 is a schematic diagram illustrating the operation for the two channel source driver according to one embodiment of the present invention when the two channel source driver performs polarity inversing, which is a combination for the embodiments shown in FIG. 8, FIG. 9. As shown in FIG. 39, the first image data IS1 transits from positive to negative, and an absolute value of the voltage level for the first image data IS1 is larger than which of the high predetermined voltage level VPH, thus the output terminal of the source driver is pre-charged to the high predetermined voltage level VPH. The second image data IS2 transits from negative to positive, and an absolute value of the voltage level for the second image data IS2 is larger than which of the low predetermined voltage level VPL, thus the output terminal of the source driver is pre-charged to the low predetermined voltage level VPL.
In above-mentioned embodiments, the pre-charge operation is performed when the data reading signal LD has a high logic value. In the embodiment shown in FIG. 9, the output terminals of the first image data providing apparatus 301 and the second image data providing apparatus 1201 are further shorted (i.e. the switch SW1 is conductive), such that the charges can be shared and the voltage level of the output terminals is close to a voltage level between the high predetermined voltage level VPH and the low predetermined voltage level VPL (ex. the reference voltage level but not limited). After that, the pre-charge operation is performed in the following time period P1, which pre-charges the output terminals to the high predetermined voltage level VPH or the low predetermined voltage level VPL. However, the pre-charge operation can be performed without performing the charge sharing operation. The charge sharing operation can be triggered by various conditions. One of the conditions is if it is detected that two adjacent pixels lines must perform a polarity inversing operation, the charge sharing operation is performed after the data of the first pixel is outputted. The signal level transits from positive to negative or negative to positive, if the polarity is inversed. Therefore, if a charge-sharing operation is performed, the voltage level at the output terminal of the image data providing apparatus is varied to a voltage close to the reference voltage Vref, such that the output terminal is not needed to be charged from a voltage level of a polarity to a voltage level of another polarity. Also, after the pre-charge operation is performed, output terminals of the first image data providing apparatus 301 and the second image data providing apparatus 1201 are respectively charged to the target voltages VT1 and VT2. In another embodiment, the first image data IS1 transits from negative to positive and the second image data IS2 transits from positive to negative, therefore the curves thereof will be swapped. The detail for such example can be acquired according to the embodiment of FIG. 39, thus it is omitted for brevity here.
The embodiment shown in FIG. 40 comprises the charge sharing operation shown in FIG. 39, but the target voltage levels VT1, VT2 are different for these two embodiments. Also, the polarities of the embodiments shown in FIG. 40 are not inversed. Take the first image data IS1 for example, the absolute value of the target voltage level VT is smaller than the low predetermined voltage level VPL in FIG. 39, but the target voltage level VT is between the reference voltage level Vref and the low predetermined voltage level VPL in FIG. 40. Therefore, in the embodiment of FIG. 39, the output terminal is pre-charged to the high predetermined voltage level VPH or the low predetermined voltage level VPL in the time period P1 after short the output terminals of the first image data providing apparatus 301 and the second image data providing apparatus 1201. However, in the embodiment of FIG. 40, the output terminal is directly charged to the target voltage level VT without performing pre-charging operations, after short the output terminals of the first image data providing apparatus 301 and the second image data providing apparatus 1201. Via charge sharing, voltage levels for output terminals of image data providing apparatuses can be varied to an average voltage level, such that the range for following charging or pre-charging operations can be decreased to decrease thermal energy or power consumption.
FIG. 41 is a schematic diagram illustrating the operation for the two channel source driver according to one embodiment of the present invention when the two channel source driver does not perform polarity inversing. In the embodiment of FIG. 41, the first image data IS1 is the same as which in FIG. 36, and the second image data IS2 is the same as which in FIG. 37, therefore the pre-charging methods in FIG. 36 and FIG. 37 can be applied to FIG. 41. FIG. 42 is also a schematic diagram illustrating the operation for the two channel source driver according to one embodiment of the present invention when the two channel source driver does not perform polarity inversing. In the embodiment of FIG. 42, the first image data IS1 is the same as which in FIG. 32, and the second image data IS2 is the same as which in FIG. 33, therefore the pre-charging methods in FIG. 32 and FIG. 33 can be applied to FIG. 41. In the embodiments of FIG. 41 and FIG. 42, situations for the first image data IS1 and the second image data IS2 can be swapped, in such case the curves will be swapped as well. The detail for such example can be acquired according to the embodiments of FIG. 41 and FIG. 42, thus it is omitted for brevity here.
FIG. 43-FIG. 45 are source drivers according different embodiments of the present invention, which have detection controlling circuits at different locations. Please note the structures in FIG. 43 and FIG. 45 are only for example and do not mean to limit the scope of the present invention. As shown in FIG. 43, the source driver 1600 comprises a timing controller 1601, a transmitting interface 1603, first registers 1605,1608, second registers 1607, 1609, level transiting devices 1611, 1613, analog to digital converters 1615, 1617, and the above-mentioned first image data providing apparatus 301 and second image data providing apparatus 1201. Please note some advice for above-mentioned embodiments are not illustrated in FIG. 43 to FIG. 45. The timing controller 1601 is for controlling timings for other devices, and the transmitting interface 1603 is for transmitting image data (also can transmit other signals). The first registers 1605, 1608 register the image data and transmit to the second registers 1607, 1609 until image data for a complete pixel line is formed. The second registers 1607, 1609 output the image data, which will be processed by level transiting devices 1611, 1613, analog to digital converters 1615, 1617, to the first image data providing apparatus 301 and second image data providing apparatus 1201.
Therefore, the input terminal of the detection controlling circuit 307 can be coupled to output terminals of the first registers 1605, 1608 and the second registers 1607, 1609 to acquire image data for different pixel lines, as shown in FIG. 43. Alternatively, the detection controlling circuit 307 can be directly coupled to the transmitting interface 1603 having a plurality of following devices, as shown in FIG. 44. By this way, it can be avoided to locate the detection controlling circuit 307 at the same region of the following devices, such that the space of the chip can be optimally used. Or, the detection controlling circuit 307 can be incorporated into the timing controller 1601, as shown in FIG. 45. In the embodiment show in FIG. 45, firmware can be written into the timing controller 1601 to perform the function of the detection controlling circuit 307.
In view of above-mentioned embodiments, a display driving method can be acquired, as show in FIG. 46. The method comprises following steps:
Step 1901
Provide a first predetermined voltage level. For example, one of the high predetermined voltage level VPH, the low predetermined voltage level VPL and reference voltage level Vref.
Step 1903
Utilize a first image data providing apparatus (ex. 301 in FIG. 3) to output a first image data IS1.
Step 1905
Determine if an output terminal of the first image data providing apparatus is pre-charged to the first predetermined voltage level according to a relation between an absolute value of a voltage level of the first image data and an absolute value of the first predetermined voltage level. For example, VPH is utilized as the first predetermined voltage level, and the output terminal is pre-charged to VPH.
Such method can further comprise: providing another predetermined voltage, that is, the second predetermined voltage level. In such case, the step 1905 can be varied to comprise the step: Determine if an output terminal of the first image data providing apparatus is pre-charged to another predetermined voltage level according to a relation between an absolute value of a voltage level of the first image data and an absolute value of the first predetermined voltage level. For example, VPH is utilized as the first predetermined voltage level, but the output terminal is pre-charged to VPL. Other detail steps can be acquired via above-mentioned embodiments, thus are omitted for brevity here.
In view of above-mentioned embodiments, the output terminal of the image data providing apparatus can be pre-charged to a predetermined level before the image data providing apparatus outputs the data according to the characteristic of the image data. By this way, the current generated via the charging operation can only flow through a switch rather than flow through a plurality of resistors such as the prior art, thus the generation for thermal energy can be decreased. Also, the charge sharing operation can be performed via the detection controlling circuit, even the polarity inversing is not performed. By this way, the pre-charge operation or charge operation can be more fast.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Application
20140320474
