BACKGROUND
Technical Field
The invention generally relates to a display driver. More particularly, the invention relates to the display driver and its operating method adapted to MIPI HS-RX.
Description of Related Art
Mobile Industry Processor Interface (MIPI) has been widely spread in consumer electronics recently. For image processing applications, MIPI DSI (Display Serial Interface) defines a high-speed serial interface between a processor and a display module, and D-PHY of MIPI DSI is a high-speed source synchronous physical layer for mobile applications. D-PHY includes at least a low-power transmitter (LP-TX), a low-power receiver (LP-RX), a high-speed transmitter (HS-TX), and a high-speed receiver (HS-RX).
Traditionally, in a driver IC with high frame rate such as 120 hz, in order to design MIPI HS-RX to support the highest MIPI transmission speed, HSRX would be set to drive with high-speed reception capability which stands for high drive capability, high anti-interference and high bias current. However, if the driver IC with high frame rate is applied under scenarios with low frame rate or low bit rate, it leads to an excess power consumption since HSRX is fixed to high drive capability and high bias current.
SUMMARY
The invention is directed to a display driver and an operating method of the display driver, in which the bias current of HS-RX would be adjusted according to the bit rate.
An embodiment of the invention provides a display driver. The display driver includes a receiver comprising a bias current control circuit. The receiver receives image data. The bias current control circuit computes a data bit rate of the image data, and adjusting a bias current of the receiver according to the data bit rate.
An embodiment of the invention provides an operating method, which is adapted to a display driver having a receiver comprising a bias current control circuit. The operating method includes: receiving, by a receiver, image data; computing, by a bias current control circuit, a bit rate of the image data; and adjusting, by a bias current control circuit, a bias current of the receiver according to the bit rate.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic block diagram illustrating a display driver according to an embodiment of the invention.
FIG. 2 is a flowchart illustrating an operating method of a display driver according to an embodiment of the invention.
FIG. 3A is a timing diagram illustrating counting transmission time of pixel data under a non-burst mode according to an embodiment of the invention.
FIG. 3B is a timing diagram illustrating counting transmission time of pixel data under a burst mode according to an embodiment of the invention.
FIG. 4 is a flowchart illustrating computing a bit rate according to an embodiment of the invention.
FIG. 5 is a flowchart illustrating an operating method of a display driver with one-time adjustment according to an embodiment of the invention.
FIG. 6 is a timing diagram illustrating an operating method of a display driver with one-time adjustment according to an embodiment of the invention.
FIG. 7 is a flowchart illustrating an operating method of a display driver with dynamic adjustment under a fixed frame rate according to another embodiment of the invention.
FIG. 8 is a timing diagram illustrating an operating method of a display driver with dynamic adjustment under a fixed frame rate according to another embodiment of the invention.
FIG. 9 is a timing diagram illustrating an operating method of a display driver with dynamic adjustment under a non-fixed frame rate according to another embodiment of the invention.
DESCRIPTION OF THE EMBODIMENTS
Embodiments are provided below to describe the disclosure in detail, though the disclosure is not limited to the provided embodiments, and the provided embodiments can be suitably combined. The term “coupling/coupled” or “connecting/connected” used in this specification (including claims) of the application may refer to any direct or indirect connection means. For example, “a first device is coupled to a second device” should be interpreted as “the first device is directly connected to the second device” or “the first device is indirectly connected to the second device through other devices or connection means.” The term “signal” can refer to a current, a voltage, a charge, a temperature, data, electromagnetic wave or any one or multiple signals. In addition, the term “and/or” can refer to “at least one of”. For example, “a first signal and/or a second signal” should be interpreted as “at least one of the first signal and the second signal”.
FIG. 1 is a schematic block diagram illustrating a display driver 10 according to an embodiment of the invention. FIG. 2 is a flowchart illustrating an operating method of the display driver 10 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, the display driver 10 at least includes a receiver 110 comprising a bias current control circuit 120. In step S210, the receiver 110 receives image data. Next, in step S220, the bias current control circuit 120 receive the image data from the receiver 110 and computes a bit rate of the image data. In step S230, the bias current control circuit 120 adjusts a bias current of the receiver 110 according to the bit rate.
In the present embodiment, the receiver 110 may include a mobile industry processor interface (MIPI). On the other hand, the receiver 110 may include a MIPI high-speed receiver (HS-RX) (not drawn) and receive the image data from a MIPI high-speed transmitter (HS-TX) (not drawn). The receiver 110 at least includes a differential amplifier 130 having a bias current source 140, and a bias current control circuit 120. The bias current control circuit 120 computes the bit rate of the image data received by the receiver 110. The bit rate indicates the amount of bits of the image data transmitted per unit time. After computing the bit rate, the bias current control circuit 120 adjusts a bias current of the bias current source 140 of the differential amplifier 130 in the receiver 110 according to the bit rate. The detail of computing the bit rate will be described thereafter. The differential amplifier 130 outputs analog driving signals to drive pixels of a display panel 150 to display images.
FIG. 3A is a timing diagram illustrating counting transmission time of pixel data under a non-burst mode according to an embodiment of the invention. FIG. 3B is a timing diagram illustrating counting transmission time of pixel data under a burst mode according to an embodiment of the invention. Referring to FIG. 3A and FIG. 3B, the bias current control circuit 120 counts transmission time DE of pixel data RGB in one of a plurality of display lines of the image data based on the clock signal, and computes the bit rate according to the transmission time DE. For example, under a non-burst mode shown in FIG. 3A, in the transmission time TL of a display line the bias current control circuit 120 receives a horizontal-sync packet HS, a horizontal back porch HBP, pixel data RGB and a horizontal front HFP. The bias current control circuit 120 counts the transmission time DE of pixel data RGB as 100 T (including 100 cycles of the clock signal). Assuming a period of the clock signal is 0.04 μs, the transmission time DE of pixel data RGB under the non-burst mode would be 4 μs. On the other hand, under a burst mode in FIG. 3B, the transmission time TL of a display line includes a horizontal-sync packet HS, a horizontal back porch HBP, pixel data RGB, a blank packet BLLP and a horizontal front HFP. The bias current control circuit 120 counts the transmission time DE of pixel data RGB as 70 T (including 70 cycles of the clock signal). Assuming a period of each cycle is 0.04 μs, the transmission time DE of pixel data RGB under the burst mode would be 2.8 μs.
FIG. 4 is a flowchart illustrating computing a bit rate according to an embodiment of the invention. In step S410, the receiver 110 receives image data. Next, in step S420, the bias current control circuit 120 counts the transmission time DE of pixel data RGB of one of a plurality of data lines of the image data. In step S430, the bias current control circuit 120 computes the MIPI bit rate (per lane) transmitted through single lane, shown as equation (1):
MIPI bit rate per lane=(H_resolution*RGB bits)/(MIPI lane number*DE) (1)
The H_resolution is a number of the pixels, the RGB bit is RGB bit number of each pixel, the MIPI lane number is the number of MIPI lane, and the DE is the transmission time DE of the pixel data RGB. For example, Giving transmission time DE as 4 μs, H_resolution as 720 pixels, number of RGB bits per pixel as 8(R)+8(G)+8(B)=24 bits, and Lane number as 4, the MIPI bit rate (per lane) would be computed as 1080 Mbps based on equation (1).
The bias current control circuit 120 inputs the computed bit rate into a lookup table Table 1 to generate a control signal S1 corresponding to the bit rate, and adjust the bias current of the bias current source 140 of the differential amplifier 130 in the receiver 110 according to the control signal S1. For example, if the bit rate is computed as 1150 Mbps, the bias current control circuit 120 would adjust the bias current to a Large HS-RX bias current setting.
TABLE 1
|
|
MIPI bit rate (per lane)
HS-RX bias current setting
|
|
|
1200~1300
Mbps
Very Large
|
1100~1200
Mbps
Large
|
1000~1100
Mbps
Medium High
|
900~1000
Mbps
Medium
|
800~900
Mbps
Medium Low
|
|
FIG. 5 is a flowchart illustrating an operating method of a display driver with one-time adjustment according to an embodiment of the invention. FIG. 6 is a timing diagram illustrating an operating method of a display driver with one-time adjustment according to an embodiment of the invention. Referring to FIG. 5 and FIG. 6, after sleeping out in step S510, the bias current control circuit 120 firstly sets a first bias current I1 for the first display line of the first frame, and receives the image data with the first bias current I1 in step S520, where the first bias current I1 would be the maximum HS-RX bias current setting as Very Large bias current setting defined in Table 1, in order to avoid receiving the first data incorrectly due to a faster bit rate with insufficient bias current in the beginning. Next, in step S530, the bias current control circuit 120 counts the transmission time DE of pixel data RGB of one of a plurality of data lines of the image data, such as 106 T. In step S540, the bias current control circuit 120 computes the MIPI bit rate (per lane) transmitted through single lane according to the counted transmission time DE, such as 1018 Mbps. Next, in step S550, the bias current control circuit 120 adjusts the bias current to a second bias current I2 corresponding to the computed MIPI bit rate in the beginning of the second display line, such as the Medium High HS-RX bias current setting shown in table 1. In this embodiment, the bias current control circuit 120 just adjusts the bias current once, thus the bias current would be fixed to the second bias current I2 after the first display line of the first frame. It is noted that the second bias current I2 must be less or equal to the first bias current I1.
FIG. 7 is a flowchart illustrating an operating method of a display driver with dynamic adjustment under a fixed frame rate according to another embodiment of the invention. FIG. 8 is a timing diagram illustrating an operating method of a display driver with dynamic adjustment under a fixed frame rate according to another embodiment of the invention. Referring to FIG. 7 and FIG. 8, after sleeping out in step S710, the bias current control circuit 120 firstly sets the first bias current I1 for the first display line of the frame N, and receives the image data with the first bias current I1 in step S720, where the first bias current I1 would be the maximum HS-RX bias current setting as Very Large bias current setting defined in Table 1. Next, in step S730, the bias current control circuit 120 counts the transmission time DE of pixel data RGB of one of a plurality of data lines of the image data, such as 90 T. In step S740, the bias current control circuit 120 computes the MIPI bit rate (per lane) transmitted through single lane according to the counted transmission time DE, such as 1200 Mbps. Next, in step S750, the bias current control circuit 120 adjusts the bias current to a third bias current I3A corresponding to the computed MIPI bit rate in the beginning of the second display line, such as Very Large HS-RX bias current setting shown in table 1. In step S760, the bias current control circuit 120 switches from the frame N to the frame N+1 after receiving a MIPI Vsync (not drawn). In the frame N+1, the bias current control circuit 120 sets the first bias current I1 for the first display line of the frame N+1, and receives the image data with the first bias current I1. Then, the bias current control circuit 120 counts the transmission time DE of pixel data RGB of one of a plurality of data lines of the image data, such as 92 T. The bias current control circuit 120 computes the MIPI bit rate (per lane) transmitted through single lane according to the counted transmission time DE, such as 1174 Mbps. The bias current control circuit 120 adjusts the bias current to the third bias current I3B corresponding to the computed MIPI bit rate in the beginning of the second display line, such as Large HS-RX bias current setting shown in table 1. It is noted that third bias current I3A and I3B must be less or equal to the first bias current I1.
FIG. 9 is a timing diagram illustrating an operating method of a display driver with dynamic adjustment under a non-fixed frame rate according to another embodiment of the invention. This embodiment works under some applications with non-fixed frame rates, such as a dynamic switching high/low frame rate application, and the high/low frame rates would be switched by adjusting the transmission time TL of the display lines. In this embodiment, the adjustment flow of the bias current is similar with FIG. 8, in which the bias current control circuit 120 adjusts the bias current to fourth bias current I4A during the second display line of the frame N and to fourth bias current I4B during the second display line of the frame N+1. The difference between FIG. 9 and FIG. 8 shows that the transmission time TL of the display lines and the MIPI bit rate would be changed according to the frame rate, thereby the HSRX driving capability of the driving IC would be adjusted. For example, in FIG. 9, the transmission time TL of Frame N (120 Hz) is 4.5 μs, and the transmission time TL of Frame N+1 (90 Hz) is 6.4 μs which leads to a longer transmission time DE of pixel data RGB. In the frame N, the transmission time DE is counted as 90 T, the MIPI bit rate (per lane) is computed as 1200 Mbps, and the bias current control circuit 120 adjusts the bias current to a fourth bias current I4A corresponding to the computed MIPI bit rate in the beginning of the second display line of the frame N, such as Large HS-RX bias current setting shown in table 1. In the frame N+1, the transmission time DE is counted as 120 T, the MIPI bit rate (per lane) is computed as 900 Mbps, and the bias current control circuit 120 adjusts the bias current to a fourth bias current I4B corresponding to the computed MIPI bit rate in the beginning of the second display line of the frame N+1, such as Medium HS-RX bias current setting shown in table 1. It is noted that fourth bias current I4A and I4B must be less or equal to the first bias current I1. Therefore, MIPI bit rate would be reduced for setting a less bias current under scenarios with low frame rate, so as to achieve the power saving.
Based on above, in the embodiments of the invention, the bias current of HS-RX would be adjusted once or in every frame according to a computed bit rate. Therefore, the excess power consumption could be saved since the bias current would dynamically adjusted for low bit rate.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
Patent Grant
11631363
