Patent Application
20160365042
This relates generally to electronic devices, and, more particularly, to electronic devices with displays.
Electronic devices such as cellular telephones, computers, and other electronic equipment often contain displays. A display includes an array of pixels for displaying images to a user. Display driver circuitry such as data line driver circuitry may supply data signals to the array of pixels. Gate line driver circuitry in the display driver circuitry can be used to assert a gate line signal on each row of pixels in the display in sequence to load data into the pixels.
It can be challenging to uniformly load data into the pixels of a display. The times at which the leading and trailing edges of a data line signal occur are different across the display. Due to propagation delays along the data lines, pixels at locations close to the data line driver circuitry may receive data line signals with minimal delay, whereas pixels at locations far from the data line driver circuitry may receive data line signals with larger amounts of delay. Gate line signals can also be affected by propagation delays. Pixels at locations close to the gate line driver circuitry may receive undelayed signals whereas pixels at locations far from the gate line driver circuitry may receive gate line signals with delays.
During data loading operations for each row of pixels, the gate line signal for that row of pixels is asserted, turning on associated thin-film transistors in the pixels and loading data from corresponding data lines into the pixels. Because gate line signals can experience location-dependent gate line delays and because data line signals can experience location-dependent data line delays, the desired timing relationships between date line signals and gate line signals may be disrupted. If care is not taken, there may not be sufficient data loading time (charging time) for certain pixels or a data line signal may become invalid for a pixel before the gate line signal for that pixel has been deasserted. As a result, data loading operations may not be performed satisfactorily for a display.
It would therefore be desirable to be able to provide displays with improved gate line and data line driver circuitry.
A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry may supply gate line signals to rows of the pixels on gate lines. The gate driver circuitry may have registers that form a shift register to supply the gate line signals to the gate lines. Data line driver circuitry may supply data line signals to columns of the pixels on data lines. The pixels may be liquid crystal display pixels each of which has a thin-film transistor with a gate that receives one of the gate line signals to control the application of a data line signal to a respective portion of a liquid crystal layer.
The gate line signals may experience propagation delays when traveling away from the gate line driver circuitry on the gate lines. The data line data line signals may experience propagation delays when traveling away from the data line driver circuitry on the data lines.
To compensate for data line signal propagation delays, the registers of the shift register may be clocked with increasingly delayed clocks as a function of increasing distance way from the display driver circuitry. To compensate for gate line signal propagation delays, the data line driver circuitry may impose increasing delays on the data line signals carried on the data lines as a function of increasing distance of the data lines away from the gate driver circuitry.
An illustrative electronic device of the type that may be provided with a display is shown in
Input-output circuitry in device 10 such as input-output devices 12 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 12 may include buttons, joysticks, scrolling wheels, touch pads, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user can control the operation of device 10 by supplying commands through input-output devices 12 and may receive status information and other output from device 10 using the output resources of input-output devices 12.
Input-output devices 12 may include one or more displays such as display 14. Display 14 may be a touch screen display that includes a touch sensor for gathering touch input from a user or display 14 may be insensitive to touch. A touch sensor for display 14 may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor, or other suitable touch sensor arrangements.
Control circuitry 16 may be used to run software on device 10 such as operating system code and applications. During operation of device 10, the software running on control circuitry 16 may display images on display 14 using an array of pixels in display 14.
Device 10 may be a tablet computer, laptop computer, a desktop computer, a display, a cellular telephone, a media player, a wristwatch device or other wearable electronic equipment, or other suitable electronic device.
Display 14 may be an organic light-emitting diode display, a liquid crystal display, or a display based on other types of display technology. Configurations in which display 14 is a liquid crystal display may sometimes be described herein as an example.
Display 14 may have a rectangular shape (i.e., display 14 may have a rectangular footprint and a rectangular peripheral edge that runs around the rectangular footprint) or may have other suitable shapes. Display 14 may be planar or may have a curved profile.
A top view of a portion of display 14 is shown in
Display driver circuitry 20 may be used to control the operation of pixels 22. Display driver circuitry 20 may be formed from integrated circuits, thin-film transistor circuits, or other suitable circuitry. Thin-film transistor circuitry may be formed from polysilicon thin-film transistors, semiconducting-oxide thin-film transistors such as indium gallium zinc oxide transistors, or thin-film transistors formed from other semiconductors. Pixels 22 may have color filter elements of different colors (e.g., red, green, and blue) to provide display 14 with the ability to display color images.
Display driver circuitry 20 may include display driver circuits such as display driver circuit 20A and gate driver circuitry 20B. Display driver circuit 20A, which may contain data line driver circuitry for supplying signals to data lines D, may be formed from one or more integrated circuits and/or thin-film transistor circuitry. Gate driver circuitry 20B, which may be used to supply signals to gate lines G, may be formed from integrated circuits or may be thin-film “gate-on-array” circuitry.
Display driver circuit 20A of
To display the images on display pixels 22, data line driver circuitry (source line driver circuitry) in display driver circuitry 20A may supply image data to data lines D while issuing clock signals and other control signals to supporting display driver circuitry such as gate driver circuitry 20B over path 38. Circuitry 20A may supply clock signals and other control signals to gate driver circuitry 20B on one or both edges of display 14 (see, e.g., path 38′ and gate driver circuitry 20B′ on the right-hand side of display 14 in the example of
Gate driver circuitry 20B may supply each gate line G with a gate line signal for controlling the pixels 22 of a respective row (e.g., to turn on transistors in pixels 22 when loading data from the data lines into pixel storage capacitors in those pixels from data lines D). During operation, frames of image data may be displayed by asserting a gate signal on each gate line G in the display in sequence. Shift register circuitry (e.g., a chain of registers) in gate driver circuitry 20B may be used in controlling the gate line signals.
An illustrative pixel circuit for pixels 22 of display 14 is shown in
Satisfactory loading of a data line signal from data line D into pixel 22 under the control of the gate line signal on gate line G is dependent on maintaining appropriate timing relationships between the gate line signals (gate line pulses) and data line signals (data line pulses). If the gate line signals and data line signals for a given pixel are shifted by an undesired amount with respect to each other, there will be insufficient timing margin to ensure proper data loading. As an example, the gate line signal may be deasserted after a data line signal is no longer valid, leading to erroneous amounts of charge storage on capacitor Cst and incorrect values of pixel voltage Vp. As another example, if a gate line signal is deasserted too soon, a pixel may have an insufficient pixel charging time.
Ensuring that there are appropriate timing relationships between the gate lines signals and data line signals in a display may be particularly challenging in displays where there are significant signal propagation delays associated with conveying signals between different portions of the display. Consider, as an example, display 14 of
With this type of configuration, pixels 22 in different locations on display 14 may receive data line signals and gate line signals at different times. For example, because pixels at locations PA and PC along upper edge 14-1 of display 14 are closest to data line driver circuitry 20A, the pixels at locations PA and PC will receive data line signals from data line driver circuitry 20A before the pixels at locations PB and PD along lower edge 14-2 of display 14 (i.e., locations PB and PD will experience data line propagation delays relative to locations A and C). Similarly, pixels 22 in positions PA and PB along the left edge of display 14 (i.e., the edge along which gate driver circuitry 20B runs) are closers to gate line driver circuitry 20B than pixels 22 in positions PC and PD along the right edge of display 14, so the pixels in positions PC and PD will experience gate line delays relative to the pixels in positions PA and PB.
Due to the propagation time required to convey data signals from date line driver circuitry 20A along the data lines in display 14, there is a data line delay Td between the data line signal D for pixels at locations PA and PC (which have no data line delay) and the data line signal D for pixels at locations PB and PD (which are delayed by Td). Due to the propagation time required to convey gate line signals from gate line driver circuitry 20B along the gate lines in display 14, there is a gate line delay Tg between the gate line signals G for pixels at locations PA and PB (which have no gate line delay) and the gate line signals G for the pixels at locations PC and PD (which are delayed by Tg). This can lead to timing issues. For example, there is a risk that gate line signal G will be deasserted after the signal on data line D is no longer valid, as illustrated by the delayed location of gate line signal falling edge 50 relative to data line signal falling edge 52 for the pixels at position PC. There is also a risk that pixel charging times will be undesirably shortened, as illustrated by the excessively reduced pixel charging time Tc that has resulted from the delayed position of data line signal falling edge 56 relative to gate line signal falling edge 54 (effectively causing gate line signal edge 54 to fall too soon) for the pixels at position PB.
To compensate for the timing issues caused by these signal delays, the timing of the gate line signals in different rows may be adjusted as a function of gate line position in display 14 and/or the timing of the data line signals in different columns may be adjusted as a function of data line position in display 14. Gate line driver circuitry 20B can be configured to produce gate line signals (or sets of gate line signals) that are asserted at progressively delayed times as a function of increasing row position (i.e., increasing distance from display driver circuitry 20A) to compensate for data line delay. Data line driver circuitry 20A can be configured to produce data line signals (or sets of data line signals) that are asserted at progressively delayed times as a function of column position (i.e., as a function of increasing distance from gate line driver circuitry 20A) to compensate for gate line delay.
An illustrative configuration for gate line driver circuitry 20B that allows compensation for data line delay is shown in
Each register 60 has an output 64 that produces an output signal. Gate line buffers 66 may drive the output signal from each output 64 onto a corresponding gate line, thereby creating a gate line pulse (gate line signal) for an associated row of pixels 22 in display 14. The output signal on each output 64 may be passed by a trigger signal path 68 that is coupled to that output 64 to the trigger input of a successive register 60, thereby forming the shift register.
Clocks on clock inputs 70 of registers 60 are used to clock the shift register and thereby establish the rising and falling edges of the gate line signals. The clocks may be multiphase clocks (as an example). To advance the rising edges of the gate line signals on some gate lines relative to others, different sets of clock inputs 70 may be clocked by clocks with different relative timings (i.e., increasing amounts of delay as a function of increasing distance from the edge of display 14 on which data line driver circuitry 20A is located).
As an example, in a display with 1000 lines, there may be four clock signal lines each of which distributes a differently delayed clock to a different respective set of registers 60 (e.g., a first clock signal to registers 1-250, a second, somewhat delayed, clock signal to registers 251-500, a third clock signal with additional delay to registers 501-750, and a fourth clock signal with yet further delay to registers 751-100). There may be any suitable number of registers in each set of registers (e.g., 5 or more, 10 or more, 50 or more, 100 or more, 250 or more, etc.). There is preferably a sufficiently small number of registers in each set of registers to ensure that the timing difference between successive sets of registers is relatively small and therefore results in a smooth transition between each set of registers. The present example in which there are 250 registers in each set of registers is merely illustrative.
In the illustrative configuration of
If desired, both gate line delay and data line delay may be compensated. This type of scenario is illustrated in
The foregoing is merely illustrative and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented individually or in any combination.
