Patent Grant
10360870
The present invention relates to a display driver, an electro-optical device, and an electronic apparatus.
A display driver of the related art includes a D/A conversion circuit that converts display data of each pixel into a voltage, and an amplification circuit that drives each pixel using a data voltage on the basis of the voltage. Since the amplification circuit performs a feedback control, the data voltage can be controlled to a target voltage although capacitances (for example, parasitic capacitances between data lines) of each data line are different from each other.
Recently, drive time per pixel is shortened due to advancement of a high definition electro-optical panel. For example, several to dozen pixels are driven at a time during phase development drive (for example, JP-A-2001-324970) in which several to dozen source lines are sequentially driven, and thus, high definition is achieved and the drive time per pixel is significantly shortened. If the drive time is shortened as such, drive capability of the amplification circuit needs to increase (settling time is shortened), but if the drive capability of the amplification circuit increases, accuracy of an output voltage decreases relatively. In order to achieve both, it is necessary to increase current consumption of the amplification circuit, but heat generation (temperature increase) of the display driver increases, and thus, it is difficult to achieve a high definition.
In order to solve the above problem, a method of performing drive without using feedback control, and thereafter, being set to a data voltage with high accuracy by an amplification circuit (or a method of performing only drive without using feedback control) is considered. For example, there is a method (digital assistance drive) of rapidly changing a data voltage to a target voltage by connecting an output terminal to a power supply during a predetermined period by using a transistor with drive capability according to a gradation difference between previous display data and next display data.
However, since the methods do not perform feedback control, there is a problem in which an error occurs between a data voltage that actually reaches and a target voltage due to capacitances (for example, parasitic capacitances between data lines) of each data line, and the display quality decreases (For example, display unevenness occurs). If the error between the data voltage and the target voltage is to be corrected by an amplification circuit, the amplification circuit requires drive capability for settling the data voltage in a short time, and as a result, power consumption of the amplification circuit increases.
In addition, since there is a case where a display driver is commonly used for various electro-optical panels, in a case where the display driver is used for various electro-optical panels, it is necessary to suppress a decrease in display quality caused by capacitances between data lines.
An advantage of some aspects of the invention is to provide a display driver, an electro-optical device, and an electronic apparatus which can suppress a decrease in display quality caused by capacitances between data lines, depending on various electro-optical panel.
According to an aspect of the invention, there is provided a display driver including a plurality of output terminals that output a plurality of data signals which are output to an electro-optical panel, and a drive circuit that outputs the plurality of data signals to the plurality of output terminals, in which the drive circuit includes a plurality of drive units, in which each of the plurality of drive units includes an amplification circuit and a drive assistance circuit that assists drive which is performed by the amplification circuit, and in which the drive assistance circuit of an ith drive unit of the plurality of drive units changes drive assistance capability on the basis of gradation change information representing a gradation change of the drive unit other than the ith drive unit.
In the aspect of the invention, the drive circuit includes a plurality of drive units having drive assistance circuits for assisting drive performed by an amplification circuit, and the drive assistance capability of the drive assistance circuit of the given drive unit changes on the basis of gradation change information of other drive units. By doing so, the drive assistance circuit operates with the drive assistance capability for correcting an error caused by a gradation change in other drive units, and thereby, it is possible to suppress a decrease in display quality. In addition, although the error is caused by an electro-optical panel side connected to the display driver, a drive circuit on the display driver side can perform adjustment.
In addition, in the aspect of the invention, the drive assistance capability of the drive assistance circuit of the ith drive unit may decrease, in a case where a direction of the gradation change of a drive unit adjacent to the ith drive unit is the same as a direction of the gradation change of the ith drive unit.
By doing so, it is possible to appropriately correct an error due to a gradation change of an adjacent drive unit.
In addition, in the aspect of the invention, the drive assistance capability of the drive assistance circuit of the ith drive unit may increase, in a case where a direction of the gradation change of a drive unit adjacent to the ith drive unit is different from a direction of the gradation change of the ith drive unit.
By doing so, it is possible to appropriately correct an error due to a gradation change of an adjacent drive unit.
In addition, in the aspect of the invention, the drive assistance circuit of the ith drive unit may assist drive in accordance with a direction of the gradation change of a drive unit adjacent to the ith drive unit, in a case where the gradation change of the ith drive unit is zero.
By doing so, it is possible to appropriately correct an error due to a gradation change of an adjacent drive unit.
In addition, in the aspect of the invention, the drive assistance capability of the drive assistance circuit of the ith drive unit may change on the basis of a total sum of the gradation change information of the plurality of drive units.
By doing so, it is possible to appropriately correct an error due to overall gradation changes of a plurality of drive units.
In addition, in the aspect of the invention, the drive assistance capability of the drive assistance circuit of the ith drive unit may decrease, in a case where a direction of the gradation change that is represented by the total sum of the gradation change information is the same as a direction of the gradation change of the ith drive unit.
By doing so, it is possible to appropriately correct an error due to overall gradation changes of a plurality of drive units.
In addition, in the aspect of the invention, the drive assistance capability of the drive assistance circuit of the ith drive unit may increase, in a case where a direction of the gradation change that is represented by the total sum of the gradation change information is different from a direction of the gradation change of the ith drive unit.
By doing so, it is possible to appropriately correct an error due to overall gradation changes of a plurality of drive units.
In addition, in the aspect of the invention, the drive assistance circuit of the ith drive unit may assist drive in accordance with a direction of the gradation change that is represented by the total sum information of the gradation change information, in a case where the gradation change of the ith drive unit is zero.
By doing so, it is possible to appropriately correct an error due to overall gradation changes of a plurality of drive units.
In addition, in the aspect of the invention, the drive assistance circuit may assist such that an output of the drive circuit changes to a high potential side power supply voltage direction, in a case where a direction of the gradation change is in the high potential side power supply voltage direction, and the drive assistance circuit may assist such that an output of the drive circuit changes to a low potential side power supply voltage direction, in a case where a direction of the gradation change is in the low potential side power supply voltage direction.
By doing so, assistance of changing an output in a direction according to a gradation change direction is performed by a drive assistance circuit, and thus, it is possible to easily perform drive by using an amplification circuit.
In addition, in the aspect of the invention, the drive assistance circuit may include a first drive transistor group on the high potential side power supply voltage side and a second drive transistor group on the low potential side power supply voltage side, and the drive assistance circuit may change drive capability of the first drive transistor group on the basis of the gradation change information, in a case where a direction of the gradation change is the high potential side power supply voltage direction, and may change drive capability of the second drive transistor group on the basis of the gradation change information, in a case where a direction of the gradation change is in the low potential side power supply voltage direction.
By doing so, it is possible to perform assistance of changing an output in a direction according to a gradation change direction on the basis of two drive transistor groups.
In addition, in the aspect of the invention, the drive assistance circuit may perform a preliminary drive before being driven by the amplification circuit.
By doing so, it is possible to reduce an error between a voltage reaching a preliminary drive and a target voltage, and to reduce power consumption of an amplification circuit.
In addition, in the aspect of the invention, a control circuit that performs calculation processing on the basis of the gradation change information and sets the drive assistance capability of the drive assistance circuit may be further included.
By doing so, it is possible to perform calculation processing for drive assistance capability based on a gradation change direction by using a control circuit.
In addition, in the aspect of the invention, the electro-optical panel may include a sample and hold circuit that samples and holds a plurality of video signals which are the plurality of data signals, and the plurality of output terminals may be connectable to one terminal of the sample and hold circuit.
In a case where the sample and hold circuit is included, if there is an error between a voltage and a target voltage at a timing when the voltage is held in a source line, display unevenness occurs. At this point, according to the aspect of the invention, the error can be reduced by adjusting drive assistance capability, and thus, it is possible to reduce the display unevenness.
In addition, according to another aspect of the invention, an electro-optical device includes the display driver described at any one of the above descriptions, and the electro-optical panel.
In addition, according to still another aspect of the invention, the electro-optical panel may include a sample and hold circuit that samples and holds a plurality of video signals which are the plurality of data signals and a plurality of input terminals that are connected to the plurality of output terminals of the display driver, the sample and hold circuit may include a plurality of transistors, each having a drain that is connected to a pixel and a source that is connected to any one input terminal of the plurality of input terminals, and the plurality of transistors may include a first transistor having a source and drain which are arranged in this sequence in a first direction of the electro-optical panel and a second transistor that are adjacent to the first transistor in the first direction and has a source and drain which are arranged in this sequence in the first direction.
In addition, according to still another aspect of the invention, the display driver described in any one of the above descriptions is included in an electronic apparatus.
The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
Hereinafter, preferred embodiments of the invention will be described in detail. The embodiments which will be described below do not unduly limit the content of the invention described in the claims, and all the configurations described in the embodiments are not indispensable as solution means for the invention.
1. Display Driver
The display driver 100 is, for example, an integrated circuit device, and the output terminal TQi is a pad (a pad formed on a silicon substrate) of the integrated circuit device or a terminal (a terminal to be mounted on a circuit substrate) of a package. Here, i is an integer larger than or equal to 1 and smaller than or equal to n−1. The adjacent output terminals TQi and TQi+1 are connected to adjacent data lines among a plurality of data lines (a plurality of video lines) of an electro-optical panel. Other output terminals are not provided between the output terminals TQi and TQi+1 on the silicon substrate or on the package. Terminals other than the output terminals may be provided between the output terminals TQi and TQi+1.
The drive circuit 10 includes a plurality of drive units UN1 to UNn, and each drive unit of the plurality of drive units UN1 to UNn includes an amplification circuit AM (AM 1 to AMn) and a drive assistance circuit AS (AS1 to ASn) which assists drive by using the amplification circuit AM. The drive unit UNi is connected to the output terminal TQi.
As will be described below, an operation of the drive unit UNi is divided into a preliminary drive period and an amplification drive period with reference to
In the drive circuit 10 which performs such a digital assistance drive, it is important that an error between the data voltage arriving at the preliminary drive and the target voltage is small. If the error is small, the drive capability of the amplification circuit AMi is not required, and thus, accuracy increases, and current consumption and heat generation can be suppressed.
It is assumed that a gradation of the display data which becomes an output target in a given drive unit UNi is changed from 64 to 128. In this case, the target voltage in the drive unit UNi changes from a voltage corresponding to a gradation 64 to a voltage corresponding to a gradation 128, and a voltage difference is a voltage corresponding to a gradation change of +64.
It is considered that, if the target voltage corresponding to the gradation 64 is output with high accuracy during the amplification drive period, the drive assistance circuit ASi in the next preliminary drive period may perform drive assistance by drive assistance capability for realizing a voltage change corresponding to a gradation change of +64 toward the gradation 128. That is, in short, it is considered that each drive unit of the plurality of drive units UN1 to UNn may determine the drive assistance capability based on its own gradation change information without considering a state of the other drive units.
However, it is found that proper control cannot be realized without considering the gradation changes of other drive units.
As can be seen from
A variation width of the voltage is large at 5→6 and 7→6, and it is not preferable to ignore influence of data voltage variation of adjacent drive units (here, the fifth and seventh drive units UN5 and UN7). That is, the data voltage of the sixth drive unit UN6 during the preliminary drive period is determined by an output of the drive assistance circuit AS6 of the UN6 itself and the fluctuation due to the voltage variation of an adjacent drive unit. Hence, in a case where the drive assistance capability is set such that the data voltage reaches the target voltage by an output of the drive assistance circuit AS6, an error corresponding to influence of the voltage variations of the adjacent drive units occurs between the data voltage and the target voltage. The error needs to be corrected in calculating the drive assistance capability of the drive assistance circuit AS6.
In addition, as can be seen from j→6 (j=1 to 4 and 8 to 12) in
The variation illustrated in
In this regard, in the present embodiment, the drive assistance capability of the drive assistance circuit ASi of the ith drive unit UNi among the plurality of drive units UN1 to UNn changes, based on gradation change information of the drive units other than the ith drive unit UNi.
Here, the gradation change information is information representing a change of a gradation (a gradation value). Specifically, the gradation change information may be a difference value between a gradation of the display data at a given timing and a gradation of the display data at a timing prior to the gradation, or may be other information corresponding to the difference value. In addition, the display driver 100 according to the present embodiment includes the plurality of drive units UN1 to UNn, and the gradation change information can be obtained for each drive unit. In a case where a liquid crystal display panel of a phase development type is used, a gradation change of the display data between simultaneous writing of n pixels at a given timing and simultaneous writing of the n pixels at a next timing may be referred to as the gradation change information. Specifically, the gradation change information for each of the n drive units is obtained by the gradation change in the pth drive and the (p+1)th drive of phase development. p is an integer of 1 or more, and an upper limit value of p is determined by the number of source lines of the electro-optical panel and n.
According to a method of the present embodiment, the drive assistance circuit ASi operates in accordance with the drive assistance capability in which influence caused by the parasitic capacitances (adjacent capacitances, common capacitances) between the data lines is considered. Thereby, a data voltage can be changed more accurately into the target voltage even in the drive without feedback control. Accordingly, in a case where the data voltage is settled to the target voltage by the amplification circuit AMi, it is possible to reduce an error to be corrected, and to output an accurate data voltage while reducing power consumption (drive capability) of the amplification circuit AMi.
In addition, the parasitic capacitances between the data lines depend on the product of the electro-optical panel (or individual differences even in the same product). In this regard, in the present embodiment, the drive circuit 10 on the display driver 100 side controls to suppress the influence caused by the capacitances between the data lines. By doing so, it is possible to suppress a decrease in display quality in correspondence with various electro-optical panels, and there is no need to provide an adjustment mechanism or the like on the electro-optical panel side.
As described with reference to
In this regard, in the present embodiment, a capacitance circuit CCi may be provided between the adjacent output terminals TQi and TQi+1, and a capacitance value of the capacitance circuit CCi may be controlled. Thereby, it is possible to adjust (correct) the total sum of the parasitic capacitance between the data lines and the capacitance value of the capacitance circuit CCi in the electro-optical panel such that the total sum is approximately the same in each data line. Since the capacitance between the data lines is approximately the same in each data line, variation of the data voltage due to coupling of the capacitances is approximately uniform in each data line, and the drive assistance capability is easily adjusted. In addition, it is also possible to automatically adjust the capacitance value of the capacitance circuit CCi as described with reference to
2. Electro-Optical Panel
The electro-optical panel 200 includes a sample and hold circuit that samples and holds a plurality of video signals, which are a plurality of data signals DS1 to DS8. The plurality of output terminals TQ1 to TQ8 of the display driver 100 are connectable to one terminal of the sample and hold circuit. In the following description, a case where n=8 will be described as an example, and n is not limited to 8.
Specifically, the sample and hold circuit includes transistors TR1, TR2, TR3, . . . respectively connected to the source lines DL1, DL2, DL3, . . . . If the transistors TR1, TR2, TR3, . . . are turned on, the video signals are sampled to the source lines DL1, DL2, DL3, . . . , and if the transistors are turned off, the video signals are held in the source lines DL1, DL2, DL3, . . . . Here, the video signals are drive signals which are used to drive the electro-optical panel by the display driver during the phase development drive.
In a case where the sample and hold circuit is provided, if there is an error between the voltage and a target voltage (a voltage corresponding to the display data) at a timing of holding the voltage on the source line, the error causes display unevenness. One cause of the error is the parasitic capacitance between the data lines (video lines). In this regard, in the present embodiment, the drive assistance capability is adjusted or the capacitances between the data lines are adjusted by the capacitance circuits CC1 to CC8 are performed, and thus, it is possible to reduce the display unevenness.
In addition, in the present embodiment, the electro-optical panel 200 includes a plurality of input terminals TI1 to TI8 connected to a plurality of output terminals TQ1 to TQ8 of the display driver 100. Each transistor of the plurality of transistors TR1, TR2, TR3, . . . has a drain connected to a pixel and a source connected to one input terminal of the plurality of input terminals TI1 to TI8. The first transistor TR1 has the source and the drain arranged in this sequence in a first direction D1 of the electro-optical panel 200. The second transistor TR2 adjacent to the first transistor TR1 has the drain and the source arranged in this sequence in the first direction D1. In
Specifically, the data lines VL1 to VL8 (video lines) arranged in the first direction D1 are connected to the input terminals TI1 to TI8. The data lines VL1 to VL8 are connected to the sources SS1 to SS8 of the transistors TR1 to TR8, and the data lines VL1 to VL8 are connected to sources of next eight transistors in the same manner. The drains DN1, DN2, DN3, . . . of the transistors TR1, TR2, TR3, . . . are connected to the source lines DL1, DL2, DL3, . . . , and the respective source lines are connected to a plurality of pixels (liquid crystal cells, pixel circuits). The respective transistors are arranged such that a longitudinal direction (direction of a channel width) thereof becomes a second direction D2 orthogonal (intersecting) to the first direction D1.
As such, the transistors are arranged such that sequences of the sources and the drains thereof alternate (source, drain, drain, source) with each other, and thereby, the data lines and the source lines are arranged so as to be the data line, the source line, the source line, and the data line. By doing so, a case where two source lines are located between two data lines and a case where two data lines are adjacent to each other are provided. Accordingly, a difference between the parasitic capacitances is made between the data lines.
In addition, both the data line and the source line are arranged in the same region in the arrangement portion of the transistors. In order to densely arrange the pixels and the source lines, the transistors and wires thereof also need to be arranged as densely as possible, and thus, a distance between the lines is significantly narrowed in the portion where both the data line and the source line are arranged. Accordingly, the parasitic capacitance between the data lines in the arrangement portion of the transistors occupies a large proportion of the parasitic capacitance between the data lines in all the data lines, and the difference between the parasitic capacitances between the data lines influences as described above.
In addition, while not illustrated in
The greater the parasitic capacitance between the data lines is, the greater the voltage variation due to coupling of the parasitic capacitances. That is, characteristic of the voltage variation are the same as characteristics of the parasitic capacitance of
3. Drive Circuit
The drive circuit 10 will be described in detail. First, a configuration example and an operation example of the drive circuit 10 will be described with reference to
3.1 Configuration Example and Basic Operation Example of Drive Circuit
In a case where a gradation change direction is a high potential power supply direction, the drive assistance circuit ASi performs assistance such that an output (data voltage, data signal) of the drive circuit 10 is changed to the high potential power supply direction, and in a case where the gradation change direction is a low potential power supply direction, the drive assistance circuit ASi performs assistance such that the output of the drive circuit 10 is changed to the low potential power supply direction. Here, an example in which a voltage value increases as the gradation increases, that is, an example in which the gradation change direction in the high potential power supply direction is a direction in which the gradation increases is described, but the embodiment is not limited to this.
By doing so, it is possible to change the output of the drive circuit 10 (drive unit UNi) in a direction matching the gradation change direction by using the drive assistance circuit ASi. Since the data voltage arriving at the preliminary drive period approaches a target voltage, it is possible to suppress the drive capability required for the amplification circuit AMi, and the like.
The drive assistance circuit ASi includes a first drive transistor group on the high potential power supply side and a second drive transistor group on the low potential power supply side. In a case where the gradation change direction is the high potential power supply direction, the drive assistance circuit ASi changes drive capability of the first drive transistor group based on the gradation change information, and in a case where the gradation change direction is the low potential power supply direction, the drive assistance circuit ASi changes drive capability of the second drive transistor group based on the gradation change information. By doing so, it is possible to perform drive assistance using the two drive transistor groups.
Specifically, the amplification circuit AMi amplifies an output voltage VIN of a D/A conversion circuit (D/A conversion circuit 40 of
In a case where drive capability of the transistors TP1 and TN1 is 1×, drive capability of the transistors TPk and TNk (k is an integer larger than or equal to 1 and smaller than or equal to 9) is 2k-1×. For example, the drive capability is a drain current with respect to the same gate-source voltage, and is set by, for example, a channel width (W/W of L) of the transistor or the number of unit transistors. The transistors TP1 to TP9 and TN1 to TN9 are turned on or off by a control circuit 30. The control circuit 30 calculates drive assistance capability according to the voltage change (gradation change of display data) of the data signal DSi and turns on the transistor of the drive capability corresponding to the drive assistance capability thereof, and the preliminary drive is performed by the transistor which is turned on. In the example of
In a case where the gradation is changed from 0 to 128, the drive assistance circuit ASi changes the data signal DSi from a voltage corresponding to the gradation 0 to a voltage (that is, high potential side power supply voltage VDD Side) corresponding to the gradation 128, during a preliminary drive period TS1. During an amplification drive period TA1 after the preliminary drive period TS1, the amplification circuit AMi outputs the voltage corresponding to the gradation 128 to the output terminal TQi.
During the preliminary drive, the control circuit 30 calculates the drive assistance capability for generating a voltage difference corresponding to the gradation difference during the preliminary drive period TS1 from a difference (128−0=128) between a gradation of the display data in the previous drive and the gradation of a current drive. For example, the larger the gradation difference is, the larger drive assistance capability is set. In addition, the control circuit 30 calculates drive assistance capability according to a target voltage (voltage corresponding to the gradation 128). For example, in a case where a voltage change of the data signal DSi is positive, the more the target voltage is close to the high potential side power supply voltage VDD (the more the gradation is close to a maximum gradation), the larger drive capability is set. In a case where the voltage change of the data signal DSi is positive, the control circuit 30 turns on or off the P-type transistors TP1 to TP9 of the drive assistance circuit ASi such that the transistors have the calculated drive assistance capability. The N-type transistors TN1 to TN9 are turned off.
However, in the present embodiment, the drive assistance capability is calculated in consideration of the voltage variation (gradation change) of other drive units, without simply setting the drive assistance capability for realizing a voltage difference corresponding to a gradation difference 128. Detailed calculation processing will be described below with reference to
In a case where the gradation is changed from 128 to 64, the drive assistance circuit AS1 changes the data signal DS1 from a voltage corresponding to the gradation 128 to a voltage (that is, the low potential side power supply voltage VSS Side) corresponding to the gradation 64, during the preliminary drive period TS2. During an amplification drive period TA2 after the preliminary drive period TS2, the amplification circuit AMi outputs the voltage corresponding to the gradation 64 to the output terminal TQi.
In this case, since the gradation difference is smaller (128−64=64) than the gradation difference during the preliminary drive period TS1, the capability is reduced in terms of the drive assistance capability according to the gradation difference. In addition, since the voltage change of the data signal DSi is negative, the more the target voltage is close to the low potential side power supply voltage VSS (the more the gradation is close to a minimum gradation), the larger drive assistance capability is set. In a case where the voltage change of the data signal DSi is negative, the control circuit 30 turns on or off the N-type transistors TN1 to TN9 of the drive assistance circuit ASi such that the transistors have the calculated drive assistance capability. The P-type transistors TP1 to TP9 are turned off. In this case, the drive assistance capability may also be calculated by processing which will be described below.
3.2 Calculation Processing of Drive Assistance Capability
As illustrated in
Hence, in a case where the gradation change direction of the drive unit adjacent to the ith drive unit UNi is the same as the gradation change direction of the ith drive unit UNi, the drive assistance circuit ASi of the ith drive unit UNi decreases the drive assistance capability. According to the example of
In the example of
In addition, in a case where the (i−1)th drive unit UNi−1 or the (i+1)th drive unit UNi+1 is focused, the gradation change direction of the drive unit is the same as the gradation change direction of the adjacent ith drive unit UNi. Accordingly, as illustrated in B12 and B32, the (i−1)th drive unit UNi−1 and the (i+1)th drive unit UNi+1 may also have the drive assistance capability decreased more than the capability corresponding to an original gradation change. The drive assistance capability of the (i−1)th drive unit UNi−1 and the (i+1)th drive unit UNi+1 is also calculated by adding influence of the adjacent drive unit on a side opposite to the ith drive unit UNi.
In addition, as illustrated in C11 and C21, the gradation change direction (negative direction) of the ith drive unit UNi is different from the gradation change direction (positive direction) of the (i−1)th drive unit UNi−1 Positive direction), in the example of
Hence, in a case where the gradation change direction of the drive unit adjacent to the ith drive unit UNi is different from the gradation change direction of the ith drive unit UNi, the drive assistance circuit ASi of the ith drive unit UNi increases the drive assistance capability. In the example of
A point in which calculation of the drive assistance capability performed by the (i+1)th drive unit UNi+1 is also required, and a point in which the drive assistance capabilities of the (i−1)th and the (i+1)th drive units UNi−1 and UNi+1 are also adjusted to be C11→C12 and C31→C32 are the same as in
However, as illustrated in D11, if there is a change in gradation in a predetermined direction in adjacent drive units, the data voltage of the ith drive unit UNi varies in the same direction as the predetermined direction due to the adjacent capacitance. Hence, the drive assistance circuit ASi of the ith drive unit UNi may operate with drive assistance capability for suppressing (cancelling) the variation of the data voltage.
That is, in a case where the gradation change of the ith drive unit UNi is zero, the drive assistance circuit ASi of the ith drive unit UNi assists drive in accordance with the gradation change direction of the drive unit adjacent to the ith drive unit UNi. In the example of
In this case, on a side where the gradation change directions are the same, a calculation result that the drive assistance capability increases is obtained in the same manner as in
Specifically, the drive assistance capability of the drive assistance circuit ASi of the ith drive unit UNi changes on the basis of total sum information of the gradation change information of the plurality of drive units. Here, the total sum information may be the total sum of the gradation changes of the plurality of drive units UN1 to UNn at a given timing, or may be other information corresponding to the total sum. Alternatively, it is also possible to perform a modification such as excluding a part of the gradation change from the total sum of the gradation changes of all the drive units. For example, the gradation change of the drive unit itself which is a calculation target of the drive assistance capability, or the gradation change of the adjacent drive unit may be excluded from the total sum information.
If the gradation change direction represented by the total sum information is the positive direction, the data voltage of each drive unit varies in the positive direction by the common capacitance. In addition, if the gradation change direction represented by the total sum information is the negative direction, the data voltage of each drive unit varies in the negative direction by the common capacitance. Hence, the drive assistance capability of the drive assistance circuit ASi can be calculated by a relationship between the gradation change direction represented by the total sum information and the gradation change direction of the drive unit UNi which is a target.
For example, E1 of
Hence, in a case where the gradation change direction represented by the total sum information of the gradation change information is the same as the gradation change direction of the ith drive unit UNi, the drive assistance capability of the drive assistance circuit ASi of the ith drive unit UNi decreases (E22). By doing so, the data voltage during the preliminary drive period approaches the target value by combining the drive assistance performed by the drive assistance capability of E22 and the data voltage variation caused by the common capacitance. The amount of adjustment (set value) of the drive assistance capability may be obtained by integrating the gradation change width represented by the total sum information and the common capacitance, or calculation similar thereto. In addition, regarding the common capacitance, it is considered that the fluctuation between original output terminals is not large, and if adjustment is performed by the capacitance circuit CCi, the fluctuation can be further reduced. Hence, a magnitude of the common capacitance may be treated as a common constant by all the drive units, and calculation processing can be easily performed.
The same can also be applied to
The drive assistance capability such as reducing an error due to capacitive coupling of all the data lines can be calculated by performing the common calculation illustrated in
In the above description, adjacency calculation is described with reference to
In a case where a voltage reached by the preliminary drive of the drive assistance circuit ASi deviates from the target voltage (voltage corresponding to the gradation 128 or the gradation 64 in the example of
4. Capacitance Circuit
The output terminal TQi and the output terminal TQi+1 are adjacent to each other, one terminal of the capacitance circuit CCi is connected to the output terminal TQi, and the other terminal of the capacitance circuit CCi is connected to the output terminal TQi+1. A capacitance value of the capacitance circuit CCi can be variably adjusted, and the capacitance value is set by a control signal SCT from the control circuit 30. For example, whether or not the capacitance circuit CCi connects each capacitor of the capacitor group is selected by a switch group. In this case, the control signal SCT turns on and off switches.
In the electro-optical panel of a phase development type illustrated in
According to the present embodiment, connections between each capacitor and the output terminals TQ1 and TQ2 can be controlled by the switch groups SG1 and SG2. Thereby, capacitances between the adjacent output terminals TQ1 and TQ2 can be adjusted by the capacitance circuit CC1, and the capacitance between the data lines can be equalized by correcting fluctuation of the parasitic capacitance between the data lines.
Specifically, the capacitance circuit CC1 includes the first switch group SG1 and the second switch group SG2 as at least one switch group. One terminal of the first switch group SG1 is connected to the first output terminal TQ1 (ith output terminal TQi), and the other end thereof is connected to one terminal of the capacitor group CG1. One terminal of the second switch group SG2 is connected to the second output terminal TQ2 ((i+1)th output terminal TQi+1) adjacent to the first output terminal TQ1 and the other terminal thereof is connected to the other terminal of the capacitor group CG1.
More specifically, the switch group SG1 includes switches SA1 to SA9 (in a broad sense, first to pth switches, p is an integer larger than or equal to 2), the capacitor group CG1 includes capacitors CA1 to CA9 (first to pth capacitors), and the switch group SG2 includes switches SB1 to SB9 (first to pth switches). One terminal of the switch SAj (j is an integer larger than or equal to 1 and smaller than or equal to 9) is connected to the output terminal TQ1 and the other terminal thereof is connected to one terminal of the capacitor CAj. One terminal of the switch SBj is connected to the output terminal TQ2, and the other terminal thereof is connected to the other terminal of the capacitor CAj. The switches SAj and SBj are, for example, transistors which are turned on or off by the control circuit 30 illustrated in
According to the present embodiment, the capacitor group CG1 is connected between the adjacent output terminals TQ1 and TQ2 by the first switch group SG1 and the second switch group SG2. Accordingly, each switch can be turned on or off, and thereby, whether or not each capacitor is connected between the adjacent output terminals TQ1 and TQ2 can be controlled. That is, in a case where the switches SAj and SBj are turned on, the capacitor CAj is connected between the output terminals TQ1 and TQ2, and in a case where the switches SAj and SBj are turned off, the capacitor CAj is not connected between the output terminals TQ1 and TQ2.
In the present embodiment, capacitance values of each capacitor of the capacitor group CG1 are weighted by binary numbers. That is, if the capacitance value of the capacitor CA1 is 1C, the capacitance value of the capacitor CAj is 2j-1C.
By doing so, the capacitance values of the capacitance circuit CC1 can be adjusted by 1C in a range of 1C to 256C (2p-1C in a broad sense) by controlling the switch groups SG1 and SG2 with a binary code.
5. Measurement Circuit
The measurement circuit 20 measures capacitance value information between the plurality of data lines of the electro-optical panel 200. The capacitance values of each capacitance circuit (CC1 to CC5) are set, based on the capacitance value information measured by the measurement circuit 20.
Specifically, the measurement circuit 20 measures capacitance values of parasitic capacitances CP12, CP23, CP34, CP45, and CP51 between the adjacent data lines, and acquires capacitance value information corresponding to the capacitance values. The capacitance value information may be information (data) representing the capacitance value itself, may be information for varying depending on the capacitance value, or may be information associated one-to-one with each capacitance value.
According to the present embodiment, the capacitance value of the capacitance circuit can be adjusted by measuring the capacitance value information between the data lines, based on the capacitance value information, such that the capacitances between the data lines are the same.
In addition, in the present embodiment, the measurement circuit 20 includes a comparison circuit 21 (comparator) to which a determination voltage VR (reference voltage) is input to a first input terminal (for example, a negative polarity terminal) and a switch group 22 that connects one output terminal of the plurality of output terminals TQ1 to TQ5 to a second input terminal (for example, a positive polarity terminal) of a comparison circuit 21.
Specifically, the switch group 22 includes switches SD1 to SD5. Each one terminal of the switches SD1 to SD5 is connected to the output terminals TQ1 to TQ5 and the other terminals thereof are connected to the second input terminal of the comparison circuit 21. The switches SD1 to SD5 are, for example, transistors, and are turned on or off by the control circuit 30. The determination voltage VR is supplied from, for example, a voltage generation circuit 50 of
According to the present embodiment, any one output terminal is connected to a second input terminal of the comparison circuit 21 by the switch group 22, and a voltage of the output terminal is compared with the determination voltage VR. Thereby, it is possible to compare a voltage variation of the output terminal with the determination voltage VR, and to acquire capacitance value information from the comparison result.
More specifically, in a case where a voltage of the ith output terminal TQi changes, the switch group 22 connects the (i+1)th output terminal TQi+1 adjacent to the ith output terminal TQi to the second input terminal. The comparison circuit 21 compares the voltage of the (i+1)th output terminal TQi+1 with the determination voltage VR.
For example, in a case where a voltage of the output terminal TQ3 (TQi) changes, the switches SD1 to SD3 and SD 5 are turned off, the switch SD4 (SDi+1) is turned on, and the output terminal TQ4 (TQi+1) is connected to the second input terminal of the comparison circuit 21. At this time, a voltage CMI of the second input terminal becomes a voltage VQ4 of the output terminal TQ4. The comparison circuit 21 compares a voltage CMI=VQ4 with the determination voltage VR, and outputs a signal CMQ which is the comparison result to the control circuit 30. The control circuit 30 acquires capacitance value information based on the signal CMQ.
The ith output terminal and the (i+1)th output terminal may be adjacent to each other, and a sequence thereof is not limited. That is, a case where first, second, and numbers are attached to the output terminals TQ1, TQ2, . . . is described in the above description, and the embodiment is not limited to this and first, second, . . . and numbers may be attached to the output terminals TQ5, TQ4, . . . .
According to the present embodiment, in a case where the voltage of the output terminal TQi adjacent to the output terminal TQi+1 changes, the voltage variation of the output terminal TQi+1 can be compared with the determination voltage VR by the comparison circuit 21. Since a magnitude of the voltage variation of the output terminal TQi+1 changes depending on the capacitance value of the parasitic capacitance between the adjacent data lines, the capacitance value of the parasitic capacitance can be measured based on the comparison results obtained by the comparison circuit 21.
Data signals DS1 to DS5 (data voltages) from the drive circuit 10 are supplied to each one terminal of the switches SC1 to SC5, and voltages VQ1 to VQ5 of the output terminals TQ1 to TQ5 are supplied to the other terminals of the switches SC1 to SC5. In a case where switch SCi is turned on, VQi=DSi. The switches SC1 to SC5 are, for example, transistors which are turned on or off by the control circuit 30.
For example, it is assumed that the capacitance value of CP45 of the parasitic capacitances CP12, CP23, CP34, CP45, and CP51 is maximum. In this case, the logic level of the output signal CMQ of the comparison circuit 21 is changed by the voltage setting value (4 in the example of
Next, the control circuit 30 increases the voltage setting value of the output terminal TQ3 by 1 (S15). That is, the control circuit 30 increases the voltage setting value of the output terminal TQ3 by +1, and the drive circuit 10 outputs the voltage VQ3=DS3 according to the voltage setting value. For example, the initial value of the voltage setting value is zero, and the initial value is the voltage VQ3=VC. The change of the voltage setting value in step S15 is not limited to +1, and the voltage setting value may vary such that the voltage VQ3 gradually increases (or decreases). Next, the comparison circuit 21 determines whether or not the voltage VQ4 of the output terminal TQ4 is larger than the determination voltage VR (S16). In a case where it is determined that the voltage VQ4 is lower than or equal to the determination voltage VR, the control circuit 30 increases the voltage setting value of the output terminal TQ3 by 1 (S15). Meanwhile, in a case where it is determined that the voltage VQ4 is larger than the determination voltage VR, the control circuit 30 records the voltage setting value of the output terminal TQ3 at that time (S17).
Next, the control circuit 30 sets the voltage setting value of the output terminal TQ3 to a minimum value extracted in step S6 (S35). That is, the control circuit 30 changes the voltage setting value (for example, 0) corresponding to the initial voltage VC to the minimum value (4 in the example of
For example, there is a method of adjusting a capacitance value of a capacitance circuit by measuring only capacitance values of some parasitic capacitances as a modified example of the measuring method and the adjusting method, as will be described below. That is, as described with reference to
6. Electro-Optical Device
The interface circuit 70 performs communication between the display driver 100 and an external processing device (for example, a processing unit 310 of
The control circuit 30 controls each unit of the display driver 100 on the basis of the clock signal or the display data input through the interface circuit 70. For example, the control circuit 30 selects horizontal scan lines of the pixel array 210 or controls display timing of vertical synchronization control and the like of the pixel array 210, and controls the drive circuit 10 in accordance with the display timing.
The voltage generation circuit 50 generates various voltages and outputs the voltages to the drive circuit 10 or the D/A conversion circuit 40. For example, the voltage generation circuit 50 includes a gradation voltage generation circuit (for example, ladder resistors) which generates a plurality of voltages, a power supply circuit which generates power supply of an amplification circuit of the drive circuit 10, a voltage generation circuit which generates the determination voltage VR of the measurement circuit 20, and the like.
The D/A conversion circuit 40 performs D/A conversion of the display data from the control circuit 30, and outputs the converted voltage to the drive circuit 10. That is, a voltage corresponding to the display data is selected among a plurality of voltages supplied from the gradation voltage generation circuit of the voltage generation circuit 50, and the selected voltage is output to the drive circuit 10.
The storage unit 60 stores various types of data (for example, setting data) and the like used for controlling the display driver 100. For example, the storage unit 60 is configured with a nonvolatile memory or RAM (SRAM, DRAM, and the like).
7. Electronic Apparatus
The electronic apparatus 300 includes a processing unit 310 (for example, a processor such as a CPU, or a gate array), a storage unit 320 (for example, a memory, a hard disk, or the like), an operation unit 330 (an operation device), an interface unit 340 (an interface circuit or an interface device), and the electro-optical device 400 (display). The electro-optical device 400 includes the display driver 100 and the electro-optical panel 200 as illustrated in
The operation unit 330 is a user interface that receives various operations from a user. For example, the operation unit includes buttons, a mouse, a keyboard, a touch panel mounted on the electro-optical device 400 (electro-optical panel 200), and the like. The interface unit 340 is a data interface which receives and outputs image data or control data. For example, the interface unit includes a wired communication interface such as a USB, or a wireless communication interface such as a wireless LAN. The storage unit 320 stores data input from the interface unit 340. Alternatively, the storage unit 320 functions as a working memory of the processing unit 310. The processing unit 310 processes display data input from the interface unit 340 or stored in the storage unit 320, and transfers the processed display data to the electro-optical device 400 (display driver 100). The electro-optical device 400 displays an image on a pixel array on the basis of the display data transferred from the processing unit 310.
The present embodiment is described in detail as above, and it will be easily understood by those skilled in the art that many modifications can be made without practically departing from novel matters and effects of the invention. Hence, all the modifications are included in the scope of the invention. For example, a term described together with another term that is broader or equivalent at least once in the specification or drawings, can be replaced with a term different from the term at any position of the specification or the drawings. In addition, all combinations of the present embodiment and modification examples are also included in the scope of the invention. In addition, configurations and operations of the display driver, the electro-optical panel, the electro-optical device, the electronic apparatus, and the like are not limited to the description of the present embodiment, and various modifications can be made.
The entire disclosure of Japanese Patent Application No. 2016-157266, filed Aug. 10, 2016 is expressly incorporated by reference herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-157266 | Aug 2016 | JP | national |
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