Patent Application
20240153435
This application claims priority from Korean Patent Application No. 10-2022-0147999 filed on Nov. 8, 2022 in the Korean Intellectual Property Office and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference.
As a display panel is gradually increased in its size, a display driving device includes a plurality of source driver circuits. When data are simultaneously output to data lines connected to the source driver circuits, broadband electromagnetic interference (EMI) may occur between adjacent data lines.
The inventive concepts relate to a display driving circuit, and more particularly, to a display driving circuit including a plurality of source driver circuits and a display device thereof.
An object of the inventive concepts is to provide a display device having improved EMI level.
Another object of the inventive concepts is to provide a method of manufacturing a semiconductor device, which may improve device performance and reliability.
Some example embodiments of the inventive concepts provide a display driving circuit including a timing controller configured to output image data and a source control signal, a first source driver circuit configured to output first source data of the image data by activating a plurality of first data lines in accordance with the source control signal, the first data lines having a first output spreading time, a second source driver circuit configured to output second source data of the image data by activating a plurality of second data lines in accordance with the source control signal, the second data lines having a second output spreading time, and a third source driver circuit configured to output third source data of the image data by activating a plurality of third data lines in accordance with the source control signal, the third data lines having a third output spreading time, wherein the first output spreading time, the second output spreading time, and the third output spreading time do not overlap.
Some example embodiments of the inventive concepts provide a display device including a display panel including a plurality of pixels connected to a plurality of first data lines and a plurality of second data lines, a timing controller configured to output a first source control signal and a second source control signal, a first source driver circuit configured to output first source data to first pixels, of the plurality of pixels, connected to the plurality of first data lines in a first output enable pattern in accordance with the first source control signal, and a second source driver circuit configured to output second source data to second pixels, of the plurality of pixels, connected to the plurality of second data lines in a second output enable pattern different from the first output enable pattern in accordance with the second source control signal.
Some example embodiments of the inventive concepts provide a display driving circuit including a first source driver circuit configured to output first image data to a plurality of first data lines of a display panel, a second source driver circuit configured to output second image data to a plurality of second data lines of the display panel and a timing controller configured to control the first source driver circuit and the second source driver circuit such that a first output spreading time of the first data lines and a second output spreading time of the second data lines are different from each other.
The objects of the inventive concepts are not limited to those mentioned above and additional objects of the inventive concepts, which are not mentioned herein, will be clearly understood by those skilled in the art from the following description of the inventive concepts.
The display device 100 is a device for displaying contents, which may be a TV, a desktop PC, a laptop computer, a video wall, a large format display (LFD), a digital signage (digital signboard), a digital information display (DID), a projector display, a digital video disk (DVD) player, a refrigerator, a washing machine, a smartphone, a tablet PC, a monitor, smart glasses, a smart watch, etc. Any device capable of displaying contents may be the display device 100.
The display device 100 includes a display panel 400, a processor 120, a communication interface 130, a memory 140, a user interface 150, an image processor 160, a scaler 170, a frame rate converter 180, and/or a timing controller (TCON) 200, but is not limited thereto. The display device 100 may be implemented in a form from which some components are excluded, or may be implemented in a form in which other components are further included.
The display panel 400 may be implemented in various forms such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED), a Plasma Display Panel (PDP), a micro LED, a Laser Display, a VR, and/or Glass. The display panel 400 may also include a driving circuit, a backlight unit or the like, which may be implemented in the form of a-si TFT, a low temperature poly silicon (LTPS) TFT, an organic TFT (OTFT) or the like. The display panel 400 may be implemented as a touch screen coupled with a touch sensor, a flexible display, a three-dimensional (3D) display, etc.
The processor 120 controls an overall operation of the display device 100. In detail, the processor 120 may be connected to each component of the display device 100 to control the overall operation of the display device 100. For example, the processor 120 may be connected to a component such as the display panel 400 to control the operation of the display device 100. In addition, the processor 120 may include an image processor 160, a scaler 170, a frame rate converter 180 and/or a timing controller 200, but is not limited thereto, and each component may be implemented separately. In this case, the processor 120 may be connected to the image processor, the scaler, the frame rate converter and the timing controller to control the operation of the display device 100. This will be described with reference to the drawings that will be described later.
According to some example embodiments, the processor 120 may be implemented as a digital signal processor (DSP), a microprocessor and/or a timing controller (TCON), but is not limited thereto. The processor may include one or more of a central processing unit (CPU), a micro controller unit (MCU), a micro processing unit (MPU), a controller, an application processor (AP) or a communication processor (CP) and/or an ARM processor, and/or may be defined as a corresponding terminology. In addition, the processor 120 may be implemented as a System on Chip (SoC) and/or a Large Scale Integration (LSI), which is embedded with a processing algorithm, and/or may be implemented in the form of a Field Programmable Gate Array (FPGA).
The communication interface 130 is a component that performs communication with various types of external devices in accordance with various types of communication modes. For example, the display device 100 may receive contents and the like from an external device through the communication interface 130.
The communication interface 130 may include a WiFi module, a Bluetooth module, an infrared communication module, a wireless communication module and/or the like. In this case, each communication module may be implemented in the form of at least one hardware chip.
The WiFi module and the Bluetooth module perform communication in a WiFi method and a Bluetooth method, respectively. When the WiFi module and/or the Bluetooth module is used, various kinds of connection information such as SSID and a session key is first transmitted and received and communication is connected using the information, so that the information may be transmitted and/or received. The infrared communication module performs communication in accordance with an Infrared Data Association (IrDA) communication technology for wirelessly transmitting data to a short distance by using infrared rays between a visible ray and the millimeter wave.
The wireless communication module may include at least one communication chip that performs communication in accordance with various wireless communication specifications such as ZigBee, 3rd Generation (3G), 3rd Generation Partnership Project (3GPP), Long Term Evolution (LTE_, LTE Advanced (LTE-A), 4th Generation (4G) and/or 5th Generation (5G), in addition to the above-described communication modes.
The communication interface 130 may include a wired communication interface such as a high-definition multimedia interface (HDMI), a DP, a thunderbolt, a USB, an RGB, a D-SUB and/or a DVI.
In addition, the communication interface 130 may include at least one of a Local Area Network (LAN) module, an Ethernet module and/or a wired communication module for performing communication by using a pair cable, a coaxial cable, an optical fiber cable and/or the like.
The memory 140 may refer to hardware for storing information such as data in an electric or magnetic form so that the processor 120 or the like may access. To this end, the memory 140 may be implemented as at least one of a non-volatile memory, a volatile memory, a flash memory, a hard disk drive (HDD), a solid state drive (SSD), a RAM, and/or a ROM.
At least one instruction or module required, or sufficient, for the operation of the display device 100 and/or the processor 120 may be stored in the memory 140. In this case, the instruction is a sign unit indicating the operation of the display device 100 and/or the processor 120, and may be made of a machine language that is a language that may be understood by a computer. The module may be an instruction set of a series of instructions that perform a particular task of a task unit.
The memory 140 may store data that is information of a bit or byte unit that may represent a character, a number, an image and/or the like. For example, contents, display driving control information and/or the like may be stored in the memory 140.
The memory 140 is accessed by the processor 120, and read/write/correction/deletion/update of instructions, modules and/or data may be performed by the processor 120.
The user interface 150 may be implemented as a button, a touch pad, a mouse, a keyboard or a remote controller, and/or may be implemented as a touch screen capable of performing the above-described display function and a manipulation input function. In this case, the button may include various types of buttons such as a mechanical button, a touch pad and/or a wheel, which are formed on any area, such as a front surface portion, a side portion and/or a rear surface portion, at an external appearance of a main body of the display device 100.
The display device 100 may further include a microphone (not shown), and may receive a user voice through the microphone. The display device 100 may digitize the user voice received through the microphone and perform a corresponding operation based on the digitized user voice. Alternatively, the display device 100 may receive a user voice, which is input by a separate device such as a remote control device (not shown), from the corresponding device.
In this case, the remote control device may be a device manufactured to control the display device 100, but is not limited thereto. The remote control device may be a device in which an application for controlling the display device 100 is installed in a device such as a smartphone.
In this case, the display device 100 may include an IR RX module, and may receive a control signal from the remote control device through the IR RX module, but is not limited thereto. The display device 100 may receive the control signal from the remote control device through Bluetooth, WiFi and/or the like, and any communication specification capable of receiving the control signal from the remote control device may be used.
The remote control device may include a microphone for receiving a user voice, and/or a communication module for digitizing the received user voice and transmitting the digitized user voice to the display device 100.
The processor 120 may directly identify the digitized user voice, but may transmit the digitized user voice to an external server such as an STT server and receive a corresponding control command from the external server.
The image processor 160 may image-process contents. For example, each image processor 160 may decode the received contents.
The scaler 170 may adjust resolution of the contents. For example, the scaler 170 may adjust vertical resolution of the contents based on an equivalent value of vertical resolution of the display panel 400.
The frame rate converter 180 may change a frame rate of the contents. For example, when the display device 100 operates in a first frame mode, the frame rate converter 180 may change the contents of the first frame rate into contents of the second frame rate through a frame skip. Alternatively, when the display device 100 operates in a second frame mode, the frame rate converter 180 may change the contents of the second frame rate into the contents of the first frame rate through frame copying and/or interpolation.
According to some example embodiments, the timing controller 200 may convert image signals input from another component (for example, the processor 120) into data signals, for example, RGB data or YUV data and generate a plurality of control signals (or driving signals) for controlling an operation of the display driving circuit 600.
Although the image processor 160, the scaler 170, the frame rate converter 180 and the timing controller 200 have been described as being individually implemented, the inventive concepts are not limited thereto. For example, at least a portion of the image processor 160, the scaler 170, the frame rate converter 180 and/or the timing controller 200 may be implemented as one component. In addition, at least a portion of the image processor 160, the scaler 170, the frame rate converter 180 and/or the timing controller 200 may be implemented as one component of the display panel 400 and/or the processor 120.
Referring to
The timing controller 200 may generate serial data streams, which include RGB data or YUV data for displaying an image on the display panel 400 in units of frames, and may output the generated serial data streams to the display driving circuit 600 through signal lines.
The display driving circuit 600 may be implemented as including the timing controller 200 as shown in
According to some example embodiments, the display driving circuit 600 may receive data packets from the timing controller 200 through an interface and output a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable signal DE, display data (RGB data) and/or an operation clock (e.g., PCLK). For example, the operation clock PCLK may be a main clock (e.g., MCLK) itself input from the processor 120, or may be a clock transformed from the main clock MCLK input from the processor 120 under the control of the timing controller 200 in accordance with some example embodiments.
In accordance with some example embodiments, the timing controller 200 may receive a feedback signal ‘f’ from a source driver circuit 300 inside the display driving circuit 600 and reset the operation clock PCLK, an image data signal, a source control signal C and/or the like, which are provided to the source driver circuit 300 in accordance with the feedback signal.
According to some example embodiments, the display driving circuit 600 may control various interfaces. For example, the interfaces may include Reduced Swing Differential Signaling (RSDS), mini-LVDS, Point-to-Point Differential Signaling (PPDS), Advanced Intra-Panel Interface (AiPi), mobile industry processor interface (MIPI), mobile display digital interface (MDDI), serial peripheral interface (SPI), inter-integrated circuit (I2C) and/or compact display port (CDP).
The display driving circuit 600 may output display data (RGB data) (or image data streams) to the display panel 400 at a set frame rate.
Referring to
The display panel 400 may include a plurality of pixels PX disposed along a plurality of gate lines G1 to Gn and a plurality of source lines S1 to Sm. According to some example embodiments, in the display panel 400, for example, the gate lines G1 to Gn and the source lines S1 to Sm may be alternately disposed in a matrix form. For example, a gate signal may be supplied to the gate lines, and an image data signal corresponding to the display data (RGB data) may be supplied to the data lines S1 to Sm. The image data signal corresponding to the display data (RGB data) may be provided to the source driver circuit 300 under the control of the timing controller 200.
According to some example embodiments, the timing controller 200 may provide the operation clock (e.g., PCLK) for the operation of the gate driver circuit 500 and/or the source driver circuit 300, the gate control signal for controlling the operation of the gate driver 500 and the source control signal C for controlling the operation of the source driver circuit 300.
According to some example embodiments, the source driver circuit 300 activates the data lines in accordance with the source control signal C received from the timing controller 200, provides the image data to the source lines S1 to Sm, that is, the data lines and/or outputs the image data to the display panel.
According to some example embodiments, the source driver circuit 300 may be implemented with a plurality of source driver circuits 310, 320, . . . , 340 in accordance with the size of the display panel as shown in
According to some example embodiments, the gate driver circuit 500 may be implemented as a plurality of gate driver circuits depending on the size of the display panel as shown in
The plurality of pixels included in the display panel may be connected to the first data lines (D1 to Dn of 310), the second data lines (D1 to Dn of 320) and/or the third data lines (D1 to Dn of 330), and are not repeatedly connected to the data lines different from each other. For example, the first pixels connected to the first data lines are not connected to the second data lines or the third data lines. The second pixels connected to the second data lines are not connected to the third data lines or the first data lines. The third pixels connected to the third data lines are not connected to the first data lines or the second data lines. That is, all, or one or more, of the first pixels connected to the first data lines, the second pixels connected to the second data lines and the third pixels connected to the third data lines are all, or one or more, displayed. That is, each of the first pixels, the second pixels and the third pixels may be a portion of the entire pixels included in the display panel.
The gate driver circuit 500 may drive a switching element (not shown) by applying voltages (e.g., VGH and/or VGL) to the plurality of gate lines G1 to Gn. The source driver circuit 300 may charge the pixels by converting the display data (RGB data) transmitted as a digital value into an analog value.
In some example embodiments, the display driving circuit 600 may output an image in units of frames. During a time (hereinafter, referred to as a scan time) required, or sufficient, to display one frame, which is output, on the display panel 400, the gate driver circuit 500 may sequentially scan the plurality of gate lines G1 to Gn.
The source driver circuit 300 may input a signal (hereinafter, referred to as a data signal) corresponding to the display data (RGB data) to the pixels PX during a time at which the gate driver circuit 500 scans each, or one or more, of the plurality of gate lines G1 to Gn. The pixels display an image in accordance with the input data signal. For example, the RGB data may be implemented as 18 bits, 24 bits, 30 bits (also, each of the RGB data is 6 bits or 8 bits or 10 bits).
Referring to
The timing controller 200 may include a reception (RX) module 210, a buffer memory 220, a timing control circuit 230 and/or a transmission (TX) module 250.
The RX module 210 receives image data from the outside such as the processor 120 and outputs the image data to the buffer memory 220. The buffer memory 220 stores data input to the timing controller 210 through the RX module 210 and outputs the data to the TX module 250. For example, the buffer memory 220 may store the image data for each, or one or more, of the source driver circuits 310 to 340. For example, the buffer memory 220 may store image data, in which control signals Hsync, Vsync and/or Dsync are combined, while being distinguished in units of frames and for each, or one or more, source driver circuit.
The timing control circuit 230 may output source control signals C1, C2, C3 and/or C4 based on the received main clock MCLK. According to some example embodiments, the timing control circuit 230 may output each, or one or more, of the source control signals C1, C2, C3 and/or C4 that are randomly activated. As used herein, the term “randomly activated” means that the source control signals C1, C2, C3 and/or C4 are activated in a random order without being activated at the same time. According to some example embodiments, the source control signals C1, C2, C3 and/or C4 may have an activation period that is equal to a frame period or a multiple of the frame period.
According to some example embodiments, the TX module 250 may output the source control signals C1 to C4 and/or the image data stored in the buffer memory 220 for each, or one or more, of the source driver circuits 310 to 340. For example, the TX module 250 may output source driving data SD1 to SD4 together with the source control signals C1 to C4 in accordance with the output order of the source control signals C1 to C4.
According to some example embodiments, the TX module 250 may receive feedback signals f1 to f4 from the source driver circuits 310 to 340. According to some example embodiments, the timing control circuit 230 may receive the feedback signals f1 to f4 through the TX module 250 and change an activation time point of the source control signals C1 to C4 based on the feedback signals f1 to f4.
Referring to
According to some example embodiments, the data decoder 311 may decode the source driving data SDk (k is any one of 1 to 4) output from the timing controller 200 to restore a plurality of control signals and/or data signals, for example, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync and/or a data synchronization signal Dsync and restore source data of a corresponding source driver circuit.
According to some example embodiments, the data decoder 311 distinguishes only image data pData among the restored signals and outputs the distinguished image data to the data converter 312.
The internal clock generator 313 generates an internal operation clock CLK1 in accordance with the control signals restored from the source driving data SDk, for example, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync and/or the data synchronization signal Dsync.
According to some example embodiments, the internal clock generator 313 may directly receive the source control signals C1 to C4 to generate an internal clock CLK1 corresponding to the source control signals C1 to C4.
According to some example embodiments, the source driver circuit 310 may further include an output spreading circuit 315. The output spreading circuit 315 may generate an output spreading pattern Ci2 in accordance with the source control signals C1 to C4.
According to some example embodiments, the output spreading circuit 315 includes a plurality of output enable patterns, and outputs any one pattern Ci2 corresponding to the source control signals C1 to C4 to the data converter 312. The data converter 312 activates the output of the data lines D1 to Dn based on the received output spreading pattern Ci2. The data converter 312 converts the image data pData received in the serial stream in parallel and outputs the converted image data to the data lines D1 to Dn in accordance with the activated pattern.
According to some example embodiments, the output spreading circuit 315 may output a clock control signal Ci1 to the internal clock generator 313 based on the source control signals C1 to C4. The internal clock generator 313 may adjust a high duty (high width), a low duty (low width) and an enable starting time of the internal operation clock CLK1 based on the clock control signal Ci1 to output the adjusted result to the data converter 312.
According to some example embodiments, the data converter 312 outputs the image data converted in parallel in accordance with at least one of the output spreading pattern Ci2 corresponding to the source control signals C1 to C4 or the internal operation clock CLK1 adjusted based on the source control signals C1 to C4, to the data lines D1 to Dn.
Referring to
The timing controller 200 may be connected to the first to fourth source driver circuits 310, 320, 330 and/or 340 in a point-to-point manner to provide the image data and the source control signals C1, C2, C3 and/or C4. The timing controller 200 may provide the input data (RGB Data) to the respective source driver circuits 310, 320, 330 and/or 340 through the data lines in accordance with the source control signals C1, C2, C3 and/or C4.
According to some example embodiments, the first source driver circuit 310 is connected to the plurality of first data lines (D1 to Dn of 310) of the display panel 400, the second source driver circuit 320 is connected to the plurality of second data lines (D1 to Dn of 320) of the display panel 400, the third source driver circuit 330 is connected to the plurality of third data lines (D1 to Dn of 330) of the display panel 400, and the fourth source driver circuit 340 is connected to the plurality of fourth data lines (D1 to Dn of 340) of the display panel 400. The first data lines, the second data lines, the third data lines and the fourth data lines may refer to those provided by grouping of data lines connected to the same source driver circuit.
The pixels included in the display panel 400 may be connected to any one of the first data lines, the second data lines, the third data lines and/or the fourth data lines to receive the image data from each of the source driver circuits (one of 310, 320, 330 and/or 340) respectively connected to the first data lines, the second data lines, the third data lines and/or the fourth data lines.
Each, or one or more, of the first data lines, the second data lines, the third data lines and/or the fourth data lines is activated with different output patterns in accordance with the source control signals C1, C2, C3 and/or C4. When the image data of all, or one or more, of the data lines is simultaneously output to the display panel 400, ElectroMagnetic Interference (EMI) may occur due to interference between the data lines, thereby affecting the image data provided to the display panel 400 as noise. Therefore, image data output spreading times of the first data lines, the second data lines, the third data lines and/or the fourth data lines may be controlled differently from one another, whereby occurrence of EMI may be reduced, or removed, or minimized. Accordingly, the display panel 400 according to example embodiments may display an image with reduced or no interference and/or the image may be clearer.
According to some example embodiments, the source control signals C1, C2, C3 and/or C4 may be multi-bit type digital signals as the same source control signal. For example, when the source control signals C1, C2, C3 and/or C4 are implemented as multi-bit signals, the operation of each, or one or more, source driver circuit may be controlled in accordance with a bit value corresponding to each, or one or more, position. For example, when one source driver circuit is controlled by a 2-bit signal, the source control signals C1, C2, C3 and/or C4 are received as multi-bit signals such as aabbccdd, and the operation of the source driver circuit 310 may be controlled in accordance with a bit value ‘aa’, the operation of the source driver circuit 320 may be controlled in accordance with a bit value ‘bb’, the operation of the source driver circuit 330 may be controlled in accordance with a bit value ‘cc’ and the operation of the source driver circuit 340 may be controlled in accordance with a bit value ‘dd’.
Otherwise, according to some example embodiments, the source control signals C1, C2, C3 and/or C4 may be multi-bit type digital signals having different values. For example, the timing controller 200 may output the source control signal C1 to the source driver circuit 310, output the source control signal C2 to the source driver circuit 320, output the source control signal C3 to the source driver circuit 330 and/or output the source control signal C4 to the source driver circuit 340.
Otherwise, according to some example embodiments, the source control signals C1, C2, C3 and/or C4 may be analog signals having different values.
According to some example embodiments, the timing controller 200 randomly controls a time point at which image data is input to each, or one or more, of the source driver circuits 310, 320, 330 and/or 340 to differently control an output spreading time in the first data lines, the second data lines, the third data lines and/or the fourth data lines. According to some example embodiments, the timing controller 200 may control a time point at which image data is input to the display panel 400 by varying the time points t1, t2, t3 and/or t4 for activating the respective source driver circuits 310 to 340 in accordance with the source control signals C1, C2, C3 and/or C4.
In the shown example, the first source driver circuit 310 may receive an image data signal at the time point t1, the second source driver circuit 320 may receive an image data signal at the time point t2, the fourth source driver circuit 340 may receive an image data signal at the time point t3, and the third source driver circuit 330 may receive an image data signal at the time point t4. That is, the data lines may be activated in the order of the first source driver circuit 310, the second source driver circuit 320, the fourth source driver circuit 340 and the third source driver 330.
Therefore, the output spreading time may be different between adjacent source driver circuits, for example, between the first source driver circuit 310 and the second source driver circuit 320, between the second source driver circuit 320 and the third source driver circuit 330, and between the third source driver circuit 330 and the fourth source driver circuit 340, whereby occurrence of EMI may be reduced or minimized. Accordingly, the display panel 400 according to example embodiments may display an image with reduced or no interference and/or the image may be clearer.
Alternatively, according to some example embodiments, the timing controller 200 may control the source driver circuits, which have a close distance between the data line, among the plurality of source driver circuits, to allow a difference in the output spreading time to be increased, thereby reducing or minimizing occurrence of EMI. For example, with respect to the first source driver circuit, the source driver circuit having a close distance between the data lines may be the second source driver circuit 320 adjacent thereto, and the source driver circuit having a remote distance between the data lines may be the fourth source driver circuit 340. In this case, the image data may be input in the order of 310, 340 and 320.
In the shown example, it is assumed that the display panel includes a plurality of pixels respectively connected to a total of 4(n+1) data lines, and each source driver circuit is connected to each of (n+1) data lines. The first output enable pattern (
According to some example embodiments, the source driver circuits 310, 320, 330 and/or 340 may include an output spreading circuit (e.g., 315 in
According to some example embodiments, the source driver circuits 310, 320, 330 and/or 340 may include an output spreading circuit (e.g., 315 in
Referring to
For convenience of description, it is assumed that an input time point of the first internal clock 310_CLK1 for the first source driver circuit 310 is t11, an input time point of the second internal clock 320_CLK1 for the second source driver circuit 320 is t21, an input time point of the third internal clock 330_CLK1 for the third source driver circuit 330 is t31 and an input time point of the fourth internal clock 340_CLK1 for the fourth source driver circuit 340 is t41.
According to some example embodiments, the timing controller 200 may control the source driver circuits 310, 320, 330 and/or 340 through the source control signal so that the internal clocks do not overlap equally.
For example, the timing controller 200 may provide the first source driver circuit 310, the second source driver circuit 320, the third source driver circuit 330 and/or the fourth source driver circuit 340 with different enable starting time points t11, t21, t31 and/or t41 of the internal clock SIC_CLK. That is, t11, t21, t31 and/or t41 may not overlap one another at the same time. According to some example embodiments, the first source driver circuit 310, the second source driver circuit 320, the third source driver circuit 330 and/or the fourth source driver circuit 340 may have the input time points t11, t21, t31 and/or t41 in a sequential order, or may randomly have the input time points t11, t21, t31 and/or t41 in a non-sequential order. According to some example embodiments, the order of the input time points t11, t21, t31 and/or t41 may be determined in accordance with a preset (or alternately given) manner (for example, spaced distance between the source driver circuits) that is not sequential in the order of t11, t21, t31 and/or t41.
For example, the timing controller 200 may provide the first source driver circuit 310, the second source driver circuit 320, the third source driver circuit 330 and/or the fourth source driver circuit 340 with different duties of the internal clock SIC_CLK. The timing controller 200 may set a high duty width and/or a low duty width and provide the set duty widths to the source driver circuit. In detail, the timing controller 200 may differently set a duty width w1 of the first internal clock 310_CLK1, a duty width w2 of the second internal clock 320_CLK1, a duty width w3 of the third internal clock 330_CLK1 and/or a duty width w4 of the fourth internal clock 340_CLK1 and provide the different duty widths to the source driver circuits 310, 320, 330 and/or 340, respectively. According to some example embodiments, the duty widths w1, w2, w3 and/or w4 may be different values.
Otherwise, according to some example embodiments, the timing controller 200 may provide the first source driver circuit 310, the second source driver circuit 320, the third source driver circuit 330 and/or the fourth source driver circuit 340 with different enable starting times t11, t21, t31 and/or t41 and different duties of the internal clock SIC_CLK. As shown in
As described above, the timing controller 200 may control the internal clock SIC_CLK1 to spread the rising edge and the falling edge of the clock signal, so that the output spreading times at which the image data is input to the data lines may not overlap each other.
Referring to
The first source driver circuit 310 outputs first image data by spreading to a first output in accordance with the timing information (S12). The second source driver circuit 320 outputs second image data by spreading to a second output in accordance with the timing information (S13). The first output may have an output spreading time different from that of the second output.
The output spreading time may be differently set for each, or one or more, source driver circuit in accordance with some example embodiments described with reference to
Referring to
The feedback signals f1, f2, f3 and/or f4 may include information on an actual output spreading time in each, or one or more, of the source driver circuits 310, 320, 330 and/or 340. That is, the first feedback signal f1 may include information on a first actual output spreading time in the first source driver circuit 310. That is, the actual output spreading time may include a time point at which the source driver outputs the image data to the data lines, that is, the display panel 400.
When receiving the feedback signals f1, f2, f3 and/or f4 from the plurality of source driver circuits, respectively, the timing controller 200 may reset the source control signal so that the output spreading time does not overlap another output spreading time.
According to some example embodiments, the timing controller 200 may reset the source control signal to control an image data input time point in each, or one or more, of the source driver circuits 310 to 340 in accordance with the feedback signal T.
Otherwise, according to some example embodiments, the timing controller 200 may differently control the internal clock CLK1 provided to the source driver circuits 310 to 340 in accordance with the feedback signal ‘f’ so that the output spreading time of each, or one or more, source driver circuit does not overlap another output spreading time. At this time, “controlling the operation clock” means that at least one of the high duty, the low duty or the enable starting time of the operation clock is controlled.
Otherwise, according to some example embodiments, the timing controller 200 may reset the source control signal to select different output enable patterns from among the plurality of output enable patterns included in the source driver circuits 310 to 340 in accordance with the feedback signal T.
Referring to
The first source driver circuit 310 outputs first image data by spreading to a first output in accordance with the timing information (S22). Then, the first source driver circuit 310 may generate a first feedback signal f1 for the first output spreading time and output the first feedback signal f1 to the timing controller 200.
The second source driver circuit 320 outputs second image data by spreading to a second output in accordance with the timing information (S23). The first output may have an output spreading time different from that of the second output. Then, the second source driver circuit 320 may generate a second feedback signal f2 for a second output spreading time and output the second feedback signal f2 to the timing controller 200.
The timing controller 200 may check whether the output spreading time of the plurality of source driver circuits is overlapped with another output spreading time, based on the first feedback signal f1 and the second feedback signal f2, and may control the timing information (S24). The timing controller 200 outputs the controlled timing information to the first source driver circuit 310 and the second source driver circuit 320. Therefore, the display driving circuit 600 may reduce, or prevent, the first output spreading time and the second output spreading time of the following operation from being overlapped with each other.
One or more of the elements disclosed above may include or be implemented in one or more processing circuitries such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitries more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.
Although some example embodiments of the inventive concepts have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that the inventive concepts can be embodied in other specific forms without departing from technical spirits and essential characteristics of the inventive concepts. Thus, some example embodiments are to be considered in all, or one or more, respects as illustrative and not restrictive.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0147999 | Nov 2022 | KR | national |
