Patent Application
20230368723
This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0058017 filed in the Korean Intellectual Property Office on May 11, 2022, the contents of which are incorporated in their entirety herein by reference.
The disclosure relates to a display driver integrated circuit and a driving method of the display driver integrated circuit.
A display panel provides various visual information to a user through an image. Color and resolution expressed in order to provide better image quality are constantly evolving. A display driver integrated circuit (DDI) is used to implement the image on the display panel. A large-capacity memory is sometimes required in order to drive the display driver integrated circuit in various ways.
Example embodiments relate to a display driver integrated circuit capable of performing driving in various modes and a method of driving the display driver integrated circuit.
An example embodiment provides a display driver integrated circuit including: a memory including a plurality of pieces of driving information corresponding to a plurality of pieces of display mode information, the plurality of display mode information regarding a method of processing an image signal; a signal controller including a buffer, the signal controller configured to receive display mode information and image signals from a host, retrieve driving information corresponding to the display mode information among the plurality of pieces of driving information from the memory, the plurality of pieces of driving information including the driving information and write the driving information in the buffer, and convert the image signal into image data based on the driving information written in the buffer; and a data driver configured to generate a plurality of data signals based on the image data.
An example embodiment provides a method that is executed by a display device, the method including: receiving display mode information and an image signal from a host; retrieving driving information corresponding to the display mode information from a memory, the memory storing a plurality of pieces of driving information corresponding to a plurality of pieces of display mode information regarding a method of processing the image signal , the plurality of pieces of driving information including the driving information, writing the driving information in a buffer; and converting the image signal into image data based on the driving information written in the buffer.
An example embodiment provides a display system including: a host configured to generate display mode information based on a user input or an external condition; a signal including a buffer, the signal controller configured receive display mode information and image signals from a host, retrieve one piece of driving information corresponding to the display mode information write it in the buffer, and convert the image signal into image data by using the driving information written in the buffer; and a memory including a plurality of pieces of driving information corresponding to a plurality of pieces of display mode information regarding a method of processing an image signal, the plurality of pieces of driving information including the driving information; a data driver configured to generate a plurality of data signals based on the image data; and a display panel configured to operate in response to the data signals received from the data driver.
In the following detailed description, only certain example embodiments have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described example embodiments may be modified in various different ways, all without departing from the spirit or scope of the disclosure.
Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. In a flowchart described with reference to the drawings, several operations may be merged, some operations may be divided, and specific operations may not be performed.
In addition, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Although the terms first, second, and the like may be used herein to describe various elements, components, steps and/or operations, these terms are only used to distinguish one element, component, step or operation from another element, component, step, or operation.
The display system 1 may include a host 10 and a display device 20.
The host 10 may perform overall control of operations of the display device 20. The host 10 may include an application processor or a system on chip (SOC).
The host 10 may determine an appropriate mode for driving the display device 20 based on a user input or an external condition. The display device 20 may be controlled based on one of a plurality of display modes. For example, the host 10 may determine a display mode in consideration of information related to frequency of an image signal IMS, information related to illumination entering the display device 20, information related to brightness of the display panel 25, user input, and the like. The host 10 may provide information related to the determined display mode to the display device 20. The display mode may indicate a method in which the display panel 25 displays data. For example, the display mode may be a mode in which data is outputted through the display panel 25 with high luminance when there is a lot of illumination entering the display device 20, or when a user sets the brightness of the display panel 25 to be high. A method of generating image data through processing an image signal by the display device 20 may vary based on display mode information.
The host 10 may provide the image signal IMS and a command CMD to the display device 20. The image signal IMS may be a signal of an image to be displayed on the display panel 25. The image signal IMS may include luminance information divided into grays for each pixel of the display panel 25. The image signal IMS may include red, green, and blue data corresponding to red, green, and blue sub-pixels, respectively. The image signal IMS may be generated by the host 10 or transmitted to the host 10 from the outside. The command CMD may include information related to display mode information, vertical synchronization, horizontal synchronization, and the like.
In
The display device 20 may include a display driver IC (DDI) 21 and a display panel 25. The display device 20 may include an organic light emitting diode display, a liquid crystal display, or the like. In addition, the display device 20 may include a flexible display device implemented as an organic light emitting diode display, a rollable display device, a curved display device, a transparent display device, a mirror display device, etc.
The display driver IC 21 may control the display panel 25 based on the image signal IMS and the command CMD. The display driver IC 21 may receive the image signal IMS and the command CMD from the host 10.
The display panel 25 may include a plurality of pixels. Each of (or alternatively, at least one of) the pixels may include a plurality of color (red, green, and blue) sub-pixels.
The display driver IC 21 may include a signal generator 200, a scan driver 250, and a data driver 270.
The scan driver 250 may provide a plurality of scan signals SS to the display panel 25 in response to a first control signal CON1.
The data driver 270 may provide a plurality of data signals GS corresponding to image data DATA to the display panel 25 in response to a second control signal CON2. For example, the data driver 270 may convert the image data DATA into a plurality of data signals corresponding to the data signals GS. Accordingly, the data driver 270 may convert image data DATA of a gray domain into a data voltage of a voltage domain.
The signal generator 200 may include a signal controller 210 and a memory 230. The signal controller 210 may include a buffer 211 and a processor 215. The processor 215 is configured to control an overall operation of the signal controller 210.
The processor 215 may receive the command CMD and the image signal IMS.
The processor 215 may generate the first control signal CON1 and a second control signal CON2 based on the received command CMD and the image signal IMS. Specifically, the processor 215 may retrieve driving information corresponding to the command CMD from the memory 230. In addition, the processor 215 may generate the first control signal CON1 and the second control signal CON2 based on the driving information. The driving information may include information related to display driving timing, such as vertical synchronization, horizontal synchronization, and a data writing period. Alternatively, information related to the driving timing may be included in the command CMD. The first control signal CON1 may include a horizontal synchronization signal.
In addition, the processor 215 may generate the image data DATA based on the command CMD and the image signal IMS received. Specifically, the processor 215 may retrieve driving information corresponding to the command CMD from the memory 230. In addition, the processor 215 may generate the image data DATA based on the driving information and the image signal IMS.
The processor 215 may perform an operation of retrieving driving information corresponding to the command CMD received from the host 10 from the memory 230 in every frame. However, some example embodiments are not limited thereto, and the processor 215 may perform an operation of retrieving driving information corresponding to the command CMD received from the host 10 from the memory 230 with a desired (or alternatively, predetermined) period.
Alternatively, only when mode information indicated by the command CMD received from the host 10 is changed, the processor 215 may perform an operation of retrieving driving information corresponding to the changed mode information from the memory 230.
For example, there may be a case in which the processor 215 receives a first command CMD from the host 10 and then receives a second command CMD following the first command CMD. In this case, when the first command CMD and the second command CMD are the same, the processor 215 may not perform an operation of retrieving driving information corresponding to the received second command CMD from the memory 230. However, when display mode information in the second command CMD is different from display mode information in the first command CMD, the processor 215 may perform the operation of retrieving the driving information corresponding to the received second command CMD from the memory 230. Thereafter, the processor 215 may generate the first control signal CON1, the second control signal CON2, and the image data DATA based on the driving information retrieved from the memory 230 and the image signal IMS.
Alternatively, the processor 215 may determine that the display mode has been changed in consideration of information related to vertical synchronization included in the command CMD received from the host 10 or a frequency at which the image signal IMS is inputted from the host 10. For example, the processor 215 may calculate a frame frequency from information related to vertical synchronization, and when the frame frequency changes, the processor 215 may determine that the display mode has been changed. Similarly, the processor 215 may calculate the frame frequency from an interval between data enable (DE) signals applied when the image signal IMS is inputted, and when the frame frequency changes, the processor 215 may determine that the display mode has been changed. When the processor determine that the display mode has been changed, the processor 215 may perform an operation of retrieving driving information corresponding to the changed mode information from the memory 230.
The processor 215 may write the driving information retrieved from the memory 230 to the buffer 211, and may use the driving information written in the buffer 211 to generate the first control signal CON1, the second control signal CON2, and the image data DATA.
In addition, the processor 215 may generate the second control signal CON2, and the processor 215 may transmit it to the data driver 270 with the image data DATA. The second control signal CON2 may include an internal vertical synchronization signal for distinguishing frames and an internal display activation signal for determining a data writing period. The internal vertical synchronization signal may be a signal delayed by a desired (or alternatively, predetermined) period with respect to a vertical synchronization signal (hereinafter, referred to as an original vertical synchronization signal) generated based on the driving information or generated based on information included in the command CMD. For example, the processor 215 may generate an original vertical synchronization signal based on information related to vertical synchronization in the driving information stored in the memory 230. The processor 215 may receive mode information from the host 10 during a front porch period before the original vertical synchronization signal. The processor 215 may generate an internal vertical synchronization signal for controlling the data driver 270 by delaying the original vertical synchronization signal for a desired (or alternatively, predetermined) delay period. In this case, the desired or predetermined delay period may be a period necessary for the processor 215 to write the driving information retrieved from the memory 230 in the buffer 211.
The internal display activation signal may be a signal delayed by a desired (or alternatively, predetermined) period with respect to a display activation signal (hereinafter, referred to as an original display activation signal) generated based on the driving information or generated based on information included in the command CMD. For example, the processor 215 may generate an original display activation signal based on information related to a data writing period in the driving information stored in the memory 230. The processor 215 may generate an internal display activation signal for controlling the data driver 270 by delaying the original display activation signal for a desired (or alternatively, predetermined) period.
The buffer 211 may receive the driving information retrieved by the processor 215 from the memory 230, and may temporarily store the driving information. The buffer 211 may be configured by using a static random access memory (SRAM) or flip-flop (FF), but some example embodiments are not limited thereto, and various memories may be used.
The memory 230 may include driving information that is required or desired based on a display mode. The memory 230 may be configured as any non-volatile memory. For example, the memory 230 may include a NAND flash memory, a vertical NAND (VNAND) flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase-change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc.
The driving information based on the display mode may be stored in advance in the memory 230 in consideration of a physical characteristic of the display panel 25. The driving information may be information that preferably is updated in one frame unit, and may be in the form of a lookup table (LUT).
For example, the lookup table may include a gamma conversion table based on a gamma value indicating a gamma characteristic. The processor 215 may derive the image data DATA corresponding to the image signal IMS by using a gamma conversion table of the lookup table. A correlation between the image signal IMS and the image data DATA may follow a gamma curve specified based on the gamma value. The processor 215 may convert the image signal IMS into the image data DATA through a gamma conversion table in which the gamma curve based on the gamma value is specified.
The buffer 211 may be configured by using the SRAM, the flip-flop, or the like, and thus a time for the processor 215 to access the buffer 211 to read the driving information may be shorter than a time for the processor 215 to access the memory 230. An amount of driving information that can be stored in the buffer 211 is limited, and thus whenever display mode information is changed, the processor 215 may store and use necessary driving information in the buffer 211 from the memory 230 in which the driving information is stored.
An operating method of the signal generator 200 will be described in detail with reference to
The signal controller 210 may receive mode information from the host 10 (S301). Alternatively, the signal controller 210 may determine the mode information based on a signal received from the host 10.
The signal controller 210 may read the memory 230 to search a lookup table corresponding to the received mode information (S303).
Thereafter, the signal controller 210 may write the searched lookup table in the buffer 211 (S305).
The signal controller 210 may control the scan driver 250 and the data driver 270 based on the lookup table stored in the buffer 211 (S307).
This method provides significant advantages in speed and efficiency at least because of the inclusion of the buffer 211. The look up table can be accessed more quickly and energy efficiently from the buffer 211 than from the memory 230. Accordingly, by copying the look up table to the buffer 210 and using the copied look up table for the other operations of the method, the time required to perform the operations by the signal controller 210 can be reduced. The overall energy consumption by the display drive integrated circuit is also reduced.
The signal generator 400 may include a signal controller 410 and a memory 430.
The signal controller 410 may include a buffer 411 and a processor 415. The processor 415 may perform an operation of converting the image signal IMS into the image data DATA. The processor 415 may process at least one piece of data among a plurality of pieces of data in the image signal IMS. For example, the processor 415 may process at least one of red (R), green (G), or blue (B) data in the image signal IMS, but example embodiments are not limited thereto.
The processor 415 may include an internal memory 413.
The internal memory 413 may be configured as a flip-flop, but example embodiments are not limited thereto. The processor 415 may convert the image signal IMS into the image data DATA based on data stored in the internal memory 413.
The memory 430 may include lookup tables 431a, 431b, . . . , and 431n including driving information based on a display mode.
The signal controller 410 may receive mode information in the command CMD from the host 10. For example, the signal controller 410 may receive the mode information from the host 10 during a front porch period before a time when the original vertical synchronization signal Vsync is generated.
The signal controller 410 may retrieve one lookup table 431k corresponding to the mode information in the memory 430. The signal controller 410 may write the retrieved lookup table 431k in the buffer 411. A time required (or alternatively, desired) for the signal controller 410 to retrieve the lookup table 431k and write the lookup table in the buffer 411 may be predetermined or calculated.
Thereafter, the signal controller 410 may load the lookup table 431k stored in the buffer 411 into the internal memory 413 in response to the original vertical synchronization signal Vsync.
The processor 415 may convert the image signal IMS into the image data DATA by using the lookup table 431k loaded in the internal memory 413.
The signal generator 500 may include a signal controller 510 and a memory 530.
The signal controller 510 may include a buffer 511 and a plurality of processors 515. Each of (or alternatively, at least one of) the processors 515_1, 515_2 . . . , and 515_n may perform an operation of converting the image signal IMS into the image data DATA. For example, each of (or alternatively, at least one of) the processors 515_1, 515_2, . . . , and 515_n may process each of red (R), green (G), and blue (B) data in the image signal IMS, but example embodiments are not limited thereto. Each of (or alternatively, at least one of) the processors 515_1, 515_2, . . . , and 515_n may convert the image signal IMS into the image data DATA in the same manner as the processor 415 described with reference to
The processors 515_1, 515_2, . . . , and 515_n may respectively include corresponding internal memories 513_1, 513_2, . . . , and 513_n.
The internal memories 513_1, 513_2, . . . , and 513_n may be configured as flip-flops, but example embodiments are not limited thereto. The processor 515_m (m being a natural number that is greater than or equal to 1) may convert the image signal IMS into the image data DATA based on data stored in the internal memory 513_m (m being a natural number that is greater than or equal to 1).
The memory 530 may include lookup tables 531a, 531b, . . . , and 531n including driving information based on a display mode.
The signal controller 510 may receive mode information in the command CMD from the host 10. For example, the signal controller 510 may receive the mode information from the host 10 during a front porch period before a time when the original vertical synchronization signal Vsync is generated.
The signal controller 510 may retrieve one lookup table 531k corresponding to the mode information in the memory 530. The signal controller 510 may write the retrieved lookup table 531k in the buffer 511. A time required (or alternatively, desired) for the signal controller 510 to retrieve the lookup table 531k and write the lookup table in the buffer 511 may be predetermined or calculated.
Thereafter, the signal controller 510 may copy the lookup table 531k stored in the buffer 511 by a number of the processors 515 in response to the original vertical synchronization signal Vsync. In
The processor 515_m may convert the image signal IMS into the image data DATA based on the lookup table 531k loaded into the internal memory 513_m.
The signal generator 600 may include a signal controller 610 and a memory 630.
The signal controller 610 may include a buffer 611 and a plurality of processors 615. The processors 615 may perform an operation of converting the image signal IMS into the image data DATA. For example, each of (or alternatively, at least one of) the processors 615_1, 615_2, . . . , and 615_n may process each of red (R), green (G), and blue (B) data in the image signal IMS, but example embodiments are not limited thereto. Each of (or alternatively, at least one of) the processors 615_1, 615_2, . . . , and 615_n may convert the image signal IMS into the image data DATA in the same manner as the processor 415 described with reference to
The memory 630 may include lookup tables 631a, 631b, . . . , and 631n including driving information based on a display mode.
The signal controller 610 may receive mode information in the command CMD from the host 10. For example, the signal controller 610 may receive the mode information from the host 10 during a front porch period before a time when the original vertical synchronization signal Vsync is generated.
The signal controller 610 may retrieve one lookup table 631k corresponding to the mode information in the memory 630. The signal controller 610 may write the retrieved lookup table 631k in the buffer 611. A time required (or alternatively, desired) for the signal controller 610 to retrieve the lookup table 631k and write the lookup table in the buffer 611 may be predetermined or calculated.
Thereafter, the signal controller 610 may transfer the lookup table 631k stored in the buffer 611 to each of (or alternatively, at least one of) the processors 615_1, 651_2, . . . , and 651_n in response to the original vertical synchronization signal Vsync. Each of (or alternatively, at least one of) the processors 615_1, 651_2, . . . , and 651_n may convert the image signal IMS into the image data DATA based on the received lookup table 631k.
At t1, the processor 215 generates and outputs an external vertical synchronization signal Vsync in the form of a pulse. The processor 215 receives the mode information from the host 10 during the front porch period before the time when the external vertical synchronization signal External Vsync is generated. Herein, it has been described that the mode information may be received from the host 10, but may also be determined by the processor 215.
An external display signal Display active is deactivated at a time point t0 and activated at t5. An activation period of the external display signal Display active may be a period in which a data voltage is outputted to the display panel. A period in which data is actually outputted to the display panel 25 is not a frame period 1frame by the external vertical synchronization signal Vsync, but a frame period 1′frame by an internal vertical synchronization signal I_Vsync.
The processor 215 may retrieve any lookup table corresponding to the mode information received from the host 10 from the memory 230, and may write the lookup table in the buffer 211 during a period t2 to t4. As illustrated in
A period t2 to t4 required (or alternatively, desired) for the processor 215 to the retrieve lookup table and write lookup table in the buffer 211 may be predetermined or calculated.
At t3, the processor 215 generates and outputs the internal vertical synchronization signal I_Vsync in the form of a pulse.
At t4, the processor 215 reads the lookup table stored in the buffer 211 in response to the internal vertical synchronization signal I_Vsync. In
At t6, an internal display signal I_Display active is activated. Starting from t6, each of (or alternatively, at least one of) the processors in the signal generator 200 may convert the image signal IMS into the image data DATA based on the lookup table received from the buffer 211. During a period in which the internal display signal I_Display active is activated, the data driver 270 may output a plurality of data voltages corresponding to one frame to a plurality of data lines.
At t7, the external vertical synchronization signal Vsync may be activated again, and the signal generator 200 may repeat the above-described operation.
Referring to
The processor 80 may control input and output of data of the memory 82, the display device 84, and the peripheral device 86, and may perform image processing of image data transmitted between the corresponding devices.
The display device 84 may include a display driving circuit DDI 840 and a display panel DP 842, and may store image data applied through the system bus 88 in a frame memory included in a display driving circuit DDI 840 and display the image data on a display panel DP 842. The display driving circuit 840 may be a display driving circuit according to some example embodiments.
The peripheral device 86 may be a device that converts a motion picture or still image, such as for a camera, scanner, or webcam, into an electrical signal. The image data acquired through the peripheral device 86 may be stored in the memory 82 or may be displayed on the display panel DP 842 in real time.
The memory 82 may include a volatile memory such as a dynamic random access memory (DRAM) and/or a non-volatile memory such as a flash memory. The memory 82 may include a DRAM, a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a NOR flash memory, a NAND flash memory, and a fusion flash memory (e.g., a memory in which a static random access memory (SRAM) buffer, a NAND flash memory, and a NOR interface logic are combined). The memory 82 may store image data acquired from the peripheral device 86 or a video signal processed by the processor 80.
The semiconductor system 8 may be provided in a mobile electronic product such as a smart phone, but the example embodiments are not limited thereto, and may be provided in various types of electronic products that display images.
Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the signal controller 210 and the various processors may be implemented as processing circuitry. The processing circuitry specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.
Processor(s), controller(s), and/or processing circuitry may be configured to perform actions or steps by being specifically programmed to perform those action or steps (such as with an FPGA or ASIC) or may be configured to perform actions or steps by executing instructions received from a memory, or a combination thereof.
It is to be understood that the disclosure is not limited to the disclosed example embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0058017 | May 2022 | KR | national |
