Patent Application
20170193931
The present disclosure relates to a display driving circuit, a method for controlling the display driving circuit, and a display device.
A Liquid Crystal Display (LCD) comprises a color film substrate, an array substrate, and a backlight module for providing a light source. In comparison with the LCD, an Organic Light Emitting Diode (OLED) display has a self-luminous advantage as a current-type light emitting device.
Usually, an OLED display panel may be disposed on a non-display side of a liquid crystal display panel to provide backlight for the LCD. In this case, the backlight module and the color film substrate may be removed from the LCD. Accordingly, structure of the LCD can be simplified.
To drive the OLED display panel and the LCD panel to display, typically, driver ICs for driving the OLED display panel and the liquid crystal display panel need to be set separately. However, as a result, the number of driver ICs will be increased, which leads to a complex product structure and a cost rising.
Embodiments of the present disclosure provide a display driving circuit, a method for controlling the display driving circuit, and a display device, which are capable of solving the problems of a complex product structure and a cost rising due to a separate arrangement of driver ICs for driving the OLED display panel and the liquid crystal display panel.
An aspect of the embodiments of the present disclosure provides a display driving circuit for driving pixel cells located on a liquid crystal display panel and sub-pixels located on an OLED display panel, one of the pixel cells corresponding to at least one of the sub-pixels, the display driving circuit comprising: a shift register unit connected respectively to a source signal terminal, a pulse signal terminal, and at least one signal output terminal, and configured to output a signal inputted from the source signal terminal to the signal output terminal under control of the pulse signal terminal; wherein one pixel cell and at least one sub-pixel corresponding to the one pixel cell are connected to the same signal output terminal.
Optionally, the at least one sub-pixel corresponding to one of the pixel cells includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the at least one signal output terminal includes a first signal output terminal, a second signal output terminal, and a third signal output terminal; the first signal output terminal is connected to the pixel cell and the first sub-pixel; the second signal output terminal is connected to the pixel cell and the second sub-pixel; the third signal output terminal is connected to the pixel cell and the third sub-pixel; and light rays that respectively transmit through the first sub-pixel, the second sub-pixel, and the third sub-pixel constitute light rays of three primary colors.
Optionally, the display driving circuit further comprises a gate driver and a source driver; the gate driver is connected to the pixel cell via a first gate line, and configured to control tuning-on of the pixel cell via the first gate line; the gate driver is connected to the sub-pixel via a second gate line, and configured to control tuning-on of the sub-pixel via the second control gate line; and the source driver is connected to the source signal terminal, and configured to output a data signal to the source signal terminal.
Optionally, the display driving circuit further comprises a pulse signal generator connected to the pulse signal terminal and configured to input a pulse signal to the pulse signal terminal.
Optionally, the first gate line and the second gate line are connected to each other.
Another aspect of the present disclosure provides a display device, comprising a liquid crystal display panel and an OLED display panel disposed opposite to each other, and further comprising any of the display driving circuit described above.
Yet another aspect of the embodiments of the present disclosure provides a method for controlling any of the display driving circuit described above, the method comprising: outputting, by the shift register unit, a signal from the source signal terminal to the signal output terminal under control of the pulse signal terminal; and charging, by the signal output terminal, one pixel cell and the at least one sub-pixel that are connected to the same signal output terminal.
Optionally, in a case where the at least one sub-pixel corresponding to one of the pixel cells includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the at least one signal output terminal includes a first signal output terminal, a second terminal, and a third signal output terminal, the method comprises: inputting a first pulse signal from the pulse signal terminal, outputting a signal from the source signal terminal to the first signal output terminal, and charging the pixel cell and the first sub-pixel via the first signal output terminal by the shift register unit; inputting a second pulse signal from the pulse signal terminal, outputting a signal from the source signal terminal to the second signal output terminal, and charging the pixel cell and the second sub-pixel via the second signal output terminal by the shift register unit; and inputting a third pulse signal from the pulse signal terminal, outputting a signal from the source signal terminal to the third signal output terminal, and charging the pixel cell and the third sub-pixel via the third signal output terminal by the shift register unit.
Optionally, prior to outputting, by the shift register unit, a signal from the source signal terminal to the signal output terminal under control of the pulse signal terminal, the method comprises: controlling, by the gate driver, tuning-on of the pixel cell via the first gate line; controlling, by the gate driver, tuning-on of the sub-pixel corresponding to the pixel cell via the second gate line; and outputting, by the source driver, a data signal to the source signal terminal.
Optionally, prior to outputting, by the shift register unit, a signal from the source signal terminal to the signal output terminal under control of the pulse signal terminal, the method comprises: inputting, by a pulse signal generator, a pulse signal to the pulse signal terminal.
The embodiments of the present disclosure provide a display driving circuit, a method for controlling the display driving circuit, and a display device, the display driving circuit is for driving pixel cells located on a liquid crystal display panel and sub-pixels located on an OLED display panel, one the pixel cell corresponds to at least one sub-pixel. Further, the display driving circuit comprises a shift register unit. The shift register unit is connected respectively to a source signal terminal, a pulse signal terminal, and at least one signal output terminal, and configured to output a signal inputted from the source signal terminal to the signal output terminal under control of the pulse signal terminal. One pixel cell and at least one sub-pixel corresponding to the one pixel cell are connected to the same signal output terminal.
Since one pixel cell and at least one sub-pixel corresponding to the one pixel cell are connected to the same signal output terminal, when the shift register unit outputs a data signal inputted from the source signal terminal to the signal output terminal under the control of the pulse signal terminal, the pixel cell and the sub-pixel that are connected to the signal output terminal can simultaneously receive the data signal to complete pixel charging and perform displaying. In this way, by means of the display driving circuit, pixel cells located on the liquid crystal display panel and sub-pixels located on the OLED display panel can be simultaneously driven to display, without disposing driving circuits separately for the liquid crystal display panel and the OLED display panel, which can simplify product structure and reduce costs.
Hereinafter, the embodiments of the present disclosure will be described clearly and comprehensively in combination with the drawings. Obviously, these described embodiments are merely parts of the embodiments of the present disclosure, rather than all of the embodiments thereof.
It should be noted that, herein, directional terms such as “upper”, “lower”, “left”, and “right” and so on are defined with respect to a schematic placed orientation of the liquid crystal display panel 01 and the OLED display panel 02 in the drawings. As will be appreciated, these directional terms are relative concepts, and used to describe and clarify relative positional relationship that may change accordingly based on a change of orientation in which the liquid crystal display panel 01 and the OLED display panel 02 are placed.
In
It should be noted that, the source signal terminal Source can provide a required data signal Vdata to the liquid crystal display panel 01 and the OLED display panel 02. For example, as shown in
At this time, the data signal Vdata can enable pixel electrodes in the pixel cell 100 on the liquid crystal display panel 01 to be charged, thereby changing electric field between the pixel electrodes and a common electrode of the liquid crystal display panel 01. Accordingly, the aim of changing a deflection angle of liquid crystal molecules in the pixel cell 100 is achieved, so that light outgoing amount of the pixel cell 100 can be adjusted to display different grayscales.
Further, the data signal provided by the source signal terminal Source to the OLED display panel 02 can be used to control a light emitting luminance of OLED in sub-pixels on the OLED display panel 02, so that the backlight luminance provided by the OLED display panel 02 can be adjusted.
To sum up, the display device is composed of the liquid crystal display panel 01 and the OLED display panel 02, and different sub-pixels in the OLED display panel 02 can provide the backlight of different colors that can constitute the three primary colors. Thus, the display device does not require a color filter substrate disposed therein. In addition, a final display effect of the display device at the pixel cell 100 is overlapped by luminance grayscales provided by the liquid crystal display panel 01 and the backlight of three primary colors provided by the OLED display panel 02.
Prior to that the shift register unit SR provides the data signal Vdata inputted from the source signal terminal Source to the pixel cell 100 on the liquid crystal display panel 01 and to the sub-pixel 200 corresponding to the pixel cell 100 and located on the OLED display panel 02, the pixel cell 100 and the sub-pixel 200 need to be in a turned-on state.
In order to turn on the pixel cell 100 and the sub-pixel 200, as shown in
Alternatively, the first gate line S1 and second gate line S2 may be connected, so that there is no need for the gate driver 20 to output a gate scan signal separately to the first gate line S1 and the second gate line S2, and further, the pixel cell 100 and the sub-pixel 200 corresponding to the pixel cell 100 may be turned on simultaneously, thereby a response speed of the display device can be increased.
Alternatively, the shift register unit SR is capable of storing temporarily the data signal Vdata outputted by the source signal terminal Source, and the pulse signal terminal PR can control at what time the shift register unit SR outputs via the signal output terminal OUTPUT the data signal Vdata to the pixel cell 100 and the sub-pixel 200 whose positions correspond to each other. For example, a pulse signal outputted from the pulse signal terminal PS may be provided by a pulse signal generator 30 shown in
The present disclosure makes no limitations to a position of the shift register unit SR, the shift register unit SR may be fabricated on the liquid crystal display panel 01, or on the OLED display panel 02. Optionally, one shift register unit SR may be disposed within each pixel 100, so that all shift register units SR are evenly distributed on the display panel (the liquid crystal display panel 01 or the OLED display panel 02), this can avoid a display effect from being affected by that the shift register units SR have an uneven influence on an effective display region of the pixel cell 100 due to uneven distribution of the shift register units SR on the display panel.
An embodiment of the present disclosure provides a display driving circuit for driving pixel cells located on a liquid crystal display panel and sub-pixels located on an OLED display panel, one the pixel cell corresponds to at least one sub-pixel. Further, the display driving circuit comprises a shift register unit. The shift register unit has a source signal terminal, a pulse signal terminal, and at least one signal output terminal, and configured to output a signal inputted from the source signal terminal to the signal output terminal under control of the pulse signal terminal. One pixel cell and at least one sub-pixel corresponding to the one pixel cell are connected to the same signal output terminal.
Since one pixel cell and at least one sub-pixel corresponding to the one pixel cell are connected to the same signal output terminal, when the shift register unit outputs a data signal inputted from the source signal terminal to the signal output terminal under control of the pulse signal terminal, the pixel cell and the sub-pixel that are connected to the signal output terminal can simultaneously receive the data signal to complete pixel charging and perform displaying. In this way, by means of the display driving circuit, pixel cells located on the liquid crystal display panel and sub-pixels located on the OLED display panel can be simultaneously driven to display, without disposing driving circuits separately for the liquid crystal display panel and the OLED display panel, which can simplify product structure and reduce costs.
The present disclosure makes no limitations to the number of the sub-pixels 200 to which one pixel cell 100 can correspond. In this case, on the one hand, one pixel cell 100 and one sub-pixel 200 corresponding to the pixel cell 100 are connected to the same signal output terminal OUTPUT, so that the larger the number of the sub-pixel 200 to which the pixel cell 100 can correspond is, the larger the number of the output terminals OUTPUT that need to be set is, which results in a complex circuit structure. On the other hand, if one pixel cell 100 corresponds to one sub-pixel 200, then the pixel cell 100 can only emit monochromatic light, so that three adjacent different pixel cells 100 together are able to achieve the three primary colors (e.g., R, G, B) for displaying. This will cause a resolution of the display device composed of the liquid crystal display panel 01 and the OLED display panel 02 to decrease, and exquisiteness of a displayed image to reduce. Three different sub-pixels 200 can emit light of a different color respectively to constitute the three primary colors.
To sum up, optionally, one pixel cell 100 corresponds to three sub-pixels 200 capable of emitting light of different colors. In this way, each pixel cell 100 is able to achieve displaying of the three primary colors, which can ensure that the composed display device has a high resolution, and a display effect of the display device is improved.
In this case, the first signal output terminal OUTPUT1 is connected to the pixel cell 100 and the first sub-pixel 211.
The second signal output terminal OUTPUT2 is connected to the pixel cell 100 and the second sub-pixel 212.
The third signal output terminal OUTPUT3 is connected to the pixel cell 100 and the third sub-pixel 213.
For example, light rays transmit respectively through the first sub-pixel 211, the second sub-pixel 212, and the third sub-pixel 213 constitute light of the three primary colors.
It should be noted that the present disclosure makes no limitations to light ray that constitute the three primary colors. They may be red light, green light, and blue light, or cyan light, magenta light, and yellow light. For convenience of description, hereinafter, descriptions are provided with the first sub-pixel 211 emits red light, the second sub-pixel 212 emits green light, and the third sub-pixel 213 emits blue light as an example.
In this way, the data signal Vdata inputted from the source signal terminal Source can pass through the shift register unit SR, and be outputted, to the pixel cell 100 and the first sub-pixel 211 via the first signal output terminal OUTPUT1, to the pixel cell 100 and the second sub-pixel 212 via the second signal output terminal OUTPUT2, and to the pixel cell 100 and the third sub-pixel 213 via the third signal output terminal OUTPUT3, respectively, at different times under the control of the pulse signal data terminal PS. Herein, a valid time length of the data signal Vdata inputted from the source signal terminal Source (a high voltage level maintenance time length of the data signal Vdata as shown in
It should be noted that, the at least one signal output terminal OUTPUT including the first signal output terminal OUTPUT1, the second signal output terminal OUTPUT2, and the third signal output terminal OUTPUT3 refers to that the shift register unit SR may be composed of a single shift register having three signal output terminals, i.e., the first signal output terminal OUTPUT1, the second signal output terminal OUTPUT2, and the third signal output terminal OUTPUT3. Alternatively, the shift register unit SR may be composed of three shift registers each having one signal output terminal. For example, when the shift register unit SR is composed of a first shift register, a second shift register, and a third shift register, the first shift register has the first signal output terminal OUTPUT1, the second shift register has the second signal output terminal OUTPUT2, and the third shift register has the third signal output terminal OUTPUT3. The present disclosure makes no limitations to a concrete structure of the shift register unit SR, as long as the shift register unit SR can output the signal from the signal source terminal Source to the signal output terminal under the control of the pulse signal terminal PS.
Next, in conjunction with
Next, the pulse signal terminal PS of the shift register unit SR is input a first pulse signal PS1, so that the shift register unit SR outputs the data signal Vdata inputted from source signal terminal Source to the first signal output terminal OUTPUT1, and charges the pixel cell 100 and the first sub-pixel 211 through the first signal output terminal OUTPUT1.
In this case, the first sub-pixel 211 can emit red light (R) whose luminance matches the data signal Vdata. Further, the data signal Vdata charges the pixel cell 100 to cause grayscale values of the pixel cell 100 to match the data signal Vdata.
Next, the pulse signal terminal PS of the shift register unit SR is input a second pulse signal PS2, so that the shift register unit SR outputs the data signal Vdata inputted from source signal terminal Source to the second signal output terminal OUTPUT2, and charges the pixel cell 100 and the second sub-pixel 212 via the second signal output terminal OUTPUT2.
In this case, the second sub-pixel 212 can emit green light (G) whose luminance matches the data signal Vdata. Further, the data signal Vdata charges the pixel cell 100 to cause the grayscale values of the pixel cell 100 to match the data signal Vdata.
Next, the pulse signal terminal PS of the shift register unit SR is input a third pulse signal PS3, so that the shift register unit SR outputs the data signal Vdata inputted from source signal terminal Source to the third signal output terminal OUTPUT3, and charges the pixel cell 100 and the third sub-pixel 213 via the third signal output terminal OUTPUT3.
In this case, the third sub-pixel 213 can emit blue light (B) whose luminance matches the data signal Vdata. Further, the data signal Vdata charges the pixel cell 100 to cause the grayscale values of the pixel cell 100 to match the data signal Vdata.
As a result, in an image frame, i.e., within a time period during which the gate drive signal Gate in
Another aspect of the embodiments of the present disclosure provides a display device comprising the liquid crystal display panel 01 and the OLED display panel 02 that are disposed opposite to each other as shown in
It should be noted that, in the embodiments of the present disclosure, the display device may be a liquid crystal TV, a digital photo frame, a mobile phone, a tablet computer, or any products or components having a display function.
In step S101, the shift register unit SR as shown in
In step S102, the pixel cell 100 and the sub-pixel 200 that are connected to the same signal output terminal OUTPUT are charged through the signal output terminal OUTPUT.
Since one pixel cell and at least one sub-pixel corresponding to the one pixel cell are connected to the same signal output terminal, thus when the shift register unit outputs a data signal inputted from the source signal terminal to the signal output terminal under the control of the pulse signal terminal, the pixel cell and the sub-pixel that are connected to the signal output terminal can simultaneously receive the data signal to complete pixel charging and perform displaying. In this way, by means of the display driving circuit, pixel cells located on the liquid crystal display panel and sub-pixels located on the OLED display panel can be simultaneously driven to display, without disposing driving circuits separately for the liquid crystal display panel and the OLED display panel, which can simplify product structure and reduce costs.
On basis of this, prior to that the shift register unit SR provides the data signal Vdata inputted from the source signal terminal Source to the pixel cell 100 on the liquid crystal display panel 01 and to the sub-pixel 200 corresponding to the pixel cell 100 and located on the OLED display panel 02, the pixel cell 100 and the sub-pixel 200 need to be in a turned-on state. Besides, since the source signal terminal Source needs to provide a required data signal Vdata to the liquid crystal display panel 01 and the OLED display panel 02, therefore, prior to the step S101, the method may further comprise:
First, the gate driver 20 shown in
For example, the gate driver 20 inputs the gate drive signal Gate to the first gate line S1, and then turns on the pixel cell 100 via the gate driver signal Gate.
Next, the gate driver 20 controls the sub-pixel 200 corresponding to the pixel cell 100 to be turned on via the second gate line S2.
For example, the gate driver 20 inputs the gate drive signal Gate to the second gate line S2, then turns on the sub-pixel 200 corresponding to the pixel 100 via the gate driver signal Gate.
Thereafter, the source driver 10 shown in
The data signal Vdata can enable the pixel cell 100 and the sub-pixel 200 corresponding to the pixel cell 100 to be charged. As a result, a final display effect of the display device composed of the liquid crystal display panel 01 and the OLED display panel 02 at the pixel cell 100 is overlapped by the luminance grayscales provided by the liquid crystal display panel and the backlight of three primary colors provided by the OLED display panel 02.
In addition, the shift register unit SR is capable of storing temporarily the data signal Vdata input from the source signal terminal Source, and the pulse signal terminal PS can control at what time the shift register unit SR outputs via the signal output terminal OUTPUT the data signal Vdata to the pixel cell 100 and the sub-pixel 200 whose positions correspond to each other. Thus, in a case where the display driving circuit described above comprises the pulse signal generator 30, prior to the step S101, the method further comprises that the pulse signal generator 30 inputs a pulse signal to the pulse signal terminal PS.
In order to improve a resolution of the display device composed of the liquid crystal display panel 01 and the OLED display panel 02 on the basis of avoiding a complex circuit structure, optionally, one pixel cell 100 may correspond to three sub-pixels 200 capable of emitting light of different colors. That is to say, the at least one sub-pixel 200 corresponding to one pixel cell 100 includes a first sub-pixel 211, a second sub-pixel 212, and a third sub-pixel 213, wherein the at least one signal output terminal OUTPUT includes a first signal output terminal OUTPUT1, a second signal output terminal OUTPUT2, and a third signal output terminal OUTPUT3.
In step S201, the gate driver 20 controls the pixel cell 100 as well as the first sub-pixel 211, the second sub-pixel 212, and the third sub-pixel 213 corresponding to the pixel cell 100 to be turned on.
For example, the gate driver 20 inputs a gate scan signal Gate to the first gate line S1, to turn on the pixel cell 100. Besides, since the first sub-pixel 211, the second sub-pixel 212, and the third sub-pixel 213 are located in the same row, thus each of them is connected to the second gate line S2. Therefore, when the gate driver 20 inputs the gate scan signal Gate to the second gate line S2, all of the first sub-pixel 211, the second sub-pixel 212, and the third sub-pixel 213 can be turned on.
In step S202, the pulse signal terminal PS is input a first pulse signal PS1, so that the shift register unit SR outputs the data signal Vdata inputted from source signal terminal Source to the first signal output terminal OUTPUT1, and charges the pixel cell 100 and the first sub-pixel 211 via the first signal output terminal OUTPUT1.
In this way, the first sub-pixel 211 can emit red light (R) whose luminance matches the data signal Vdata. Further, the data signal Vdata charges the pixel cell 100 to cause the grayscale values of the pixel cell 100 to match the data signal Vdata.
In step S203, the pulse signal terminal PS is input a second pulse signal PS2, so that the shift register unit SR outputs the data signal Vdata inputted from source signal terminal Source to the second signal output terminal OUTPUT2, and charges the pixel cell 100 and the second sub-pixel 212 via the second signal output terminal OUTPUT2.
In this way, the second sub-pixel 212 can emit green light (G) whose luminance matches the data signal Vdata. Further, the data signal Vdata charges the pixel cell 100 to cause the grayscale values of the pixel cell 100 to match the data signal Vdata.
In step 204, the pulse signal terminal PS of the shift register unit SR is input a third pulse signal PS3, so that the shift register unit SR outputs the data signal Vdata inputted from source signal terminal Source to the third signal output terminal OUTPUT3, and charges the pixel cell 100 and the third sub-pixel 213 via the third signal output terminal OUTPUT3.
In this way, the third sub-pixel 213 can emit blue light (B) whose luminance matches the data signal Vdata. Further, the data signal Vdata charges the pixel cell 100 to cause the grayscale values of the pixel cell 100 to match the data signal Vdata.
To sum up, in an image frame, i.e., within a time period during which the gate drive signal Gate in
The above described merely are specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, modification and replacements easily conceivable for those skilled in the art within the technical range revealed by the present disclosure all fall into the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure is based on the protection scope of the claims.
The present application claims priority of the Chinese Patent Application No. 201610004880.9 filed on Jan. 4, 2016, the entire disclosure of which is hereby incorporated in full text by reference as part of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201610004880.9 | Jan 2016 | CN | national |
