Patent Application
20080180463
1. Field of the Invention
The present invention relates to a display driving device a display device, and to the driving method thereof, and in particular, relates to a display driving device that drives display pixels comprising current-controlled light emitting elements that emit light in specific brightness gradation levels through supplying currents to the driving device, a display device comprising a display panel wherein the aforementioned display pixels are arrayed in a plurality of rows and columns for displaying an image, and to the driving method thereof.
2. Description of the Related Art
In recent years, organic electroluminescent display panels, which are display panels wherein organic electroluminescent elements, which are self-luminous elements, are arrayed two-dimensionally, have been known as display devices for electronic equipment such as mobile telephones and portable music players.
In particular, when compared to the widely used liquid crystal display devices, organic electroluminescent display panels to which the active matrix drive method has been applied, can provide faster display response speeds, reduced dependency on the viewing angle, increased brightness, heightened contrast, increased display quality and resolution, and so forth. Additionally, organic electroluminescent display panels do not require backlights or light guide plates, as with a liquid crystal display devices, and thus have the superior characteristics that they can be made thinner and lighter. Because of this, organic electroluminescent display panels are anticipated to be applied to a variety of electronic devices in the future.
On the other hand, in recent years mobile telephones, the display is more and more used to display video information (image information), such as still images and videos, and the like, in addition to text information, through the mobile telephones' provision of camera functions and television reception functions. Typically, in this type of video information, there are more curved expressions than there are linear expressions. Because of this, delta arrangements and mosaic arrangements of display pixels are used in display panels used in digital cameras, mobile telephones, and the like.
When the image data is displayed in color, the display pixels that are arranged in the display panel are structured with the three colored pixels of red (R), green (G), and blue (B) as a single set, where, in the delta arrangement, these colored pixels are arranged shifted by a predetermined pixel pitch portion. In regards to the methods for connecting the data lines in this case, there is the so-called “same-color interconnection” method wherein the colored pixels PXp of the same color in each row are connected together by a data line DLp that is disposed in the column direction (the vertical direction in the figure) as shown in, for example,
In the same-color interconnections illustrated in
Here, when an organic electroluminescent display panel to which an active drive method is applied is used as the display panel described above, typically a structure is used comprising organic electroluminescent elements, which are light emitting elements, as the individual display pixels, along with pixel driving circuits for supplying drive currents (light emitting drive currents) in accordance with the display data. The pixel driving circuits, which will be described in detail below, have a circuit structure comprising a plurality of switching elements (such as thin film transistors).
Because of this, in the case wherein same-color interconnections are applied in a delta arrangement as showed in
On the other hand, in the case wherein the different-color interconnections are applied in the delta arrangement, the degree of the serpentine pattern for the data lines is reduced, as shown in
The present invention has the benefit of enabling the provision of a display driving device, a display device, and a driving method thereof, capable of displaying with excellent quality desired image data using general-use current drivers in display panels having an array of pixels of a plurality of colors wherein the data lines are different-color interconnections.
In order to achieve the benefit described above, the display driving device for driving, based on display data and through a data line, each of a plurality of pixels of different colors, disposed along the data line, connected to the data line and put into a selected state sequentially, comprising:
a current generating circuit that generates and outputs a data current which has a current value corresponding to a brightness designated by the display data; and
a current control unit that receives the data current that is outputted from the current generating circuit; generates a gradation current, based on the received data current and the display characteristics of each display pixel that is put into the selected state; and supplies, to the data line, the generated gradation current, so that the pixel emits light at the designated brightness based on the display characteristics thereof.
In order to achieve the benefit described above, the display device for displaying a color image defined by display data, comprising:
a pixel array in which a plurality of scan lines are arranged in a row direction, a plurality of data lines are arranged in a column direction, a plurality of display pixels are arranged and have a plurality of colors, each of the display pixels is connected to respective one of the scan lines and respective one of the data lines and arranged in a neighborhood of an intersection of the respective scan line and respective data line, and the display pixels of at least two different colors of the plurality of colors are connected to each of the data lines;
a scan driving circuit that sets the plurality of display pixels into a selected state by row;
a current generating circuit that generates and outputs a data current which has a current value corresponding to a brightness designated by the display data; and
a current control unit that: receives the data current that is outputted from the current generating circuit; generates a gradation current, based on the received data current and the display characteristics of each display pixel that is put into the selected state by the scan driving circuit; and supplies, to the data line, the generated gradation current, so that the pixel emits light at the designated brightness based on the display characteristics thereof.
In order to achieve the benefit described above, the driving method for a display device for displaying a color image defined display data, wherein:
the display device comprises a pixel array, in which a plurality of scan lines are arranged in a row direction, a plurality of data lines are arranged in a column direction, plurality of display pixels are arranged and have a plurality of colors, each of the display pixels is connected to respective one of the scan lines and one of the data lines and arranged in a neighborhood of the intersection of the respective scan line and respective data line, and the display pixels of at least two different colors of the plurality of colors are connected to each of the data lines;
the driving method comprises:
an operation of setting the plurality of display pixels into a selected state by row;
an operation of generating and outputting a data current which has a current value corresponding to a brightness designated by the display data in accordance with the timing with which the selected state is set;
an operation of receiving the data current; and
an operation of generating, a gradation current, based on the received data current and the display characteristics of each display pixel that is put into the selected state, and supplying through each data line, to the display pixel that is put into the selected state, the generated gradation current, in such a way that the generating and supplying operation is performed in synchronization with the timing with which the display pixel that is connected to each data line is set into the selected state.
A display driving device, a display device, and the driving method thereof, according to the present invention, will be described in detail below based on embodiments illustrated in the drawings.
As illustrated in
The pixel array 110 is arranged in a delta arrangement of color pixels (display pixels) PIX, in the three colors of red (R), green (G), and blue (B), in n rows and m columns (where n and m are positive integers) in the neighborhood of each of the intersections of a plurality of scan lines SL, arranged in the row direction, and a plurality of data lines DL, arranged in the column direction. The scan driver 120 sequentially sets the color pixels FIX in each row into the selected state through applying a scan signal Vsel, with a specific timing, to each of the scan lines SL. The current driver 130 receives the display data that is supplied by the display signal generating circuit 160, described below, and generates a data current Idata that has a current value in accordance with the brightness gradation value that is included in the display data, and supplies the data current Idata to the current control unit 140, described below. The current control unit 140 is connected to the data line DL for each row and receives the data current Idata in accordance with the display data that is supplied from the current driver 130, described above, converts the data current Idata into a gradation current Ipix, having a current value in accordance with the current efficiency (the light emitting efficiency; display characteristic) of each color pixel PIX, and supplies this gradation current Ipix to each data line DL. Based, for example, on the timing signal that is supplied from the display signal generating circuit 160, the system controller 150 generates and outputs the various control signals (the scan control signal, the data control signal, and the current control signal, and the like) that control the operating states of, at least, the scan driver 120, the current driver 130, and the current control unit 140. Based on, for example, a video signal that is supplied from the outside of the display device 100A, the display signal generating circuit 116 generates and supplies to the current driver 130 display data having brightness gradation values comprising digital data, and generates or extracts, and provides to the aforementioned system controller 150, timing signals (a system clock, or the like) for displaying an image of the display data in the display region that is formed by the pixel array 110.
Each of the structures described above will be explained in detail below.
The pixel array 110 that can be applied to a display device according to the present embodiment is a regular repeating arrangement of color pixels PIX, comprising the three colors of red (R), green (G), and blue (B) in the row direction (in the horizontal direction in the figure) as shown in, for example,
A plurality of scan lines SL is arranged with each scan line SL in the form of a straight line in the row direction (the horizontal direction in the figure), and each is connected to the color pixels PIX that are arranged in the regular RGB sequence described above. On other hand, a plurality of data lines DL is arranged with each in a serpentine pattern in the column direction (the vertical direction in the figure), and each is connected to color pixels PIX that are of different colors in the even rows and the odd rows. In other words, so-called “different-color interconnections,” wherein two colors of color pixels PIX, which are different for each row (for example, red (R) color pixels PIX in rows 1, 3, . . . (2i−1) (where “i” is a positive integer; that is, odd rows) and green (G) color pixels PIX in rows 2, 4, . . . , 2i (that is, even rows)) are connected alternatingly to a single data line DL, is applied to the pixel array 110 according to the present embodiment.
Each color pixel PIX is disposed in the neighborhood of an intersection between a scan line SL and a data line DL, and is connected to the scan line SL and the data line DL that forms the intersection. Additionally, each color pixel PIX is provided with a current-controlled light emitting element, such as an organic electroluminescent element, and a pixel driving circuit that causes the light emitting element to perform a light emitting operation at a desired brightness based on display data (a gradation current). Note that an example of a circuit structure for a color pixel PIX that can be applied in the present embodiment will be described in detail below.
The scan driver 120 sets the color pixels PIX into the selected state, by row, through applying sequentially the scan signal Vsel (for example, the HIGH level) to the scan line SL for each row disposed in the pixel array 110, based on a scan control signal supplied by the system controller 150. By doing so, the scan driver 120 controls the gradation current Ipix, supplied by the current driver 130 and the current control unit 140 through the data line DL for each column, so as to write to the individual color pixels PIX that are set to the selected state row by row.
Here the scan driver 120, although not shown in the figure, is provided, for example, with a shift register circuit that outputs sequentially a shift signal corresponding to the scan line SL for each row based on a scan start signal and a scan clock signal supplied as scan control signals from the system controller 150, described below, and an output circuit (output buffer) that converts the shift signal, which is outputted sequentially from the shift register circuit, to a specific signal level (the select level or the non-select level) and outputs the results as the scan signal Vsel to the scan lines SL for each row based on the output control signal supplied as a scan control signal from the system controller 150.
The current driver 130 sequentially and repetitively performs, for each row, the operations of sequentially receiving and latching, with a specific timing for each row, the display data that is supplied from the display signal generating circuit 160, described below, based on a data control signal that is supplied from the system controller 150, generating the data current Idata having a current value in accordance with the brightness gradation value that is included in the display data, and supplying this data current Idata to the current control unit 140 (current value converting circuit unit 140-1, 140-2, . . . 140-m), described below.
The current driver 130 comprises, as shown in
The shift register circuit 131 shifts sequentially a sampling start signal STR and outputs the shift signal, based on a shift clock signal CLK that is supplied as a data control signal from the system controller 150. The data register circuit 132 sequentially receives the brightness gradation values D0 through Dm of display data comprising one line worth of digital data that is supplied from the display signal generating circuit 160 based on the input timing of the shift signal that is outputted from the shift register circuit 131. The data latch circuit 133 latches one row worth of display data D0 through Dm received from the data register circuit 132, based on the data latch signal STB. The D/A converter 134 converts the latched display data D0 through Dm into the respective specific analog signal voltages (data voltages Vdata (Vdata 0 through Vdata m)) based on gradation reference voltages V0 through Vp supplied from a power supply, not shown. The voltage/current converter and current supply circuit 135 generates the respective data currents Idata (Idata 0 through Idata m) having current values in accordance with the brightness gradation values D0 through Dm of the display data, based on the data voltages Vdata, and supplies these simultaneously to the current control unit 140 (the current value converting circuit units 141-1, 141-2, . . . ), described below, based on an output enable signal OE supplied from the system controller 150.
The current control unit 140 operates based on a current control signal supplied from the system controller 150. The current control unit 140 simultaneously receives, during a first operating period, the data currents Idata Ibased on the brightness gradation values of one row of display data supplied by the current driver 130, and latches these individually in the color pixel PIX for each individual column. The current control unit 140 also supplies simultaneously, through each data line DL to each color pixel PIX, the gradation currents Ipix that have been generated so as to be in accordance with the current efficiencies of each of the color pixels PIX that have been set into the selected state, based on the latched data current Idata, during a second operating period wherein the scan line SL of a specific row has been set into the selected state by the scan driver 120, described above.
During this second operating period, the current control unit 140 also performs an operation that receives, from the current driver 130, and latches data currents Idata for each column, corresponding to the display data for the color pixels PIX for the row that will be set into the selected state during the next operating period, doing so in parallel with the operation for supplying the gradation currents Ipix through each data line DL to each color pixel PIX that has been set to the selected state.
As shown in, for example,
Note that only the current control unit (current value converting circuit unit) connected to a data line DL of a specific column (for example, the jth column; where j is any given integer in the range of 1=j=m) disposed in the pixel array 110 is shown here.
Additionally,
The current value converting circuit units 141 (141-1, 141-2, . . . , 141-m shown in
The current latching/converting circuit 142a has a circuit structure, as shown in
Here a switching control signal LC1, which is supplied as a current control signal from the system controller 150, is applied to the control terminal (gate) of the transistor Ta5. Furthermore, a switching control signal LC2, which is supplied as a current control signal from the system controller 150, is applied to the control terminals of the transistors Ta1 and Ta2. Additionally, the control terminals of the transistors Ta3 and Ta4 are both connected to the contact NA1, so that the transistors Ta3 and Ta4 form a current mirror circuit. Additionally, a specific low-voltage potential Vee, having a voltage level that is lower than the ground voltage GND, is applied to the contact NA3.
Additionally, as with the current latching/converting circuit 142a, the current latching/converting circuit 142b also has a circuit structure comprising: transistors Tb1 and Tb2, the current paths thereof being connected in series between a contact NB1 and the input contact IN; a transistor Tb3, the current path thereof being connected between the contact NB2 of the transistors Tb1 and Tb2 and a contact NB3; transistors Tb4 and Tb5, the current paths thereof being connected in series between the contact NB3 and the output contact OUT; and a capacitor CB that is connected between the contacts NB1 and NB3.
Here the switching control signal LC1 is applied to the control terminals of the transistors Tb1 and Tb2. Moreover, the switching control signal LC2 is applied to the control terminal of the transistors Tb5. Additionally, the control terminals of the transistors Tb3 and Tb4 are both connected to the contact NB1, so that the transistors Tb3 and Tb4 form a current mirror circuit. Moreover, as with the contact NA3, described above, the low-voltage potential Vee is applied to the contact NB3.
Note that the transistors Ta1, Ta2, and Ta5 provided in the current latching/converting circuit 142a, and the transistors Tb1, Tb2, and Tb5 provided in the current latching/converting circuit 142b, form a contact switching circuit according to the present invention. Moreover the transistor Ta3 and capacitor CA provided in the current latching/converting circuit 142a, and the transistor Tb3 and capacitor CB provided in the current latching/converting circuit 142b, form a current latching circuit according to the present invention.
Additionally, the current ratios between the input currents (the data current Idata) and the output currents (the gradation current Ipix) in the current mirror circuits (the transistors Ta3 and Ta4 and the transistors Tb3 and Tb4), provided in the current latching/converting circuits 142a and 142b, are set depending on the current efficiencies (see below) of the color pixels PIX to which the gradation currents Ipix, which are the output currents of the current value converting circuit units 141 (the current latching/converting circuits 142a and 142b) are applied, so as to be, for example, 1:1 or x:1 (x>1).
Here the individual RGB color pixels that are applied to the color display are known typically to have different brightness, depending on the color of light emitted (different light emitting efficiencies, or in other words, different current efficiencies) when a light emitting drive current having a constant current value is applied to the light emitting elements. Specifically, when a light emitting drive current having a given current value is applied, the blue will have the greatest light emitting brightness, followed by green and then by red with sequentially lower light emitting brightness.
Consequently, when there is a color display using RGB color pixels, it is necessary to convert (correct) the current values of the light emitting drive currents applied to the light emitting elements (or the gradation currents written to each of the color pixels) in order to reconcile the brightness of each of the colors.
As shown in
Specifically, as shown in Table 1, when producing a white display, if the maximum brightness gradation values for each of the pixels PIX for R, G, and B (that is, the maximum brightness per unit surface area: cd/m2), are, respectively, LVR, LVG, and LVB, and the current efficiencies (that is, the light emitting brightness per unit current value: cd/A) are, respectively, ηR, ηG, and ηB, then the current values (the current value per unit area: μA/m2) for each pixel at the maximum brightness gradation can be expressed respectively as LVR/ηR, LVG/ηG, and LVB/ηB. Consequently, the current ratios that are set in the current mirror circuits (that is, the ratio of the output current Iout to the input current Iin; Iout:Iin) can be expressed as LVR/ηR:1, LVG/ηG:1, and LVB/ηB:1 for the individual R, G, and B color pixels PIX.
Furthermore, in each of the color pixels PIX for R, G, and B, applied in the present embodiment, the pixel current values at the aforementioned maximum brightness gradations are specified, as shown in Table 2, for example, at, respectively 2.04 μA/m2, 0.89 μA/m2, and 0.71 μA/m2, based on the current efficiencies ηR, ηG, and ηB of the respective color pixels PIX. In this case, the red pixel, which has the largest of the pixel current values (that is, having the smallest current efficiency), is used as a reference, and the current ratios (that is, the ratio of the gradation current Ipix, which is the output current, to the data current Idata, which is the input current) corresponding to each color pixels PIX are set, respectively, to 1:1, 1:2.3, and 1:2.9. Specifically, the transistor size ratios of the transistors Ta3 and Ta4, and of the transistors Tb3 and Tb4, which form the current mirror circuits, for example, are set corresponding to the current ratios. Here, for example, the transistor size is a channel width of each of the transistors in the case where a channel length of each of the transistors is fixed in same size, and the transistor size ratios are ratios of the channel width of each of the transistors.
In this way, the current ratios that are set for the individual current mirror circuits corresponding to the R, G, and B color pixels PIX (the ratio of the gradation current Ipix that is the output current to the data current Idata that is the input current) are set so as to be 1 or less (such that the gradation current Ipix is no more than the data current Idata). Doing so enables the current value of the data current Idata, which is outputted from the current driver 130, to be increased, enabling the D/A converter 134 (shown in
Note that the capacitors CA and CB, provided in the individual current latching/converting circuits 142a and 142b, may be the parasitic capacitances that are formed between the gates and the drains of the respective transistors Ta3 or Ta4 and Tb3 or Tb4. Additionally, each of the transistors Ta1 through Ta5, and Tb1 through Tb5, which constitute the individual current value converting circuit units 141 (the current latching/converting circuit 142a and 142b), may use an n-channel field effect transistor using, for example, and amorphous silicon semiconductor or a polysilicon semiconductor as the channel layer.
Here there is a problem area in that there tends to be a change over time in the element characteristics (the threshold voltage, and the like) of amorphous silicon transistors. However, when a field effect transistor provided with an amorphous silicon semiconductor is used as the current value converting circuit unit 141 (the current latching/converting circuits 142a and 142b) according to the present embodiment, fabricating proximally the pair of transistors Ta3 and Ta4 and the pair of transistors Tb3 and Tb4 that structure the current mirror circuits can cause the degrees of advancement in the change (degradation) of the characteristics of these transistors to be equal to each other. Additionally, because it is possible to control the operating state by a single gate voltage (the voltage of contact NA1 or NB1), it is also possible to perform extreme control of the effects of the change in characteristics on the operation of the current mirror circuits (the current value of the gradation current Ipix relative to the data current Idata) and, further, on the display quality.
That is, in the current control unit 140 (the current value converting circuit unit 141) in the present embodiment, the current mirror circuit and the current driver 130 are connected in either the current latching/converting circuit 142a or 142b based on the switching control signal LC1 or LC2, which are of mutually opposite phases, supplied as current control signals from the system controller 150 (at which time, the current mirror circuit and the data line DL are set to a non-connected state), so that the data current Idata that is supplied from the current driver 130 will be received. At the same time, on the other side, the current mirror circuit and the data line DL are connected (at which time, the current mirror circuit and the current driver 130 are set into a non-connected state), so that the current that flows on the output side of the current mirror circuit is supplied to the specific color pixel PIX through the data line DL as the gradation current Ipix. Note that a specific control operation for the current control unit 140 will be explained in detail in the driving method of the display device, described below.
The system controller 150 supplies, to the scan driver 120, the current driver 130, and the current control unit 140, a scan control signal, a data control signal, and a current control signal, which control the operating status, to thereby perform, with the respective specific timings, the operations of generating and applying to the scan line SL a scan signal Vsel in the scan driver 120, generating the data current Idata in accordance with the display data in the current driver 130, and converting the data current Idata to generate the gradation current Ipix, which is supplied to the data line DL, in the current control unit 140. In this way, the system controller 150 controls the display of the specific image information, based on the video signal, onto the pixel array 110 by writing the display data to the individual color pixels PIX to cause light emitting operations at the appropriate brightness gradations.
The display signal generating circuit 160 extracts the signal component that includes the brightness gradation value from the video signal that is supplied from the outside of the display device 100A, for example, and supplies that signal component to the current driver 130 as the display data for each row in the pixel array 110. If this video signal includes a timing signal component that specifies the display timing of the image data, such as in a television broadcast signal (a component video signal) then the display signal generating circuit 160 has, in addition to the function for extracting the signal component that includes the brightness gradation value, a function for extracting the timing signal component and supplying it to the system controller 150. In this case, as shown in
Next the driving method in the display device described above will be explained in reference to the figures.
Here, a specific description will be given regarding the latching operation and writing operation for display data for color pixels PIX of the odd number (2i−1) rows and of the even number (2i) rows (where “i” is a positive integer fulfilling 1=2i−1=n−1, and 2=2i=n), for the case wherein the pixel array 110 is a pixel array of n rows by m columns (where n is an odd number and m is a multiple of 3), as described above.
Moreover,
The driving control operation in the display device 100A in the present embodiment includes a current latching operation that is performed during a first-half of one horizontal scan period (a current latching operation period) and a current writing operation that is performed during a second-half of one horizontal scan period (a current writing operation period), with two horizontal scan periods wherein two adjacent rows of color pixels PIX are selected sequentially is defined as one unit period. Here the current latching operation is the operation wherein the data current Idata that is in accordance with the brightness gradation value of the display data for one row, supplied from the current driver 130, is received by, and maintained in, one of the pair of current latching/converting circuits 142a and 142b of the current value converting circuit unit 141 that is provided for each column of the current control unit 140. Moreover, the current writing operation is the operation that generates the gradation current Ipix that has a specific current ratio, shown in Table 1 or Table 2 described above, relative to the data current Idata that is received by either the current latching/converting circuit 142a or 142b in the current latching operation described above, and writes this gradation current Ipix to each of the color pixels PIX in the specific row.
Here the aforementioned current latching operation and current writing operation are performed in a synchronized manner between the pair of current latching/converting circuits 142a and 142b that form the current value converting circuit unit 141, and are controlled so as to be repeatedly performed alternatingly.
In other words, during the period wherein the data current Idata that is supplied corresponding to each data line DL from the current driver 130 based on the display data is received and held by one of the current latching/converting circuit sides (for example, the current latching/converting circuit 142a) of the air of current latching/converting circuits 142a and 142b that form one of the current value converting circuit units 141, the gradation current Ipix corresponding to the data current Idata that was received and latched with the timing of the immediately preceding reception is supplied, simultaneously and in parallel, to each data line DL from the current latching/converting circuit on the other side (for example, the current latching/converting circuit 142b). Because of this, as will be described below, an operation is performed wherein the gradation current Ipix is generated substantially continuously based on the display data from the display driver 130 and the current control unit 140, and supplied to the data lines DL for each column.
Specifically, during a first operating period (the first-half of one horizontal scan period, when two horizontal scan periods is defined as a unit period) in the current value converting circuit units 141 that are provided for each column in the current control unit 140, described above, when, as shown in
Additionally, the data current Idata that corresponds to the display data for the color pixels PIX in each column for a specific row (such as row (2i−1)) is supplied from the current driver 130, synchronized with this timing. When this is done, there is electrical shorting between the gate and the drain of the transistor Ta3, which turns ON in the saturation region, so the data current Idata flows in the direction of the low-voltage potential Vee through transistors Ta1 and Ta3 and contact NA3. At this time, the current level of the data current Idata will be converted into a voltage level (the voltage component) across the gate and source of the transistor Ta3, which is stored as an electrical charge in the capacitor CA (the current latching operation).
At this time, the potential at contact NA1 will increase according to the charge that is stored in the capacitor CA, causing the transistor Ta4, which forms the current mirror circuit together with the transistor Ta3, to turn ON, but because the transistor Ta5 is set to the OFF state, no current flows in the transistor Ta4.
In this way, in the current latching operation, the data current Idata that is outputted for each column depending on the brightness gradation level that is included in the display data from the current driver 130 flows to the current latching/converting circuit 142a, equipped on one side in each of the current value converting circuit units 141, so that the data current Idata (2i−1) for one row (for example, row (2i−1)) will be received by, and latched in, the current control unit 140.
Next, during a second operating period (the second-half of one horizontal scan period, when two horizontal scan periods is defined as a unit period), when, as shown in
At this time, a potential (high voltage) will be maintained at the contact NA, given the current latching operation described above (
Additionally, synchronized with this timing, a scan signal Vsel of the select level (HIGH level) will be applied to the scan line SL of the row to which the display data is being written by the scan driver 120, to set into the selected state the other pixels PIX of the applicable row. Doing so causes the gradation current Ipix, described above, to flow so as to be extracted in the direction of the current control unit 140 through each data line DL so that, as described below, a charge (voltage component) that is in accordance with the gradation current Ipix will be stored in the pixel driving circuit that is provided for the individual color pixels PIX (current writing operation).
Here, in the current writing operation to the color pixels PIX by the current control units 140, the current value for the data current Idata in accordance with the brightness gradation value of the display data for the applicable color pixel PIX will be converted (corrected) into the current value in accordance with the current efficiency of the color pixel PIX, according to the current ratio set in the current mirror circuit (the transistors Ta3 and Ta4), set in the current latching/converting circuit 142a, to flow to each color pixel PIX as the gradation current Ipix.
In this way, in the current writing operation, the gradation current Ipix is extracted from the color pixels PIX of the row that is set to the selected state (for example, row (2i−1)) by the current latching/converting circuit 142a, provided on one side of each of the current value converting circuit units 141, to which the data current Idata is supplied by the current latching operation described above. Because of this, one row worth of gradation current Ipix (2i−1) is written to, and latched in, the individual color pixels PIX (the red (R) color pixel in the example in
Furthermore, in the current latching/converting circuit 142a that is provided in the other side of this type of current value converting circuit unit 141, during the period of the current writing operation wherein the specific gradation currents Ipix are extracted through the data line from the color pixels PIX that are set to the selected state, the switching control signal LC1 that is supplied as a current control signal from the system controller 150 is set to the HIGH level (H) and the switching control signal LC2 is set to the LOW level (L), as shown in
Additionally, the data current Idata that corresponds to the display data for the color pixels PIX in each column for the next row (such as row 2i) is supplied from the current driver 130, synchronized with this timing. As a result, as with the case of the current latching operation in the one current latching/converting circuit 142a, described above, the data current Idata (2i) flows in the direction of the low-voltage potential Vee through transistors Tb1 and Tb3, and the contact NB3, so that a voltage component in accordance with the applicable data current Idata will be stored in the capacitor CB that is connected across the gate and source of the transistor Tb3 (current latching operation).
Next, during a third operating period (the first-half of one horizontal scan period, when two horizontal scan periods is defined as a unit period; the same as for the first operating period described above), as shown in
Because of this, the gradation current Ipix, which has a current value that is based on the charge that was stored in the capacitor CA by the current latching operation (
In this way, during the period wherein the current writing operation that supplies the gradation current Ipix to the color pixel PIX in the odd (2i−1) row is performed in the one current latching/converting circuit 142a of the current value converting circuit unit 141, the current latching operation, which receives and latches the data current Idata in accordance with the color pixel PIX for the even (2i) row, is performed simultaneously in the other current latching/converting circuit 142b. Moreover, during the period wherein the current writing operation that supplies the gradation current Ipix to the color pixel PIX in the even (2i) row is performed in the other current latching/converting circuit 142b, the current latching operation, which receives and latches the data current Idata in accordance with the color pixel PIX for the odd (2i+1) row, is performed simultaneously in the first current latching/converting circuit 142a.
The display device according to the present embodiment comprises a pixel array wherein the individual RGB pixels are arranged in a delta arrangement having different-color interconnections wherein color pixels having two different colors are connected regularly to each data line disposed in the column direction, and comprises a current driver for generating a data current having a current value in accordance with the brightness gradation value included in the display data for each color pixel in the individual column, and a current control unit for converting the data current that is generated for each pixel in the individual column into a current value in accordance with a current ratio for each color pixel, and outputting the current value, as a gradation current, through the data line DL for the individual column. Because of this, it is possible to convert the current values for the data currents that are outputted from the current driver for pixels of different colors that are connected to the data line, doing so in accordance with the current efficiencies (light emitting efficiencies) of each color pixel. Consequently, it is possible to use, without modification, existing current drivers (data drivers) that generate and output data currents having current values that are in accordance with only the brightness gradation values that are included in the display data.
Furthermore, a current value converting circuit unit comprising a set (a pair) of current mirror circuits (current latching/converting circuits) formed in advance so as to have a current ratio in accordance with the current efficiencies of the color pixels of different colors that are connected to the individual data line is used as a structure for converting data currents that are in accordance with only the brightness gradation values of the display data that are outputted from the current driver, as described above, into gradation currents that have current values that are in accordance with the current efficiencies of the color pixels. Additionally, these enable the use of a simple control method for repeatedly alternating a current latching operation and a current writing operation. Because of this, it is possible to maintain a temporal margin in the switching control timing of the output current in the writing operation of the gradation signal to the color pixels in each row, enabling the display of desired image data, such as video images, with excellent image quality.
As a result, the provision of a plurality of current drivers (data drivers) corresponding to the individual color pixels is not necessary in a display device that is provided with a pixel array wherein the color pixels are arranged in a delta arrangement with different-color interconnections. Moreover, this enables gradation currents to be generated and outputted to data lines for the individual color pixels using a simple control method. Because of this, it is possible not only to prevent increased complexity of the display device, the driver structure, and the control method, but also to prevent increases in product costs.
Note that in the current control unit 140 according to the resent invention, a case was described wherein, in order to accommodate the circuit structures of the pixel driving circuits provided for the pixels PIX (shown in
Note that the majority of the well-known current drivers (data drivers) that are commonly distributed in the market today, and that can be obtained easily, have structures that output the current (the data current Idata) with a positive polarity. Because of this, the use of the current control unit 140 and the color pixels PIX (pixel driving circuits) as described above enables the achievement, using well-known current drivers, of a display driving device wherein the gradation current flows in the draw-down direction in the current control 140 direction.
Moreover, in the display device according to the present embodiment, as shown in
Moreover, the pixel array comprised pixels of the three colors of red, green, and blue, wherein color pixels of two different colors were connected to a single data line. However, the present invention is not limited thereto, but instead the pixel array may comprise color pixels of more than three colors, such as color pixels of four colors or more. Moreover, there may be color pixels of more than two colors, for example color pixels of three colors or more, connected regularly to a single data line.
Next a specific circuit example for a display pixel that can be used in the display device set forth in the embodiment described above will be explained in reference to the figures.
As shown in
The pixel driving circuit DC, as shown in, for example,
The organic electroluminescent element OLED is connected with the anode terminal thereof connected to the contact N12 of the aforementioned pixel driving circuit DC, and the cathode terminal thereof is connected to Vss (for example, the ground potential).
Here n-channel thin film transistors (field effect transistors) can be used for any of the transistors Tr11 through Tr13. Additionally, the capacitor Cs is the parasitic capacitance that is formed between the gate and the source of the transistor Tr13, or has a supplemental capacitance that is added between the gate and the source.
(Driving Control Operation for Display Pixel)
The driving control operation for the light emitting element (the organic electroluminescent element OLED) in the pixel driving circuit DC that has a circuit structure such as described above has, as shown in, for example,
Firstly, in the current writing operation (the current writing operation period Tse), as has been explained in the operation of the current control unit 140, described above (in reference to
Doing so not only applies a LOW level power supply voltage Vsc to the contact N11 (one end of the capacitor Cs and the gate terminal of the transistor Tr13) by turning ON the transistors Tr11 and Tr12 that form the pixel driving circuit DC for the color pixels PIX, but also performs the operation of drawing (extracting) the gradation current Ipix in the direction of the current control unit 140 through the data line DL from the color pixel FIX (the pixel driving circuit DC). Doing this causes a voltage level that is even lower than the potential of the LOW level power supply voltage Vsc to be applied to the contact N12 (the other side of the capacitor Cs and the source terminal of the transistor Tr13).
The potential difference that is produced between the contacts N11 and N12 (across the gate and the source of the transistor Tr13 and across the ends of the capacitor Cs) turns the transistor Tr130N, so that, as shown in
At this time, an electric charge in accordance with the potential difference that is produced between the contacts N11 and N12 (across the gate and source of the transistor Tr13) is stored in the capacitor Cs, and is maintained (charged) as a voltage component. Additionally, a LOW level power supply voltage Vsc, having a voltage level that is lower than the constant voltage Vss (for example, the ground potential) that is applied to the cathode terminal of the organic electroluminescent element OLED, is applied to the power supply line VL, and the writing current Iwrt is controlled so as to flow to (or be drawn down from) the current control unit 140 through the data line DL, so the voltage that is applied to the anode terminal (the contact N12) of the organic electroluminescent element OLED will be lower than the potential of the cathode terminal (the constant voltage Vss) Because this results in the application of a reverse bias voltage to the organic electroluminescent element OLED, the light emission driving current does not flow to the organic electroluminescent element OLED, so there is no light emitting operation.
Following this, in the light emitting operation (light emitting operation period Tnse) after the conclusion of the current writing operation, not only are the color pixels PIX of the applicable row set into a non-selected state through the application of the LOW level (L) scan signal Vsel to the scan line SL of each row by the scan driver 120, as shown in
Because of this, the transistors Tr11 and Tr12 are turned OFF, not only interrupting the application of the power supply voltage Vsc to the contact N11, but also interrupting the application of the voltage level accompanying the draw-down operation of the gradation power supply Ipix to the contact N12. Because of this, the capacitor Cs will maintain the stored charge in the current writing operation described above.
By the capacitor Cs maintaining the charge (the charged voltage) that is stored at the time of the current writing operation, the potential difference between the contacts N11 and N12 (between the gate and source of the transistor Tr13) will be maintained, maintaining in the conductive state (the ON state) so as to enable the transistor Tr13 to pass a current at a current value in accordance with the writing current Iwrt. Furthermore, the application, to the power supply line VL, of a power supply voltage Vsc that has a higher voltage level than the constant voltage Vss (for example, the ground potential), which is applied to the cathode terminal of the organic electroluminescent element OLED, causes the voltage that is applied to the anode terminal (contact N12) of the organic electroluminescent element OLED to be higher than the voltage of the terminal (the constant voltage Vss).
Furthermore, the application, to the power supply line VL, of a power supply voltage Vsc that has a higher voltage level than the constant voltage Vss (for example, the ground potential), which is applied to the cathode terminal of the organic electroluminescent element OLED, causes the voltage that is applied to the anode terminal (contact N12) of the organic electroluminescent element OLED to be higher than the voltage of the cathode terminal (the constant voltage Vss). Here the potential difference (charged voltage) based on the charge that is stored by the capacitor Cs corresponds to the potential difference when the transistor Tr13 passes a writing current Iwrt in accordance with the gradation current Ipix. Because of this, the light emitting driving current Iem that flows in the organic electroluminescent element OLED will have a current value that is equal to that of the writing current Iwrt, described above (which is essentially equal to the gradation current Ipix).
Because of this, during the light emitting operation period Tnse, the voltage component in accordance with the gradation current Ipix that was written during the current writing operation period Tse will be maintained, so the transistor Tr13 will be turned ON in a saturation state based thereon, so the light emitting driving current Iem will be supplied continuously. Because of this, the operation wherein the organic electroluminescent element OLED emits light at the brightness gradation in accordance with the current efficiency of each color pixel PIX and in accordance with the brightness gradation of the display data will be continuous.
Additionally, performing this type of series of driving control operations sequentially and repetitively for each row for all of the color pixels PIX that are arranged in the pixel array 110 writes one screen worth of display data with light emissions at specific brightness gradations, displaying the desired image information.
Here, in the pixel driving circuit DC according to the present embodiment, there are no particular limitations appertaining to the transistors Tr11 through Tr13; however, a structure using thin film transistors (field effect transistors) having identical channel polarity for all of the transistors Tr11 through Tr13 may be used. Consequently, an n-channel field effect transistor with an amorphous silicon semiconductor or a polysilicon semiconductor as the channel layer can be used in the same manner as for the current control unit 140 (the current value converting circuit unit 141 and the current latching/converting circuits 142a and 142b), discussed above.
Doing so enables the integrated fabrication of both the pixel array 110 wherein the color pixels PIX are arranged in a delta arrangement, provided with the pixel driving circuit DC according to the present embodiment, along with the current driving unit 140, on the same panel substrate (an insulating substrate) using the same manufacturing processes. In particular, in the case wherein the pixel array 110 and the current control unit 140 are structured using n-channel field effect transistors using amorphous silicon semiconductor layers, manufacturing technologies for amorphous silicon, which are already well established, can be used, making it possible to manufacture field effect transistors with stabilized operating characteristics relatively inexpensively, thus making it possible to achieve easily display devices with superior display quality.
Note that when the color pixel PIX (the pixel driving circuit DC) as described above is used, it is necessary to perform control so as to switch the voltage level of the power supply voltage Vsc that is applied to the power supply line VL that is provided in each row of the pixel array 110 during the current writing operation period Tse and the light emitting operation period Tnse, as shown in
Additionally, in the embodiment described above, the pixel array 110 had a structure wherein color pixels PIX of two different colors were connected alternatingly by rows to a single data line DL, and each power supply value converting circuit unit 141 of the current control unit 140 had a set of power supply converting circuits that provided a current mirror circuit for each data line DL. However, the present invention is not limited thereto, and instead there may be a power supply converting circuit for each color, corresponding to a plurality of colors, for each data line DL, where a plurality of color pixels PIX that is greater than 2 colors is connected to a single data line DL.
Additionally, while the scan driver 120 applied the scan signal Vsel sequentially to the individual scan lines SL of the pixel array 110, to set the color pixels PIX of each row sequentially into the selected state, the present invention is not limited thereto, but rather each row of color pixels PIX may be put into the selected state in any given order.
Additionally, in the color pixels PIX according to the embodiment described above, a circuit structure was illustrated corresponding to a current specifying method of a type wherein the gradation current Ipix was extracted through the data line DL from the color pixel PIX (the pixel driving circuit DC) through the provision of three transistors as the pixel driving circuit DC and generating a gradation current Ipix, with a negative polarity, by the current control unit 140. However, the present invention is not limited thereto, but may have a different circuit structure insofar as there is a pixel driving circuit that uses, at least, a current specifying method. Furthermore, there may be a circuit structure corresponding to the state wherein the gradation current Ipix is generated with a positive polarity using the current control unit 140, and the gradation current Ipix is pushed into the color pixels PIX (the pixel driving circuit DC) through the data line DL.
Furthermore, in the embodiment described above, a structure was illustrated using an organic electroluminescent element OLED as the light emitting element for structuring the color elements PIX. However, the display device according to the present invention is not limited thereto, but rather, for example, other current-controlled light emitting elements, such as light emitting diodes, may be used suitably.
A second embodiment of a display device according to the present invention will be described next in reference to the figures.
In the first embodiment, described above, it was explained that a set (a pair) of current latching/converting circuits equipped with current mirror circuits each having different current ratios is connected in parallel to the data line of an individual column, and operations are repeated alternatingly for each row wherein as the data current output from the current driver is received and maintained in one current latching/converting circuit, simultaneously a gradation current is applied to the color pixel in accordance with the data current that was received and maintained during the previous operating period by the other current latching/converting circuit.
In the second embodiment, there is a distinctive feature wherein, in a set of current receiving/converting circuits that is connected to the data line in parallel, an operation wherein a gradation current in accordance with the data current is supplied to the color pixel at the same time as the data current is received by one of the current receiving/converting circuits is repetitively performed alternating with another current receiving/converting circuit.
Here explanations are omitted or abbreviated for the structures that are identical to those in the first embodiment, described above (the display device illustrated in
The current control unit 140, as illustrated in
Additionally, the current mirror circuits (transistors Ta3 and Ta4 and transistors Tb3 and Tb4) that are provided in each of the current receiving/converting circuits 142c and 142d are set so that the ratio of the gradation currents Ipix that flows through the transistor Ta4 or Tb4 relative to the data current Idata that flows on the transistor Ta3 or transistor Tb3 side (the current ratios) are in accordance with the current efficiency of the color pixels PIX to which the current writing operation is performed, as was the case in the first embodiment (and, for example, Table 1 and Table 2) described above.
Moreover,
The driving control operation in the display device according to the present embodiment uses one horizontal scan period as a unit period, and the current writing operation is performed simultaneously with the current receiving operation during the one horizontal scan period. The current receiving operation is the operation wherein the data current Idata that is in accordance with the brightness gradation value of the display data for one row, supplied from the current driver 130, is received by one of the pair of current receiving/converting circuits 142c and 142d of the current value converting circuit unit 141 that is provided for each column of the current control unit 140. Moreover, the current writing operation is the operation that generates the gradation currents Ipix that have specific current ratios, shown in Table 1 or Table 2, described above, relative to the data currents Idata that are received, and writes these gradation currents Ipix to each of the color pixels PIX in the specific row.
That is, first, during a first operating period, as shown in
Additionally, the data current Idata (2i−1) that corresponds to the display data for the color pixels PIX in each column for a specific row (for example, row (2i−1)) is supplied from the current driver 130, synchronized with this timing, turning the transistor Ta3 ON in the saturation domain. The data current Idata (2i−1) flows in the direction of the low-voltage potential Vee through transistors Ta1 and Ta3, and contact NA3, and the current level of the data current Idata (2i−1) is converted into a voltage level (a voltage component) across the gate and source of the transistor Ta3, producing a specific potential at contact NA1 (current receiving operation).
At this time, the transistor Ta4, which forms the current mirror together with the transistor Ta3, is turned ON by the voltage that appears at the contact NA1. Because of this, the gradation current Ipix (2i−1), which has a current value in accordance with the current efficiency of the color pixel PIX in the applicable row, based on the voltage at the contact NA1, flows so as to be drawn in the direction of the low-voltage potential Vee from the data line DL side through the transistors Ta5 and Ta4.
Additionally, synchronized with this timing, a scan signal Vsel of the select level (HIGH level) will be applied to the scan line SL of the row to which the display data is being written by the scan driver 120 (for example, row (2i−1), to set into the selected state the other pixels PIX of the applicable row. Doing so causes the gradation current Ipix (2i−1), described above, to flow so as to be extracted in the direction of the current control unit 140 through each data line DL so that a charge (voltage component) that is in accordance with the gradation current Ipix (2i−1) will be maintained in the pixel driving circuit DC of the individual color pixels PIX (the red (R) color pixel in
Note that during this first operating period, the transistors Tb1 and Tb5 of the current receiving/transforming circuit 142d are set to the OFF state. Because of this there is no current flowing on the 142d side, so neither the data current receiving operation nor the gradation current writing operation is performed on the 142d side.
Next, during a second operating period, as shown in
Additionally, the data current Idata (2i) that corresponds to the display data for the color pixels PIX in each column for the next row (such as row (2i)) is supplied from the current driver 130, synchronized with this timing, turning the transistor Tb3 ON in the saturation domain. The data current Idata (2i) flows in the direction of the low-voltage potential Vee through transistors Tb1 and Tb3, and contact NB3, and the current level of the data current Idata (2i) is converted into a voltage level (a voltage component) across the gate and source of the transistor Tb3, producing a specific potential at contact NB1 (current receiving operation).
At this time, the transistor Tb4, which forms the current mirror together with the transistor Tb3, is turned ON by the voltage that appears at the contact NB1. Because of this, the gradation current Ipix (2i), which has a current value in accordance with the current efficiency of the color pixel PIX in the applicable row, based on the voltage at the contact NB1, flows so as to be drawn in the direction of the low-voltage potential Vee from the data line DL side through the transistors Tb5 and Tb4.
Additionally, the color pixels PIX of the row to which the display data (such as row 2i) is to be written are set to the selected state, synchronized with this timing. Doing so causes the gradation current Ipix (2i), described above, to flow so as to be extracted in the direction of the current control unit 140 through each data line DL so that a charge (voltage component) that is in accordance with the gradation current Ipix (2i) will be maintained in the pixel driving circuit DC of the individual color pixels PIX (the green (G) color pixel in
Note that during this second operating period, the transistors Ta1 and Ta5 of the current receiving/transforming circuit 142c are set to the OFF state. Because of this there is no current flowing on the 142c side, so neither the data current receiving operation nor the gradation current writing operation is performed on the 142c side.
In this way, control in the present embodiment is such that an operation wherein a current receiving operation and a current writing operation are performed simultaneously by only one of the current receiving/converting circuits, of the set of current receiving/converting circuits 142c and 142d that is provided in the current value converting circuit unit 141, is repeated alternatingly by the set of current receiving/converting circuits 142c and 142d.
Given the present embodiment, as the data currents that are generated for each color pixel based on the brightness gradation values that are included in the display data are received they are simultaneously converted into current values in accordance with the current efficiencies of the individual color pixels to output the gradation currents through the data lines DL of the individual columns. Because of this, there is no need, as there was in the first embodiment, described above, to perform the data current receiving operation (current latching operation) for the specific color pixels in a separate operating period from the gradation current outputting operation (gradation writing operation), nor is there that need to maintain (latch) the voltage component in accordance with the received data current. Because of this, it is possible to start the display operations for the desired image data immediately, using a simple circuit structure and driving method.
A third embodiment of a display device according to the present invention will be described next in reference to the figures.
Here the structures that are similar to those in the first embodiment, described above, are assigned similar or identical codes, and explanations thereof are abbreviated or omitted.
The display device 100B according to the present embodiment, as illustrated in
The current reset circuit unit 170, as shown in
Here a p-channel thin film transistor is used as the transistor Tc1 and an n-channel thin film transistor is used as the transistor Tc2. Additionally, a reset control signal RSc, which is supplied as a current control signal from the system controller 150, is applied in common to the control terminals (gates) of the transistor Tc1 and Tc2. Note that field effect transistors having, for example, a polysilicon semiconductor as the channel layer, may be used for the transistors Tc1 and Tc2. Consequently, the current reset circuit unit 170 according to the present embodiment may be fabricated integrally with the current driver 130.
In the current reset circuit unit 170 (the reset circuits 171) according to the present embodiment, one of the transistors Tc1 or Tc2 is turned ON, and the other is turned OFF, based on a reset control signal RSc that is supplied as a reset control signal from the system controller 150. As a result, a current passing operation and the reset operation are performed selectively. Here the “current passing operation” is the operation that passes, to the current control unit 140 for each the data current Idata based on the brightness gradation value for one row of display data, supplied from the current driver. Moreover, the reset operation is an operation (reset operation) for resetting (initializing), by applying a specific reset voltage (the low-voltage potential Vee), to the current control unit 140 for each individual row, to discharge the residual charge to the current value converting circuit unit 141 (the current latching/converting circuits 142a and 142b).
Next the driving method in a display device wherein the aforementioned reset circuit unit is provided will be explained in reference to the figures.
Here a driving control operation (reset operation) that is unique to this embodiment will be explained in detail; see the first embodiment (
In the driving control operation in the display device 100B according to the present embodiment, control is such that the reset operation will be performed with timing that is in advance of the current latching operation, as described above, in each of the one horizontal scan periods in the driving control operation according to the first embodiment, illustrated in
Specifically, first, during a first operating period (the first-half one horizontal scan period, where two horizontal scan periods is defined as a unit period), as shown in
As a result, the reset circuit 171 and the current mirror circuit (transistors Ta3 and Ta4, and contact NA1) of the current latching/converting circuit 142a are connected electrically through the transistors Ta1 and Ta2, and the data line DL and the current latching/converting circuit 142a are disconnected from each other electrically by the transistor Ta5. Additionally, when in this state, the reset circuit 171 and the current mirror circuit (transistors Tb3 and Tb4, and contact NB1) of the current latching/converting circuit 142b are disconnected electrically by the transistors Tb1 and Tb2, and the data line DL and the current latching/converting circuit 142b are connected electrically through the transistor Ta5.
Simultaneously with this timing, the reset control signal RSc that is supplied from the system controller 150 is set to the HIGH level (H), turning OFF transistor Tc1 and turning ON transistor Tc2 of the reset circuits 171 that are provided for each current reset circuit unit 170. As a result, the specific low-voltage potential Vee is applied to the contact NA1 through the transistor Tc2 of the reset circuit 171, the input terminal IN of the current value converting circuit unit 141, and transistors Ta1 and Ta2 of the current latching/converting circuit 142a, to discharge the stored charge remaining in the capacitor CA (the reset operation).
Following this, the reset control signal RSc that is supplied from the system controller 150 is set to the LOW level (L), turning ON transistor Tc1 and turning. OFF transistor Tc2 of the reset circuits 171. Simultaneously with this timing, the data current Idata (2i−1) that corresponds to the brightness gradation values of the display data for the color pixels PIX in each column for a specific row (for example, row (2i−1)) is supplied from the current driver 130, synchronized with this timing, and is applied the input terminal IN of the current value converting circuit unit 141 through the transistor Tc1 of the reset circuit 171. Consequently, there is electrical shorting between the gate and the drain of transistor Ta of the current latching/converting circuit 142a, which turns ON in the saturation region, so the data current Idata (2i−1) flows in the direction of the low-voltage potential Vee through transistors Ta1 and Ta3 and contact NA3. Because of this, the current level of the data current Idata (2i−1) will be converted into a voltage level (the voltage component) across the gate and source of the transistor Ta3, and is stored as an electrical charge in the capacitor CA (the current latching operation).
Next, during a second operating period (the second-half one horizontal scan period when two horizontal scan periods is defined as a unit period), the switching control signal LC1 is set to the HIGH level (H) and the switching control signal LC2 is set to the LOW level (L) As a result, transistors Ta1 and Ta2 are turned OFF and transistor Ta5 is turned ON in the current latching/converting circuit 142a, and transistors Tb1 and Tb2 are turned ON and transistor Tb5 is turned OFF in the current latching/converting circuit 142b.
At this time, in the current latching/converting circuit 142a, a voltage (high-voltage) is maintained in the contact NA1 based on the charge that is stored in the capacitor CA by the current latching operation, described above. Because of this, the transistor Ta4 is turned ON, inducing a gradation current Ipix (2i−1), having a current value based on the charge stored in the capacitor CA (that is, based on the data current Idata), towards the low-voltage potential vee through the transistors Ta5 and Ta4 from the data line side.
Additionally, synchronized with this timing, a scan signal Vsel of the select level (HIGH level) will be applied to the scan line SL of the row to which the display data is being written by the scan driver 120 (for example, row (2i−1)), to set into the selected state the other pixels PIX of the applicable row. Consequently, a charge (voltage component), depending on the gradation current Ipix (2i−1), is maintained in the pixel driving circuit DC that is provided for each pixel PIX.
On the other hand, in the current latching/converting circuit 142b, the reset circuit 171 and the current mirror circuit (transistors Tb3 and Tb4, and contact NB1) are connected electrically through the transistors Tb1 and Tb2, and the data line DL is disconnected electrically by the transistor Tb5.
Simultaneously with this timing, the reset control signal RSc that is supplied from the system controller 150 is set to the HIGH level (H). As a result, the transistor Tc1 is turned OFF and the transistor Tc2 is turned ON in the reset circuit 171, and the specific low-voltage potential Vee is applied to the contact NB1 through transistors TB1 and TB2 of the current latching/converting circuit 142b, to discharge the stored charge remaining in the capacitor CA (the reset operation).
Following this, the reset control signal RSc that is supplied from the system controller 150 is set to the LOW level (L), turning ON transistor Tc1 and turning OFF transistor Tc2 of the reset circuit 171. Simultaneously with this timing, the data current Idata (2i) that corresponds to the brightness gradation values of the display data for the color pixels PIX in each column for the next row (for example, row 2i) is supplied from the current driver 130 and is applied to the input terminal IN of the current value converting circuit unit 141 through the transistor Tc1 of the reset circuit 171. Consequently, there is electrical shorting between the gate and the drain of transistor Tb3 of the current latching/converting circuit 142b, which turns ON in the saturation region, so the data current Idata (2i) flows in the direction of the low-voltage potential Vee through transistors Tb1 and Tb3 and contact NB3. Because of this, the current level of the data current Idata (2i) will be converted into a voltage level (the voltage component) across the gate and source of the transistor Tb3, and is stored as an electrical charge in the capacitor CB (the current latching operation).
Following this, by repeatedly performing this type of series of driving control operations, not only is it possible to discharge the charge that remains in the current value converting circuit unit 141 (the current latching/converting circuits 142a and 142b) that receives the data current Idata in accordance with the display data to perform initialization in advance, but also to continuously receive the data current Idata for each row from the current driver 130 while writing the gradation current Ipix in accordance with the current efficiency of the applicable color pixel PIX, for the color pixels PIX of each row.
Consequently, in the present embodiment the charge that is remaining in the current mirror circuit of the current latching/converting circuit can be discharged through the current latching operation and the current writing operation in the current value converting circuit unit (the current latching/converting circuit) for each column. Because of this, it is possible to prevent a phenomenon wherein the color pixel (light emitting element) cannot perform the light emitting operation at a brightness gradation that is in accordance with the display data because the gradation current changes from the actual current value that is in accordance with the display data due to charge that is remaining in the current mirror circuit of the current latching/converting circuit. Consequently, it is possible to achieve a display device having a desirable display quality by preventing the occurrence of, for example, non-uniform display, brightness deviations, and the like.
Note that in the present embodiment, the explanation is for a structure, as shown in
In this case, as the method for driving the display device, control is performed, in the timing chart illustrated in
Here explanations are omitted or abbreviated for structures that are identical to those of
In the current reset circuit unit 170 (the reset circuit 171) illustrated in
The reset circuit 171 according to the present embodiment, as shown in
Here the enable signal ENB that is applied to the transistor Tc3, and the reset control signal RSc that is applied to the transistor Tc4 have a mutually inverted phase relationship. Additionally, the transistors Tc3 and Tc4 use n-channel thin film transistors in both, so control is such that when one of the transistors Tc3 or Tc4 is in the ON state, the other is in the OFF state.
Note that field effect transistors having, for example, an amorphous silicon semiconductor as the channel layer, may be used for the transistors Tc3 and Tc4. Doing so enables the integrated fabrication of the current reset circuit 170 on the same panel substrate (an insulating substrate) as the current control unit 140 and the pixel array 110 (pixel driving circuit DC) and using the same manufacturing processes.
Here a driving control operation (reset operation) that is unique to the present embodiment will be explained in detail, and explanations of the other operations (the current latching operation and the current writing operation) will be abbreviated or omitted, referencing
In the present embodiment, as with the driving control operation illustrated in
That is, as shown in
Next, the reset control signal RSc that is supplied from the system controller 150 is set to the LOW level (L) and the enable signal ENB is set to the HIGH level (H), turning ON transistor Tc3 and turning OFF transistor Tc4 of the reset circuit 171. Simultaneously with this timing, the data current Idata (2i) that corresponds to the brightness gradation values of the display data for the color pixels PIX in each column for a specific row (for example, row 2i) is supplied from the current driver 130, and is applied to the input terminal IN of the current value converting circuit unit 141 through the transistor Tc3 of the reset circuit 171. As a result, the data current Idata (2i) flows in the direction of the low-voltage potential Vee through transistors Ta1 and Ta3 of the current latching/converting circuit 142a and through contact NA3, and the current level of the data current Idata (2i) is converted into a voltage level (a voltage component) across the gate and source of the transistor Ta3, and is stored as electric charge in the capacitor CA (current latching operation).
In the present embodiment, the charge that is remaining in the applicable current value converting circuit unit (current latching/converting circuit) can be discharged to perform initialization prior to the current latching operation in the current value converting circuit unit for each column. Because of this, it is possible to generate, and to supply to each color pixel, a gradation current that has a current value that is appropriate to the display data and to the current efficiency, and possible to achieve a desirable display quality through controlling the occurrence of, for example, non-uniform displays and brightness deviations, and the like.
Note that the voltage component corresponding to the data current Idata (2i) that is received and stored in the current latching/converting circuit 142a by the current latch operation is, in the same manner as in the first and third embodiments, described above, converted into gradation currents Ipix (2i) that have current values that are in accordance with the current efficiencies of the individual color elements PIX in the second row, and are supplied through the data lines DL for the individual columns during the next operating period.
Moreover, during the operating period wherein the aforementioned reset operation and current writing operation are performed, based on the charge (voltage component) that is stored in the capacitor CB by the current latching operation in the previous operating period in the current latching/converting circuit 142b, that is, the current latching operation that receives and latches the data current Idata (2i−1) corresponding to the display data for the color pixels PIX of row (2i−1), the transistor Tb4 turns ON to cause a gradation current Ipix (2i−1) to be drawn towards the low-voltage potential Vee through the transistors Tb5 and Tb4 from the data lines DL. As a result, by the scan driver 120 setting into the selected state the color pixels PIX of row (2i−1), synchronized with this timing, charges (voltage components) are maintained in accordance with the aforementioned gradation currents Ipix (2i−1) on the pixel driver circuits DC wherein the individual color pixels PIX are provided.
A forth embodiment of a display device according to the present invention will be described next in reference to the figures.
Here the structures that are similar to those in the first embodiment or third embodiment, described above, are assigned similar or identical codes, and explanations thereof are abbreviated or omitted.
The display device 100C according to the present embodiment, as illustrated in
The pixel reset circuit unit 180, as shown in
Here a thin film transistor (field effect transistor) that uses, for example, an n-channel amorphous silicon semiconductor can be used for the transistor Td1. Doing so enables the integrated fabrication of the pixel reset circuit 180 according to the present embodiment on the same panel substrate (an insulating substrate) as the pixel array 110 (pixel driving circuit DC) and the current control unit 140 using the same manufacturing processes.
In the pixel reset circuit unit 180 (reset circuit 181) according to the present embodiment, the transistor Td1 turns ON based on the reset control signal RSp that is applied as a reset control signal from the system controller 150 to apply a specific reset voltage (the ground potential GND) to the data line DL of each of the columns provided in the pixel array 110. As a result, the charge that is remaining in the color pixels PIX in the data line and the rows that are set to the selected state will be discharged, performing a reset (initialization) operation (pixel reset operation).
Next the driving method in a display device wherein the aforementioned reset circuit unit is provided will be explained in reference to the figures.
Here a driving control operation (pixel reset operation, reset operation) that is unique to this embodiment will be explained in detail; see the first embodiment or third embodiment (
In the driving control operation in the display device 100C according to the present embodiment, control is such that the pixel reset operation is performed within each one horizontal scan period. The pixel reset operation is an operation that resets the individual color pixels PIX of the row that is the subject of the writing operation for the display data (gradation current Ipix), through the data line DL for each column, by discharging the residual charge through applying the ground voltage GND all at once, with a timing that is prior to the reset operation in the driving control operation according to the third embodiment illustrated in
Specifically, first, during a first operating period (the first-half one horizontal scan period, where two horizontal scan periods is defined as a unit period), as shown in
Simultaneously with this timing, the reset control signal RSp that is supplied from the system controller 150 to the pixel reset circuit unit 180 is set to the HIGH level (H), and the scan signal Vsel of the selected level (the HIGH level) is applied to the scan lines of, for example, row (2i−1) from the scan driver 120.
As a result, the transistor Td1 of the reset circuit 181 that is provided for each row in the pixel reset circuit unit 180 is turned ON, and the color pixels PIX of row (2i−1) are set into the selected state. As a result, the ground voltage GND is applied to each of the color pixels PIX of the row (2i−1) through the transistors Td1 in the data lines DL, discharging the residual charge that is stored in the capacitors Cs (shown in
Following this, the reset control signal RSp that is supplied from the system controller 150 to the pixel reset circuit unit 180 is set to the LOW level (L), turning ON transistor Td1 of the reset circuits 181 to disconnect the application of the ground voltage GND to the data lines DL. Simultaneously with this timing, the reset control signal RSc that is supplied from the system controller 150 to the current reset circuit unit 170 is set to the HIGH level (H), turning OFF the transistor Tc1 and turning ON the transistor Tc2 of the reset circuit unit 171 to apply the specific low-voltage potential Vee to the current control unit 140.
Simultaneously with this timing, the switching control signal LC1 that is supplied from the system controller 150 to the current control unit 140 is set to the HIGH level (H), turning ON the transistors Tb1 and Tb2 and turning OFF the transistor Tb5 of the current latching/converting circuit 142b. As a result, the low-voltage potential Vee that is applied through the reset circuit unit 171 (the transistor Tc2) is applied to the contact NB1 through the transistors Tb1 and Tb2 of the current latching/converting circuit 142b to discharge the stored charge remaining in the capacitor CB (the reset operation).
Following this, the reset control signal RSc that is supplied from the system controller 150 to the current reset circuit unit 170 is set to the LOW level (L), turning ON transistors Tc1 and turning OFF transistors Tc2 of the reset circuits 171. The data current Idata (2i) that corresponds to the brightness gradation values of the display data for the color pixels PIX in each column for row 2i is supplied from the current driver 130, synchronized with this timing, and is applied to the current value converting circuit unit 141 through the transistor Tc1 of the reset circuit 171. As a result, the transistor Tc3 of the current latching/converting circuit 142b turns ON in the saturation region, so the data current Idata (2i) flows in the direction of the low-voltage potential vee through transistors Tb1 and Tb3 and contact NB3. Because of this, the current level of the data current Idata (2i) will be converted into a voltage level (the voltage component) across the gate and source of the transistor Tb3, which is stored as an electrical charge in the capacitor CB (the current latching operation).
Note that after the pixel reset operation for the color pixels PIX in row (2i−1), described above, the operation for writing, to the applicable color pixels PIX, the gradation currents Ipix (2i−1) that correspond to the data currents Idata (2i−1), corresponding to the color pixels PIX for the row (2i−1), which were received and maintained, in the previous operating period, in the current latching/converting circuit 142a, as shown in
Following this, in the second operating period (the second half one horizontal scan period, where two horizontal scan periods is defined as a unit period), the switching control signals LC1 and LC2 are set to the LOW level (L) to electrically disconnect the data lines DL from the current value converting circuit units 141 (the current latching/converting circuits 142a and 142b), in the same manner as with the pixel reset operation for the color pixels PIX in row (2i−1), described above. In the state, the reset control signal RSp that is supplied to the pixel reset circuit unit 180 is set to the HIGH level (H), turning ON the transistor Td1, and the color pixels PIX of row 2i are set to the selected state by the scan driver 120. As a result, the ground voltage GND is applied to each of the color pixels PIX of the applicable row through the each of the data lines DL, discharging the residual charge that is stored in the pixel driving circuits DC (the capacitors Cs) and in the data lines DL.
Next, the reset control signal RSp that is supplied to the pixel reset circuit unit 180 is set to the LOW level (L), cutting off the application of the ground voltage GND to the data lines DL, and the reset control signal RSc that is supplied by the current reset control unit 170 is set to the HIGH level (H), applying the specific low-voltage potential Vee to the current-control unit 140. Moreover, synchronized with this timing, a reset operation for discharging the residual charge that is stored in the capacitor CA of the current latching/converting circuit 142a, as with the case described above, is performed by setting the switching control signal LC2 to the HIGH level (H) and the current latching operation for receiving and maintaining the data currents Idata (2i+1) corresponding to the color pixels PIX in row (2i+1) is performed. Simultaneously, the current writing operation for writing to the applicable color pixels PIX the gradation currents Ipix (2i), in accordance with the data currents. Idata (2i) corresponding to the color pixels PIX of row 2i, received and maintained in the current latching/converting circuit 142b during the first operating period is performed at this time.
That is to say, the transistors Tb1 and Tb2 are turned ON and the transistor Tb5 is turned OFF in the current latching/converting circuit 142b through the switching control signal LC1 being set to the LOW level (L) and the switching control signal LC2 being set to the HIGH level (H). Because of this, a gradation current Ipix (2i), having a current value based on the charge stored in the capacitor CB (that is, based on the data current Idata) is drawn towards the low-voltage potential Vee through the transistors Tb5 and Tb4 from the data line side. As a result, in the pixel reset operation described above, charges (voltage components) in accordance with the gradation currents Ipix (2i) are maintained in the pixel driving circuits DC for the applicable color pixels PIX by maintaining the selected state that was set to the color pixels PIX in row 2i (current writing operation).
Following this, by repeatedly performing this type of series of driving control operations, not only is it possible to discharge the charge that remains in the current value converting circuit unit 141 (the current latching/converting circuits 142a and 142b) that receives the data currents Idata in accordance with the display data, in the color pixels PIX to which the gradation currents Ipix have been written, and in the data lines DL, to thereby perform initialization in advance, but also to continuously write the gradation currents Ipix in accordance with the current efficiencies of the applicable color pixels PIX to the color pixels PIX in each row while receiving continuously the data currents Idata for each row from the current driver 130.
Consequently, in the present embodiment the charge that is remaining in each color pixel and data line, and in the current mirror circuits of the current latching/converting circuits, can be discharged through the current latching operation and the current writing operation in the current value converting-circuit unit (the current latching/converting circuits) for each column. Because of this, it is possible to prevent a phenomenon wherein the color pixel (light emitting element) cannot perform the light emitting operation at a brightness gradation that is in accordance with the display data because the gradation current changes from the actual current value that is in accordance with the display data due to charge that is remaining in the individual color pixels and data lines, and in the current mirror circuits of the current latching/converting circuits. Consequently, it is possible to achieve a display device having a desirable display quality by preventing the occurrence of, for example, non-uniform display, brightness deviations, and the like.
Note that in the present embodiment, the explanation is for a structure, as shown in
Note that in the present embodiment, the explanation is for a structure wherein a pixel reset circuit unit (reset circuit) having the characteristics of the present embodiment is applied to the display device shown in the first example embodiment, described above (shown in
In this case, as the method for driving the display device, control is performed, in the timing chart illustrated in
Another display device according to the fourth embodiment, described above, will be described next.
Here explanations are omitted or abbreviated for structures that are identical to those of the third embodiment (shown in
In the present embodiment, as with the third embodiment (shown in
That is, as shown in
Here a thin film transistor (field effect transistor) that uses, for example, an n-channel amorphous silicon semiconductor can, as described above, be used for the transistor Td1 that is used in the pixel reset circuit unit 180 (the reset circuits 181). Because of this, the present embodiment enables the integrated fabrication of the current reset circuit 170 in addition to the pixel reset circuit 180 on the same panel substrate (an insulating substrate) as the pixel array 110 (pixel driving circuit DC) and the current control unit 140, using the same manufacturing processes.
Here a driving control operation (pixel reset operation and reset operation) that is unique to the present embodiment will be explained in detail, and explanations of the other operations (the current latching operation and the current writing operation) will be abbreviated or omitted.
In the present embodiment, as with the driving control operation illustrated in
That is, as shown in
Next, the reset control signal RSp that is supplied to the pixel reset circuit unit 180 is set to the LOW level (L), the reset control signal RSc that is supplied to the current reset circuit unit 170 is set to the HIGH level (H), the enable signal ENB is set to the LOW level (L), and the switching control signal LC1 is set to the HIGH level (H). Doing so causes the specific low-voltage potential Vee to be applied to the current latching/converting circuit 142b, discharging the residual charge that is stored in the capacitor CB (reset operation).
Thereafter, as with the driving control operation illustrated in the
Given the present embodiment, the residual charge that is stored in the color pixels for the applicable row and in the data lines can be discharged to perform initialization prior to the current writing operation to the color pixels in the individual rows, and the residual charge that is stored in the current value converting circuit units (current latching/converting circuits) can be discharged to perform initialization prior to the current latching operation in the current value converting circuit unit for each column. Because of this, it is possible to generate, and to supply to each color pixel, a gradation current that has a current value that is appropriate to the display data and to the current efficiency, and possible to achieve a desirable display quality through controlling the occurrence of, for example, non-uniform displays and brightness deviations, and the like.
Various embodiments and changes may be made thereunto without departing from the broad spirit and scope of the invention. The above-described embodiments are intended to illustrate the present invention, not to limit the scope of the present invention. The scope of the present invention is shown by the attached claims rather than the embodiments. Various modifications made within the meaning of an equivalent of the claims of the invention and within the claims are to be regarded to be in the scope of the present invention.
This application is based on Japanese Patent Application No. 2007-020396 filed on Jan. 31, 2007 and including specification, claims, drawings and summary. The disclosure of the above Japanese Patent Application is incorporated herein by reference in its entirety.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-020396 | Jan 2007 | JP | national |
