Patent Grant
11798450
The present application is a national stage entry of PCT International Application No. PCT/CN2020/073025, filed on Jan. 19, 2020, which claims priority to the Chinese Patent Application No. 201910080264.5, filed on Jan. 28, 2019, the disclosure of PCT International Application No. PCT/CN2020/073025 and the disclosure of Chinese Patent Application No. 201910080264.5 are incorporated herein by reference in its entirety as part of the present application.
Embodiments of the present disclosure relate to a display driving device and a control method thereof, and a display device.
Currently, a display panel is driven to display an image after display data of a to-be-displayed frame image is processed by a processing chip and then output to the display panel. With the appearance of high-resolution display panels, requirements on the memory bandwidth and the transmission interfaces become higher.
At least one embodiment of the present disclosure provides a control method of a display driving device, the display driving device including: at least two processing chips and memories in signal connection with the at least two processing chips in a one-to-one correspondence; each of the memories including a plurality of frame addresses set in order; each to-be-displayed frame image including at least two image regions, and the at least two image regions being in a one-to-one correspondence with the at least two processing chips; one of the at least two processing chips being a master processing chip, and a remainder of the at least two processing chips being a slave processing chip;
For example, in the embodiments of the present disclosure, the control method further includes: receiving, by the master processing chip, a frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image; receiving, by the slave processing chip, the frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image; and
For example, in the embodiments of the present disclosure, subsequent to the generating, by the master processing chip, the read/write synchronization signal upon caching the received display data, and receiving, by each of the slave processing chip, the read/write synchronization signal, the control method further includes:
For example, in the embodiments of the present disclosure, the image regions in each of the to-be-displayed frame image extend in a column direction of pixel units of the display panel and are arranged in a row direction of the pixel units of the display panel.
For example, in the embodiments of the present disclosure, the frame start signal is a field sync signal.
For example, in the embodiments of the present disclosure, in the memory, an order of the frame address caching the display data of the previous to-be-displayed frame image is before an order of the frame address caching the display data of the current to-be-displayed frame image.
For example, in the embodiments of the present disclosure, the frame address of the memory in signal connection with the master processing chip for caching the display data of the current to-be-displayed frame image is the same as the frame address of the memory in signal connection with each of the slave processing chip for caching the display data of the current to-be-displayed frame image.
For example, in the embodiments of the present disclosure, the frame address of the memory in signal connection with the master processing chip for caching the display data of the current to-be-displayed frame image is different from the frame address of the memory in signal connection with each of the slave processing chip for caching the display data of the current to-be-displayed frame image.
For example, in the embodiments of the present disclosure, sizes of the image regions are identical.
For example, in the embodiments of the present disclosure, the plurality of frame addresses of the memory in signal connection with the processing chip are used to store display data of each to-be-displayed frame image circularly in sequence.
Correspondingly, the embodiments of the present disclosure further provide a display driving device, which includes:
For example, in the embodiments of the present disclosure, the master processing chip is further configured to receive a frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image, and generate a frame start synchronization signal according to the frame start signal; in response to the frame start synchronization signal and the frame start signal, to generate a drive timing corresponding to the display data received by the master processing chip; in response to the read/write synchronization signal, to cache the received display data of the current to-be-displayed frame image and the corresponding drive timing into the frame address of the memory in signal connection with the master processing chip, read and process the display data of the previous to-be-displayed frame image cached in the memory in signal connection with the master processing chip and a corresponding drive timing and transmit the processed display data and the processed corresponding drive timing to the display panel;
For example, in the embodiments of the present disclosure, each of the at least two processing chips is further configured to receive display data of a corresponding image region in at least two to-be-displayed frame images; to cache the received display data of the at least two to-be-displayed frame images into the memory in signal connection with the processing chip by circularly using the plurality of frame addresses of the memory in sequence, and based on the plurality of frame addresses of the memory, to circularly read and convert display data of the to-be-displayed frame image cached in the memory in signal connection with the processing chip in sequence, and to transmit the converted display data to the display panel.
For example, in the embodiments of the present disclosure, the processing chip includes: a field programmable gate array chip.
For example, in the embodiments of the present disclosure, the memory includes: a double data rate synchronous dynamic random access memory.
At least one embodiment of the present disclosure further provides a display device, which includes: a display panel and any one of the above-mentioned display driving device,
In order to clearly illustrate the technical solution of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the present disclosure and thus are not limitative of the present disclosure.
In order to make objects, technical details and advantages of the embodiments of the present disclosure apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the present disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the present disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the present disclosure.
In practical designs, the memory bandwidth and the number of transmission interfaces of a processing chip are limited, which results in that a single processing chip may not meet the requirement of a high-resolution display panel, and therefore two or more processing chips are required. However, such design may not guarantee that display data output by each of a plurality of processing chips belongs to the same frame image, thereby causing abnormal display of the image, although fitting the design of high-resolution display panels.
Generally, the processing chip may be configured as a field programmable gate array (FPGA) chip. Therefore, the display data of the to-be-displayed frame image may be output to the display panel after being subjected to related image processing performed by the FPGA chip, so as to drive the display panel and realize image display. The general method is as follows. The display data of a plurality of to-be-displayed frame images are cached through the FPGA chip in a memory electrically connected with the FPGA chip, and then the display data cached in the memory is read and processed by the FPGA chip, and output to the display panel.
With the appearance of high-resolution display panels, requirements on the memory bandwidth and high-speed transmission interfaces become higher. In practical designs, the memory bandwidth and the number of transmission interfaces of a processing chip are limited, which results in that a single processing chip may not meet the requirement of the high-resolution display panel, and therefore two or more processing chips are required. Due to the arrangement of the plurality of FPGA chips, usually, a to-be-displayed frame image is divided into a plurality of regions, one region corresponds to one FPGA chip, and one FPGA chip is provided with one memory correspondingly. The display data of the same region corresponding to a plurality of to-be-displayed frame images is stored in the corresponding memory in sequence by each FPGA chip, and then, the display data in the corresponding memory is read, processed and output to the display panel. This design may meet the requirements of high-resolution display panels.
In order to ensure that the display data output by each of the plurality of FPGA chips can all belong to the same frame image, the frame addresses of the memories is usually shared between the FPGA chips. That is, when the display data of a certain to-be-displayed frame image is stored into the frame address of the corresponding memory by one FPGA chip, the frame addresses of the memories corresponding to other FPGA chips also change synchronously, so as to synchronously store the display data of the to-be-displayed frame image into the frame addresses of the corresponding memories. However, in the case where the memory initialization fails or the transmission interface may not be locked, the frame address of the memory of a certain FPGA chip may be suddenly changed, for example, reset. Since the frame addresses of the memories are shared among the FPGA chips, if the frame address of the memory of a certain FPGA chip changes suddenly, the frame addresses of the memories of the other FPGA chips also change suddenly. This may cause that the display data stored in and read from the memory by each FPGA chip may not belong to the same frame image, thereby causing abnormal display of the image.
In view of the above, as shown in
Moreover, each to-be-displayed frame image may include at least two image regions AA_m, and in the same to-be-displayed frame image, each image region AA_m corresponds to one processing chip 100_m. For example, the image region AA_1 corresponds to the processing chip 100_1, and the image region AA_2 corresponds to the processing chip 100_2, and so on, which is not described in detail herein. One of the M processing chips is defined as a master processing chip, and the rest of the processing chips are defined as slave processing chips. For example, the processing chip 100_1 is defined as a master processing chip, and the processing chips 100_2 to 100_M are defined as slave processing chips.
As shown in
S201, receiving, by the master processing chip, display data of a corresponding image region in a current to-be-displayed frame image; receiving, by each slave processing chip, display data of a corresponding image region in the current to-be-displayed frame image;
S202, generating, by the master processing chip, a read/write synchronization signal upon caching the received display data, and receiving, by each slave processing chip, the read/write synchronization signal;
S203, in response to the read/write synchronization signal, caching, by the master processing chip, the received display data of the current to-be-displayed frame image into a frame address of a corresponding memory electrically connected with the master processing chip, reading and processing display data of a previous to-be-displayed frame image cached in the electrically connected memory and transmitting the processed display data to a display panel; synchronously caching, by each slave processing chip, the received display data of the current to-be-displayed frame image to a frame address of a corresponding memory electrically connected with each slave processing chip in response to the read/write synchronization signal, and synchronously reading and processing display data of the previous to-be-displayed frame image cached in the connected memory and transmitting the processed display data to the display panel. In an embodiment, in response to the read/write synchronization signal, the master processing chip and each slave processing chip synchronously cache the received display data of the current to-be-displayed frame image into the frame addresses of the corresponding memories electrically connected with the master processing chip and each slave processing chip, synchronously read and process the display data of the previous to-be-displayed frame image cached in the connected memories and transmit the processed display data to the display panel.
In the control method of the display driving device according to the embodiment of the present disclosure, the arrangement of one master processing chip and a plurality of slave processing chips may facilitate the design of the high-resolution display panel. When caching the received display data of the corresponding image region in the current to-be-displayed frame image, the master processing chip may generate and transmit the read/write synchronization signal to each slave processing chip. By the read/write synchronization signal controlling the master processing chip and each slave processing chip, the received display data of the current to-be-displayed frame image is cached into the frame addresses of the electrically connected corresponding memories, and the display data of the previous to-be-displayed frame image cached in the electrically connected memories is read and processed and then transmitted to the display panel, so as to drive the display panel to display the image. Since the master processing chip and each slave processing chip are controlled by the read/write synchronization signal to control the storage and reading operations of the memories, the frame addresses of the memories are prevented from being shared among the processing chips, so that when the frame address of the memory corresponding to a certain processing chip changes suddenly, the frame addresses of the memories corresponding to the other processing chips may not be influenced, thereby ensuring that the display data output by each processing chip belong to the same frame image, thereby eliminating the problem of abnormal image display caused by the asynchronization of the plurality of processing chips.
In particular implementations, as shown in
In particular implementations, as shown in
Further, in particular implementations, in the memory, the order of the frame address caching the display data of the previous to-be-displayed frame image may be before the order of the frame address caching the display data of the current to-be-displayed frame image. This ensures that the read frame address is located before the stored frame address, thereby avoiding the problem of display abnormality. For example, the processing chip 100_m stores the display data of the corresponding image region AA_m in the first to-be-displayed frame image in the frame address 0 of the corresponding memory 200_m, and then, the processing chip 100_m, in response to the read/write synchronization signal, stores the display data of the corresponding image region AA_m in the second to-be-displayed frame image in the frame address 1 of the corresponding memory 200_m, and reads and converts the display data of the first to-be-displayed frame image stored in the frame address 0 of the corresponding memory 200_m and transmits the display data to the display panel. Subsequently, in response to the read/write synchronization signal, the processing chip 100_m stores the display data of the corresponding image region AA_m in the third to-be-displayed frame image in the frame address 2 of the corresponding memory 200_m, reads and converts the display data of the second to-be-displayed frame image stored in the frame address 1 of the corresponding memory 200_m, and then transmits the display data to the display panel. The rest are the same and not repeated herein.
In particular implementations, each processing chip 100_m may be configured to receive the display data of the corresponding image region AA_m in at least two to-be-displayed frame images, to circularly cache the received display data of the at least two to-be-displayed frame images into the frame addresses of the electrically connected memory 200_m in sequence in response to the read/write synchronization signal, and to circularly read and convert the display data of the to-be-displayed frame images cached in the corresponding memory 200_m in sequence and then transmit the read display data to the display panel. In an embodiment, each processing chip 100_m may be configured to receive the display data of the corresponding image regions AA_m of at least two to-be-displayed frame images, in response to the read/write synchronization signal, cache the received display data of the at least two to-be-displayed frame images into the electrically connected memory 200_m by circularly using a plurality of frame addresses of the electrically connected memory 200_m in sequence (e.g., circularly caching in the order of the frame address 1, the frame address 2, the frame address 0, the frame address 1, the frame address 2 . . . ), and based on the plurality of frame addresses of the memory 200_m, circularly read and convert the display data of the to-be-displayed frame image cached in the corresponding memory 200_m in sequence, and transmit the converted display data to the display panel (for example, circularly reading the display data in the order of the frame address 0, the frame address 1, the frame address 2, the frame address 0 and the frame address 1 . . . ). This avoids storing and reading the same frame address in the memory, thereby avoiding the problem of display abnormality.
Specifically, the memory 200_m may store N frame addresses. For example, taking N=3 as an example, the memory 200_m may store 3 frame addresses: frame address 0, frame address 1, and frame address 2. For example, a new video has 300 continuous images, and the processing chip 100_m circularly receives the display data of the corresponding image region AA_m in the three to-be-displayed frame images. The processing chip 100_m circularly caches the received display data of the three to-be-displayed frame images (i.e. the display data of the three continuous to-be-displayed frame images) in sequence into the frame addresses of the electrically connected memory 200_m, and circularly reads and converts the display data of the three to-be-displayed frame images cached in the corresponding memory 200_m in sequence and then transmits the read display data to the display panel, which may be as follows. In response to the read/write synchronization signal, the display data of the first to-be-displayed frame image of the new video is stored in the frame address 0 of the corresponding memory 200_m, and the display data of the to-be-displayed frame image of the previous video stored in the frame address 0 is read, converted and transmitted to the display panel. Subsequently, in response to the read/write synchronization signal, the display data of the second to-be-displayed frame image is stored in the frame address 1 of the corresponding memory 200_m, the display data of the first to-be-displayed frame image stored in the frame address 0 is read and converted, and then transmitted to the display panel, so that the display panel displays the first to-be-displayed frame image. Afterwards, in response to the read/write synchronization signal, the display data of the third to-be-displayed frame image is stored in the frame address 2 of the corresponding memory 200_m, the display data of the second to-be-displayed frame image stored in the frame address 1 is read and converted, and then transmitted to the display panel, so that the display panel displays the second to-be-displayed frame image. Subsequently, in response to the read/write synchronization signal, the display data of the fourth to-be-displayed frame image is stored in the frame address 0 of the corresponding memory 200_m, the display data of the third to-be-displayed frame image stored in the frame address 2 is read and converted, and then transmitted to the display panel, so that the display panel displays the third to-be-displayed frame image. Afterwards, in response to the read/write synchronization signal, the display data of the fifth to-be-displayed frame image is stored in the frame address 1 of the corresponding memory 200_m, the display data of the fourth to-be-displayed frame image stored in the frame address 0 is read and converted, and then transmitted to the display panel, so that the display panel displays the fourth to-be-displayed frame image. Subsequently, in response to the read/write synchronization signal, the display data of the sixth to-be-displayed frame image is stored in the frame address 2 of the corresponding memory 200_m, the display data of the fifth to-be-displayed frame image stored in the frame address 1 is read and converted, and then transmitted to the display panel, so that the display panel displays the fifth to-be-displayed frame image. Afterwards, reading is circularly performed in the order of the frame address 0, the frame address 1 and the frame address 2, and circular reading is performed in the order of the frame address 2, the frame address 0 and the frame address 1 to drive the display panel to display, which is not repeated herein.
Further, in order to synchronize the drive timing of the display data received by each processing chip, in particular implementations, in the embodiment of the present disclosure, the master processing chip further receives a frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image, and the slave processing chip further receives the frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image. Namely, each processing chip also receives the frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image.
For example, before the master processing chip generates the read/write synchronization signal upon caching the received display data and each slave processing chip receives the read/write synchronization signal, the control method according to at least one embodiment of the present disclosure may further include:
For example, after the master processing chip generates the read/write synchronization signal upon caching the received display data and each slave processing chip receives the read/write synchronization signal, the control method according to at least one embodiment of the present disclosure may include:
Therefore, the master processing chip also receives the frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image, and generates the frame start synchronization signal according to the frame start signal; then, generates the drive timing corresponding to the display data received by the master processing chip in response to the frame start synchronization signal and the frame start signal. Subsequently, the read/write synchronization signal is generated upon the master processing chip caches the received display data, to cache the received display data of the current to-be-displayed frame image and the corresponding drive timing into the frame address of the electrically connected corresponding memory in response to the read/write synchronization signal, read and process the display data of the previous to-be-displayed frame image and the corresponding drive timing cached in the electrically connected memory, and transmit the processed display data to the display panel. The slave processing chip also receives the frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image; and the slave processing chip also receives the frame start synchronization signal transmitted from the master processing chip, and generates the drive timing corresponding to the display data received by the slave processing chip in synchronization with the master processing chip in response to the frame start synchronization signal and the frame start signal. Subsequently, each slave processing chip receives the read/write synchronization signal, so as to cache the received display data of the current to-be-displayed frame image and the corresponding drive timing in synchronization with the master processing chip into the frame address of the electrically connected corresponding memory in response to the read/write synchronization signal, and reads and processes the display data of the previous to-be-displayed frame image and the corresponding drive timing cached in the electrically connected memory in synchronization with the master processing chip and transmit the processed display data to the display panel. Therefore, the master processing chip may determine the start of a frame image through the frame start signal, so as to generate the frame start synchronization signal, and simultaneously control the drive timing of the display data respectively received by the master processing chip and the slave processing chip through the frame start synchronization signal, so that the timing for driving the display data to display may be aligned, and the image may be refreshed synchronously.
In particular implementations, in the embodiment of the present disclosure, the image region in each to-be-displayed frame image may extend in a column direction of pixel units of the display panel and arranged in a row direction of the pixel units of the display panel. That is, each to-be-displayed frame image may include M image regions arranged in sequence in the row direction of the pixel units of the display panel. Taking M=2 as an example, as shown in
Usually, as shown in
Further, an HS signal, an effective display data strobe signal (DE) signal, or the like, are also provided in the display panel. In particular implementations, in the embodiment of the present disclosure, each processing chip may further receive at least one of the HS signal and the DE signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image, which is not limited herein. Certainly, the functions of the HS signal and the DE signal are substantially the same as the existing functions thereof, and it should be understood by those skilled in the art that the details are not described herein, and the present disclosure should not be limited thereto.
In particular implementations, in the embodiment of the present disclosure, the size of each image regions AA_m may be the same. Therefore, the data stored, read and processed by each processing chip is uniform, the power consumption of each processing chip is uniform, and the service life of each processing chip is uniform.
Based on the same inventive concept, at least one embodiment of the present disclosure further provides a display driving device adapted to implement the above-mentioned control method according to at least one embodiment of the present disclosure. As shown in
Each of the slave processing chips 100_2 to 100_M (M is an integer greater than 1) is configured to receive the read/write synchronization signal and display data AA_2 to AA_M of the corresponding image region in the current to-be-displayed frame image, to synchronously cache the received display data of the current to-be-displayed frame image in the frame addresses of the electrically connected corresponding memories 200_2 to 200_M in response to the read/write synchronization signal, and to synchronously read and process the display data of the previous to-be-displayed frame image cached in the connected memories 200_2 to 200_M and transmit the processed display data to the display panel 300.
In an embodiment, in response to the read/write synchronization signal, the master processing chip 100_1 and each of the slave processing chips 100_2 to 100_M synchronously cache the received display data of the current to-be-displayed frame image into the frame addresses of the electrically connected corresponding memories 200_1 to 200_M, and synchronously read and process the display data of the previous to-be-displayed frame image cached in the connected memories 200_1 to 200_M and transmit the processed display data to the display panel 300.
In the display driving device according to the embodiment of the present disclosure, the arrangement of one master processing chip and at least one slave processing chip may facilitate the design of the high-resolution display panel. When the received display data of the corresponding image region in the current to-be-displayed frame image is cached by the master processing chip, the read/write synchronization signal may be generated and transmitted to each slave processing chip. By the read/write synchronization signal controlling the master processing chip and each slave processing chip, the received display data of the current to-be-displayed frame image is cached into the frame addresses of the electrically connected corresponding memories, and the display data of the previous to-be-displayed frame image cached in the electrically connected memory is read and processed and then transmitted to the display panel, so as to drive the display panel to display the image. Since the master processing chip and each slave processing chip are controlled by the read/write synchronization signal to control the storage and reading operations of the memories, the frame addresses of the memories are prevented from being shared among the processing chips, so that when the frame address of the memory corresponding to a certain processing chip changes suddenly, the frame addresses of the memories corresponding to the other processing chips may not be influenced, thereby ensuring that the display data output by each processing chip belong to the same frame, and further eliminating the problem of abnormal image display caused by the asynchronization of the plurality of processing chips.
For example, the display driving device according to the embodiment of the present disclosure may be applied to a 4K (3840×2160) display panel, an 8K (7680×4320) display panel, and the like, which is not limited in the embodiment of the present disclosure.
In particular implementations, in the embodiment of the present disclosure, each processing chip is configured to receive the display data of the corresponding image region in at least two to-be-displayed frame images; to cache the received display data of at least two to-be-displayed frame images into an electrically connected memory by circularly using a plurality of frame addresses of the electrically connected memory in sequence, and based on the plurality of frame addresses of the electrically connected memory, to circularly read and convert the display data of the to-be-displayed frame images cached in the electrically connected corresponding memory in sequence, and to transmit the converted display data to the display panel; wherein for each to-be-displayed frame image, in response to the read/write synchronization signal, the display data of the current to-be-displayed frame image is cached into the frame address of the electrically connected memory, and in response to the read/write synchronization signal, the display data of the previous to-be-displayed frame image cached in the connected memory is synchronously read and processed, and transmitted to the display panel.
In particular implementations, in the embodiment of the present disclosure, the master processing chip is further configured to receive the frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image, and to generate the frame start synchronization signal according to the frame start signal; to generate the drive timing corresponding to the display data received by the master processing chip in response to the frame start synchronization signal and the frame start signal; to cache the received display data of the current to-be-displayed frame image and the corresponding drive timing into the frame address of the electrically connected corresponding memory in response to the read/write synchronization signal, read and process the display data of the previous to-be-displayed frame image and the corresponding drive timing cached in the electrically connected memory, and transmit the processed display data to the display panel.
The slave processing chip is further configured to receive the frame start synchronization signal and the frame start signal upon receiving the display data of the corresponding image region in the current to-be-displayed frame image; to synchronously generate the drive timing corresponding to the display data received from the slave processing chip in response to the frame start synchronization signal and the frame start signal; to synchronously cache the received display data of the current to-be-displayed frame image and the corresponding drive timing with the master processing chip into the frame address of the electrically connected corresponding memory in response to the read/write synchronization signal, and to synchronously read and process the display data of the previous to-be-displayed frame image and the corresponding drive timing cached in the electrically connected memory with the master processing chip and transmit the processed display data to the display panel.
In particular implementations, in embodiments of the present disclosure, the memory may include: Double Data Rate Synchronous Random Access Memory (DDR SDRAM). Certainly, in practical applications, the memory may also be other types of memory, which is not limited herein.
In particular implementations, in the embodiment of the present disclosure, the processing chip 100_m may include: a field programmable gate array chip (FPGA chip). As shown in
In particular implementations, the input interfaces RX1_m and RX2_m are electrically connected with a signal reception interface 400. The input interfaces RX1_m and RX2_m may include: high Definition Multimedia Interfaces (HDMI), such as an HDMI 2.0 interface. Certainly, the input interfaces RX1_m and RX2_m may also be other interfaces capable of achieving the effects of the present disclosure, and are not limited herein.
In particular implementations, the FIFO storage module may be an FIFO memory, which may be a Random Access Memory (RAM) inside the FPGA chip, for storing the display signals received by the input interfaces RX1_m and RX2_m. Moreover, the FIFO memory in the master processing chip is further configured to generate the frame start synchronization signal according to the frame start signal, and provide it to the timing generation module 120_1 in each slave processing chip. Moreover, the structure of the FIFO memory may be substantially the same as existing structures and variations thereof, and will not be described herein.
In particular implementations, the timing generation module 120_m may include a timing generator for synchronously generating the drive timing corresponding to the display data received by each processing chip 100_m in response to the frame start synchronization signal and the corresponding frame start signal.
In particular implementations, the write memory controller 130_m may include a Write Direct Memory Access (WDMA) engine. Moreover, the structure of the WDMA engine may be substantially the same as existing structures and variations thereof, and will not be described herein.
In particular implementations, the read memory controller 140_m may include a Read Direct Memory Access (RDMA) engine. Moreover, the structure of the RDMA engine may be substantially the same as existing structures and variations thereof, and will not be described herein.
In particular implementations, the output port 170_m may include a V-By-One interface. Moreover, the structure of the V-By-One interface may be substantially the same as existing structures and variations thereof, and will not be described herein.
Further, as shown in
Particularly, taking the structure of the drive device shown in
The master processing chip 100_1 receives the frame start signal and the display data of the corresponding image region AA_1 in the first to-be-displayed frame image through the input interfaces RX1_1 and RX2_1, and stores the frame start signal and the received display data of the corresponding image region AA_1 in the current to-be-displayed frame image into the FIFO storage module 110_1. The slave processing chip 100_2 receives the frame start signal and the display data of the corresponding image region AA_2 in the first to-be-displayed frame image through the input interfaces RX1_2 and RX2_2, and stores the received frame start signal and the received display data of the corresponding image region AA_2 in the current to-be-displayed frame image into the FIFO storage module 110_2.
The FIFO storage module 110_1 generates a frame start synchronization signal FS_1 according to the frame start signal, and transmits the frame start synchronization signal FS_1 to the timing generation module 120_1 of the master processing chip 100_1 and the timing generation module 120_2 of the slave processing chip 100_2.
The timing generation module 120_1 in the master processing chip 100_1 generates a drive timing corresponding to the display data received by the master processing chip 100_1 in response to the frame start synchronization signal FS_1 and the corresponding frame start signal. Also, the timing generation module 120_2 in the slave processing chip 100_2 synchronously generates a drive timing corresponding to the display data received by the slave processing chip 100_2 in response to the frame start synchronization signal FS_1 and the corresponding frame start signal, so as to perform synchronous processing on the display data received by the master processing chip 100_1 and the slave processing chip 100_2, so that the display data in the two chips are aligned.
The write memory controller 130_1 in the master processing chip 100_1 receives the display data stored in the FIFO storage module 110_1 and the drive timing corresponding to the display data, generates a read/write synchronization signal DX_1, and transmits the read/write synchronization signal DX_1 to the read memory controller 140_1 in the master processing chip 100_1, the write memory controller 130_2 in the slave processing chip 100_2, and the read memory controller 140_2.
The write memory controller 130_1 in the master processing chip 100_1 caches the received display data of the first to-be-displayed frame image and the corresponding drive timing into the frame address 0 of the electrically connected memory 200_1 in response to the read/write synchronization signal DX_1, and reads and processes the display data of the previous to-be-displayed frame image and the corresponding drive timing cached in the memory 200_1 in response to the read/write synchronization signal DX_1, and transmits the processed display data to the display panel 200 through the port 170_1. Moreover, the write memory controller 130_2 in the slave processing chip 100_2 caches the received display data of the first to-be-displayed frame image and the corresponding drive timing into the frame address 0 of the electrically connected memory 200_2 in response to the read/write synchronization signal DX_1, and reads and processes the display data of the previous to-be-displayed frame image and the corresponding drive timing cached in the memory 200_2 in response to the read/write synchronization signal DX_1, and transmits the processed display data to the display panel 200 through the port 170_2. This enables the display panel 200 to display the previous frame image.
Then, the master processing chip 100_1 receives the frame start signal and the display data of the corresponding image region AA_1 in the second to-be-displayed frame image through the input interfaces RX1_1 and RX2_1, and stores the received frame start signal and the received display data of the corresponding image region AA_1 in the current to-be-displayed frame image into the FIFO storage module 110_1. The slave processing chip 100_2 receives the frame start signal and the display data of the corresponding image region AA_2 in the second to-be-displayed frame image through the input interfaces RX1_2 and RX2_2, and stores the received frame start signal and the received display data of the corresponding image region AA_2 in the current to-be-displayed frame image into the FIFO storage module 110_2.
The FIFO storage module 110_1 generates a frame start synchronization signal FS_2 according to the frame start signal, and transmits the frame start synchronization signal FS_2 to the timing generation module 120_1 of the master processing chip 100_1 and the timing generation module 120_2 of the slave processing chip 100_2.
The timing generation module 120_1 in the master processing chip 100_1 generates a drive timing corresponding to the display data received by the master processing chip 100_1 in response to the frame start synchronization signal FS_2 and the corresponding frame start signal. Also, the timing generation module 120_2 in the slave processing chip 100_2 synchronously generates a drive timing corresponding to the display data received by the slave processing chip 100_2 in response to the frame start synchronization signal FS_2 and the corresponding frame start signal, so as to perform synchronous processing on the display data received by the master processing chip 100_1 and the slave processing chip 100_2, so that the display data in the two chips are aligned.
The write memory controller 130_1 in the master processing chip 100_1 receives the display data stored in the FIFO storage module 110_1 and the drive timing corresponding to the display data, generates a read/write synchronization signal DX_2, and transmits the read/write synchronization signal DX_2 to the read memory controller 140_1 in the master processing chip 100_1, the write memory controller 130_2 in the slave processing chip 100_2, and the read memory controller 140_2.
The write memory controller 130_1 in the master processing chip 100_1 caches the received display data of the second to-be-displayed frame image and the corresponding drive timing into the frame address 1 of the electrically connected memory 200_1 in response to the read/write synchronization signal DX_2, and reads and processes the display data of the first to-be-displayed frame image and the corresponding drive timing cached in the memory 200_1 in response to the read/write synchronization signal DX_2, and transmits the processed display data to the display panel 200 through the port 170_1. Moreover, the write memory controller 130_2 in the slave processing chip 100_2 caches the received display data of the second to-be-displayed frame image and the corresponding drive timing into the frame address 1 of the electrically connected memory 200_2 in response to the read/write synchronization signal DX_2, and reads and processes the display data of the first to-be-displayed frame image and the corresponding drive timing cached in the memory 200_2 in response to the read/write synchronization signal DX_2, and transmits the processed display data to the display panel 200 through the port 170_2. This enables the display panel 200 to display the first frame image.
Then, the master processing chip 100_1 receives the frame start signal and the display data of the corresponding image region AA_1 in the third to-be-displayed frame image through the input interfaces RX1_1 and RX2_1, and stores the received frame start signal and the received display data of the corresponding image region AA_1 in the current to-be-displayed frame image into the FIFO storage module 110_1. The slave processing chip 100_2 receives the frame start signal and the display data of the corresponding image region AA_2 in the third to-be-displayed frame image through the input interfaces RX1_2 and RX2_2, and stores the received frame start signal and the received display data of the corresponding image region AA_2 in the current to-be-displayed frame image into the FIFO storage module 110_2.
The FIFO storage module 110_1 generates a frame start synchronization signal FS_3 according to the frame start signal, and transmits the frame start synchronization signal FS_3 to the timing generation module 120_1 of the master processing chip 100_1 and the timing generation module 120_2 of the slave processing chip 100_2.
The timing generation module 120_1 in the master processing chip 100_1 generates a drive timing corresponding to the display data received by the master processing chip 100_1 in response to the frame start synchronization signal FS_3 and the corresponding frame start signal. Also, the timing generation module 120_2 in the slave processing chip 100_2 synchronously generates a drive timing corresponding to the display data received by the slave processing chip 100_2 in response to the frame start synchronization signal FS_3 and the corresponding frame start signal, so as to perform synchronous processing on the display data received by the master processing chip 100_1 and the slave processing chip 100_2, so that the display data in the two chips are aligned.
The write memory controller 130_1 in the master processing chip 100_1 receives the display data stored in the FIFO storage module 110_1 and the drive timing corresponding to the display data, generates a read/write synchronization signal DX_3, and transmits the read/write synchronization signal DX_3 to the read memory controller 140_1 in the master processing chip 100_1, the write memory controller 130_2 in the slave processing chip 100_2, and the read memory controller 140_2.
The write memory controller 130_1 in the master processing chip 100_1 caches the received display data of the third to-be-displayed frame image and the corresponding drive timing into the frame address 2 of the electrically connected memory 200_1 in response to the read/write synchronization signal DX_3, and reads and processes the display data of the second to-be-displayed frame image and the corresponding drive timing cached in the memory 200_1 in response to the read/write synchronization signal DX_2, and transmits the processed display data to the display panel 200 through the port 170_1. Moreover, the write memory controller 130_2 in the slave processing chip 100_2 caches the received display data of the third to-be-displayed frame image and the corresponding drive timing into the frame address 2 of the electrically connected memory 200_2 in response to the read/write synchronization signal DX_3, and reads and processes the display data of the second to-be-displayed frame image and the corresponding drive timing cached in the memory 200_2 in response to the read/write synchronization signal DX_3, and transmits the processed display data to the display panel 200 through the port 170_1. This enables the display panel 200 to display the second frame image. The rest may be done in the same manner, and is not described in detail herein.
In some embodiments of the present disclosure, the frame address of the memory, which is electrically connected to the master processing chip, for caching the display data of the current to-be-displayed frame image may be the same as the frame address of the memory, which is electrically connected to each slave processing chip, for caching the display data of the current to-be-displayed frame image. This makes the frame address for reading the stored display data from the memory the same. Certainly, in some other embodiments, the frame address of the memory electrically connected to the master processing chip for caching the display data of the current to-be-displayed frame image may be different from the frame address of the memory electrically connected to each of the slave processing chips for caching the display data of the current to-be-displayed frame image, which is not limited in the embodiments of the present disclosure.
Based on the same inventive concept, the embodiment of the present disclosure further provides a display device. As shown in
In particular implementations, in the embodiment of the present disclosure, the display panel may be, for example, a liquid crystal display panel or an electroluminescence display panel, which is not limited herein.
In particular implementations, in the embodiment of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display panel, a notebook computer, a digital photo frame, a navigator, or the like. Other essential components of the display device are understood to be necessary by those skilled in the art, and are not described herein, without being construed as limiting the present disclosure.
In the display driving device, control method thereof and display device according to the embodiment of the present disclosure, the arrangement of one master processing chip and at least one slave processing chip may facilitate the design of the high-resolution display panel. When the received display data of the corresponding image region in the current to-be-displayed frame image is cached by the master processing chip, the read/write synchronization signal may be generated and transmitted to each slave processing chip. By the read/write synchronization signal controlling the master processing chip and each slave processing chip, the received display data of the current to-be-displayed frame image is cached into the frame addresses of the electrically connected corresponding memories, and the display data of the previous to-be-displayed frame image cached in the electrically connected memory is read and processed and then transmitted to the display panel, so as to drive the display panel to display the image. Since the storage and reading operations of the memory are controlled by the read/write synchronization signal controlling the master processing chip and each slave processing chip, the frame addresses of the memories are prevented from being shared among the processing chips, so that when the frame address of the memory corresponding to a certain processing chip changes suddenly, the frame addresses of the memories corresponding to the other processing chips may not be influenced, thereby ensuring that the display data output by each processing chip belong to the same frame, and further eliminating the problem of abnormal image display caused by the asynchronization of the plurality of processing chips.
The above description relates to only exemplary embodiments of the present disclosure and is not intended to limit the scope of the present disclosure; the scopes of the disclosure are defined by the accompanying claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201910080264.5 | Jan 2019 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2020/073025 | 1/19/2020 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2020/156284 | 8/6/2020 | WO | A |
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