DISPLAY DRIVING DEVICE, SOURCE DRIVER, AND DISPLAY DEVICE INCLUDING THEREOF

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0117900, filed in the Korean Intellectual Property Office on Sep. 5, 2023, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

In general, a display panel displays images to provide various visual information to a user. The display panel includes a plurality of pixels, and each of the pixels expresses light of a certain brightness to display an image. A display driver integrated circuit (DDI) is used to drive pixels.

As a number of bits of data representing gray levels increases, a number of level shifters required for one channel may increase, and as a number of DDI channels increases to drive a high-resolution display panel, a number of DDI level shifters operating together may increase for a short time. As multiple level shifters operate together for a short time, a level of peak current may increase. Ground bouncing, which indicates a temporary increase in ground voltage due to a high level of peak current, may affect adjacent circuits, modules, and interfaces.

SUMMARY

The present disclosure relates to display driving devices, including a display driving device that generates a peak current of a low level and a display driving device that displays a high-resolution image with high gray expression, source drivers, and display devices including the same.

In general, according to some aspects, a display driving device includes: a level shifter configured to receive image data and a bias control signal, to generate decoded data including a plurality of bits by level shifting the image data, and to control an output bias current of the decoded image data based on the bias control signal; and a digital-analog converter (DAC) configured to receive the decoded image data and a plurality of gamma voltages, to select one of the gamma voltages based on the decoded image data, and to output the selected gamma voltage.

In general, according to some aspects, a source driver includes: a plurality of amplifier areas each including a level shifter configured to output a plurality of bits of decoded image data, a digital-analog converter (DAC) configured to select one of a plurality of gamma voltages based on the decoded image data, and an amplifier configured to output a data signal obtained by amplifying the selected gamma voltage to a corresponding source line among a plurality of source lines; and a source driver including a bias circuit configured to generate a bias control signal that limits output bias currents of level shifters included in each of the amplifier areas.

In general, according to some aspects, a display device includes: a pixel array configured to include a plurality of pixels; a timing controller configured to receive an image signal and a driving control signal from an outside, to generate a plurality of image data by dividing the image signal, and to generate a bias start signal based on the driving control signal; a plurality of amplifier areas configured to receive the image data and a bias control signal, generate decoded image data by level shifting the image data, control a level of an output bias current of the decoded image data based on a level of the bias control signal, receive the decoded image data and a plurality of gamma voltages, select one of the gamma voltages based on the decoded image data, and output the selected gamma voltage; and a bias circuit configured to receive a bias start signal that controls the bias control signal to be outputted at a first level, and to generate the bias control signal at a second level that different from the first level with reference to data stored in an one-time programmable (OTP) memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example block diagram of a display device.

FIG. 2 illustrates some components of an example of a source driver.

FIG. 3 illustrates a circuit diagram schematically showing a buffer and a level shifting circuit of an example of a source driver.

FIG. 4 illustrates a graph showing an output voltage and a discharging current of an example of a level shifter.

FIG. 5 illustrates a circuit diagram for recovery of an example of a level shifter.

FIG. 6 illustrates a graph showing an output voltage and a discharging current of another example of a level shifter.

FIG. 7 illustrates a block diagram showing an example of a level shifter.

FIG. 8 illustrates a circuit diagram for recovery of another example of a level shifter.

FIG. 9 illustrates a graph showing an output voltage and a discharging current of another example of a level shifter.

FIG. 10 illustrates a block diagram showing another example of a level shifter.

FIG. 11 illustrates a circuit diagram for recovery of another example of a level shifter.

FIG. 12 illustrates a graph showing an output voltage and a discharging current of another example of a level shifter.

FIG. 13 illustrates a block diagram showing another example of a level shifter.

FIG. 14 illustrates a block diagram showing another example of a level shifter.

FIG. 15 illustrates a circuit diagram for recovery of another example of a level shifter.

FIG. 16 illustrates a circuit diagram schematically showing a buffer and a level shifting circuit of another example of a source driver.

FIG. 17 illustrates a circuit diagram schematically showing a buffer and a level shifting circuit of another example of a source driver.

FIG. 18 illustrates a graph showing a simulation result of an output voltage and a discharging current of an example of a level shifter.

FIG. 19 illustrates a graph showing a simulation result of an output voltage and a discharging current of another example of a level shifter.

FIG. 20 illustrates a view for describing an example of a display system.

DETAILED DESCRIPTION

In the following detailed description, certain implementations of the present disclosure have been shown and described, by way of illustration. As those skilled in the art would realize, the described implementations may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

FIG. 1 illustrates an example block diagram of a display device.

Referring to FIG. 1, the display device 100 includes a pixel array 110, a gate driver 120, a source driver 130, and a timing controller 140.

A plurality of pixels PX for displaying an image may be positioned in the pixel array 110. The pixels PX each may be connected to a corresponding source line SL among a plurality of source lines and a corresponding gate line GL among a plurality of gate lines. The pixel PX may receive a data signal from the source line SL if the gate signal is provided to the gate line GL. The pixel PX may express light of a certain brightness corresponding to an inputted data signal. The pixel PX may display an image in one frame unit.

If the display device 100 is an organic light emitting diode display, each of the pixels PX may include a plurality of transistors each including a driving transistor and an organic light emitting diode. The driving transistor included in the pixel PX may supply a current corresponding to a data signal to the organic light emitting diode, and accordingly, the organic light emitting diode may emit light with a predetermined brightness. If the display device 100 is a liquid crystal display, each of the pixels PX may include a switching transistor and a liquid crystal capacitor. The pixel PX may control transmittance of liquid crystal in response to the data signal so that light of a certain brightness is provided to an outside.

In FIG. 1, the pixel PX is illustrated as connected to one source line SL and one gate line GL, a connection structure of signal lines of the pixels PX of the display device is not limited to thereto. For example, various signal lines may be additionally connected in response to a circuit structure of the pixels PX. In some implementations, the pixel PX may be implemented in various currently known forms.

The gate driver 120 may provide a plurality of gate signals G1, G2, . . . , and Gh. The gate signals G1, G2, . . . , and Gh may be pulse signals having an enable level and a disable level. The gate signals G1, G2, . . . , and Gh may be applied to a plurality of gate line GL. If a gate signal of an enable level is applied to the gate line GL connected to pixel PX, a data signal applied to the source line SL connected to the pixel PX may be transferred to the pixel PX. The gate driver 120 may provide the gate signals G1, G2, . . . , and Gh during a plurality of horizontal periods. One frame may include the multiple horizontal periods.

The source driver 130 may receive data DATA in a form of a digital signal from the timing controller 140 and may convert the data DATA into data signals S1, S2, . . . , Sk in a form of an analog signal. Herein, the data DATA may include gray information corresponding to each pixel PX for displaying an image signal IS on the pixel array 110. The source driver 130 may transmit a plurality of data signals S1, S2, . . . , and Sk to the pixel array 110 according to a source driver control signal CONT2 provided from the timing controller 140. The source driver 130 may be referred to as a data driver.

The source driver 130 may be electrically connected to a plurality of source lines SL. The source driver 130 may transmit a plurality of data signals S1, S2, . . . , and Sk to the source lines SL electrically connected thereto.

The source driver 130 may include a shift register 131, a plurality of amplifier areas 132a, 132b, . . . , and 132h, a bias circuit 136, and a gamma voltage generator 138. Each component included in the source driver 130 is not limited to an example shown in FIG. 1, and an additional component may be included in the source driver 130.

The shift register 131 may sample the data DATA in response to a horizontal synchronization signal Hysnc, and may provide sampled image data LD1, . . . , and LDk to the amplifier areas 132a, 132b, . . . , and 132h. The data DATA may include a plurality of source data corresponding to the source lines SL, and each of the source data may include a plurality of bits. The shift register 131 may generate image data LD1, . . . , and LDK having a plurality of bits by sampling each of the bits of the data DATA. The horizontal synchronization signal Hsync may be a signal having a predetermined period, and may be a signal that determines a scan period of the pixels PX connected to the respective gate lines GL.

Each of the amplifier areas 132a, 132b, . . . , and 132h may include a level shifter 132, a digital-to-analog converter DAC, and an amplifier 135. Hereinafter, a description will be made with reference to the amplifier area 132a that outputs a data signal S1.

The level shifter 133 may level-shift the image data LD1. The level shifter 133 may receive the image data LD1 at a low voltage level and output decoded image data HD1 at a high voltage level to the DAC 134. In some implementations, the image data LD1 may include a plurality of bits, and the level shifter 133 may generate the decoded image data HD1 having a plurality of bits by level shifting the bits of the image data LD1. The level shifter 133 may receive the digital signal LD1 to provide the DAC 134 with the decoded image data HD1 having a level that has been shifted to swing between target voltage levels.

In some implementations, the level shifter 133 may control an output bias current of the decoded image data HD1 based on a bias control signal IB. As the output bias current is controlled, a slew rate of the decoded image data HD1 may be controlled. In some implementations, the level shifter 133 may control output bias currents of the bits of the decoded image data HD1 to have a same magnitude or different magnitudes. For example, the level shifter 133 may control an output bias current of a first bit of the decoded image data HD1 and an output bias current of a second bit, which is higher than the first bit, to a first level. Alternatively, the level shifter 133 may control the output bias current of the first bit of the decoded image data HD1 to the first level, and may control the output bias current of the second bit, which is higher than the first bit, to a second level higher than the first level. In some implementations, the level shifter 133 may control the output bias current of at least one bit among the bits of the decoded image data HD1. For example, the level shifter 133 may control the output bias current of the bits excluding an MSB. In some implementations, the level shifters 133 included in the amplifier areas 132a, 132b, . . . , and 132h may jointly control the output bias current of the same bit based on the bias control signal IB. That is, the level shifters 133 included in the amplifier areas 132a, 132b, . . . , and 132h and outputting the first bit among the bits of the decoded image data HD1 may receive the same bias control signal IB. The level shifters 133 that output the first bit may control the output bias current of the first bit of the decoded image data HD1 to a same value.

The DAC 134 may output an analog signal AD1 corresponding to the decoded video data HD1. The DAC 134 may receive a plurality of gamma voltages GV along with the decoded video data HD1. The gamma voltages GV may be provided by a gamma voltage generator 138. The DAC 134 may select at least some of the gamma voltages GV from among the gamma voltages GV based on the decoded image data HD1 to transfer it as an input voltage to the amplifier 135 through an output port.

The amplifier 135 may output the input voltage transferred from the DAC 134 as a data signal Si to a pixel connected to the corresponding source line.

The bias circuit 136 may supply the bias control signal IB to the level shifters 133 of the amplifier areas 132a, 132b, . . . , and 132h. The bias circuit 136 may output the bias control signal IB and/or may control a magnitude of the bias control signal IB, based on a bias start signal CI included in the source driver control signal CONT2. In some implementations, the bias circuit 136 may include one-time programmable (OTP) memory 137. The bias circuit 136 may control the magnitude of the bias control signal IB by referring to data stored in the OTP memory 137. For example, if the bias start signal CI is inputted, the bias circuit 136, which outputs a bias control signal IB of a first level, may output a bias control signal IB of a second level that is different from the first level by referring to data stored in the OTP memory 137. That is, the bias circuit 136 may perform bias trimming with reference to data stored in the OTP memory 137. In some implementations, data stored in OTP memory 137 may have different values for each source driver 130. That is, source drivers 130 manufactured through a same process may store different values in the OTP memory 137 according to an on chip variation (OCV).

The gamma voltage generator 138 may determine a number of the gamma voltages GV based on a number of the bits of the decoded image data HD1, and may determine a magnitude of each of the gamma voltages GV based on operating conditions of the display device 100, settings of a gamma voltage register, or the like. In some implementations, the number of the gamma voltages GV may be determined according to a number of bits of image data. For example, if the decoded video data HD1 is 8-bit data, the number of the gamma voltages GV may be 28 or less, and if the decoded video data HD1 is 10-bit data, the number of the gamma voltages GV may be 210 or less. That is, if the decoded image data HD1 is data having n bits, the gamma voltages GV may have 2n different magnitudes. The gamma voltage generator 138 may determine the magnitude of each of the gamma voltages GV by selecting at least some of a plurality of reference voltages.

The timing controller 140 may receive an image signal IS and a driving control signal CTRL from a host device, and may control the gate driver 120 and the source driver 130. Herein, the host device may be a computing device or system that controls the display device 100 to display an image desired by a user on the pixel array 110 from an outside. The driving control signal CTRL provided from the host device may include control commands for controlling the gate driver 120 and the source driver 130, setting data, etc. The timing controller 140 may control the gate driver 120 and the source driver 130 based on the driving control signal CTRL. For example, the driving control signal CTRL may include a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, a main clock signal MCLK, and a data enable signal DE. The timing controller 140 may divide image data IS in units of one frame based on the vertical synchronization signal VSYNC, and may generate data DATA by dividing the image data IS in units of the gate lines GL based on the horizontal synchronization signal HSYNC. The timing controller 140 may perform control to synchronize operations of the source driver 130 and the gate driver 120 by transmitting the gate driver control signal CONT1 and the source driver control signal CONT2 to the gate driver 120 and source driver 130, respectively,

The pixel array 110 and the gate driver 120 may be implemented on a same substrate, and the source driver 130 and the timing controller 140 may be configured as a single chip. In some implementations, the pixel array 110, the gate driver 120, the source driver 130, and the timing controller 140 may be implemented on a same substrate. In some implementations, the gate driver 120, source driver 130, and the timing controller 140 may be configured as a single chip. The gate driver 120 may be implemented as a separate semiconductor die, chip, or module to be connected to the pixel array 110. Additionally, a portion of the gate driver 120 may be positioned on a substrate where the pixel array 110 is positioned, and a remaining portion may be included in a separate chip.

FIG. 2 illustrates some components of an example of a source driver.

Referring to FIG. 2, one level shifter 210 and one DAC 220 corresponding to one source line are shown. The level shifter 210 receives 3-bit image data LD [2:0], and outputs 3-bit decoded image data HD [2:0] A and HD [2:0] B. The DAC 220 receives 3-bit decoded image data HD [2:0] A and HD [2:0] B, and outputs 23 (=8) gamma voltages GV0, . . . , and GV7 as an analog signal AD based on the 3-bit decoded image data HD [2:0] A and HD [2:0] B. Hereinafter, an example of outputting an analog signal AD based on 3-bit image data LD [2:0] will be described, but the present disclosure is applicable even when outputting an analog signal based on n-bit image data and is not limited to an example below. For example, in FIG. 14, a level shifter that receives 5-bit image data and outputs 5 bits of decoded image data will be described. 5 bits of decoded image data will be used to select one of 25 (=32) gamma voltages as an analog signal.

The level shifter 210 may be connected to the DAC 220, and may output decoded image data HD [2:0] A and HD [2:0] B to the DAC 220. The level shifter 210 may include a plurality of level shifting circuits 211a, 211b, and 211c and a plurality of buffers 212a, 212b, and 212c.

The level shifting circuits 211a, 211b, and 211c may receive image data LD [3:0], may level-shift the image data LD [3:0] to a first voltage VM or a second voltage VL, and may supply the level-shifted data MD [2:0] to the buffers 212a, 212b, and 212c.

The buffers 212a, 212b, and 212c receive data MD [2:0], may level-shift data MD [2:0] to a third voltage VDD or a fourth voltage VSS, and may output level-shifted decoded image data HD [2:0] A and HD [2:0] B. The buffers 212a, 212b, and 212c may output decoded image data HD [2:0] A obtained by inverting data MD [2:0] and decode image data HD [2:0] B obtained by inverting decode image data HD [2:0] A

The buffers 212a, 212b, and 212c may respectively output upper bits HD [2] A and HD [2] B, middle bits HD [1] A and HD [1] B, and lower bits HD [0] A and HD [0] B.

The DAC 220 may output one of a plurality of gamma voltages GV0, . . . , and GV7 as an analog signal AD based on the input decoded video data HD [2:0] A and HD [2:0] B

The DAC 220 may include a plurality of stages STA2, STA1, and STA0. The stages STA2, STA1, and STA0 may respectively input upper bits HD [2] A and HD [2] B, middle bits HD [1] A and HD [1] B, and lower bits HD [0] A and HD [0] B. An output terminal of each of the stages STA2, STA1, and STA0 may be connected to an input terminal of a next stage. For example, the output terminal of the stage STA2 may be connected to the input terminal of the next stage STA1.

The stage STA2 that receives the upper bits HD [2] A and HD [2] B may include 22 decoders 221a that receive 23 gamma voltages GV0, . . . , and GV7. The decoders 221a may receive two gamma voltages GV0 and GV7, GV2 and GV5, GV1 and GV6, or GV3 and GV4, and may output one gamma voltage according to a bit HD [2] of the decoded image data. The decoders 221a may include a P-type decoder 223a and an N-type decoder 222a. A bit HD [2] A of the decoded image data is provided to a gate of a transistor included in the P-type decoder 223a, and a bit HD [2] B of the decoded image data may be provided to a gate of a transistor included in the N-type decoder 222a. At least one of the P-type decoder 223a and the N-type decoder 222a included in the same decoder 221a may output one of the two input gamma voltages GV0 and GV7, GV2 and GV5, GV1 and GV6, or GV3 and GV4.

The stage STA1, which receives the middle bits HD [1] A and HD [1] B, may include 21 decoders 221b that receive 22 gamma voltages outputted from the previous stage STA2. The decoders 221b may receive two gamma voltages, and may output one gamma voltage according to a bit HD [1] of the decoded image data. The decoders 221b may include a P-type decoder 223b and an N-type decoder 222b. A bit HD [1] A of the decoded image data is provided to a gate of a transistor included in the P-type decoder 223b, and a bit HD [1] B of the decoded image data may be provided to a gate of a transistor included in the N-type decoder 222b.

The stage STA0, which receives the lower bits HD [0] A and HD [0] B, may include 20 decoders 221c that receive 21 gamma voltages outputted from the previous stage STA1. The decoders 221c may receive two gamma voltages, and may output one gamma voltage according to a bit HD [0] of the decoded image data. The decoders 221c may include a P-type decoder 223c and an N-type decoder 222b. A bit HD [0] A of the decoded image data may be provided to a gate of a transistor included in the P-type decoder 223c, and a bit HD [0] B of the decoded image data may be provided to a gate of a transistor included in the N-type decoder 222c.

The level shifting circuits 211a, 211b, and 211c and the buffers 212a, 212b, and 212c will be described with reference to FIG. 3.

FIG. 3 illustrates a circuit diagram schematically showing a buffer and a level shifting circuit of an example of a source driver.

Referring to FIG. 3, the level shifting circuit 310 includes a cross-coupled inverter, and the cross-coupled inverter includes transistors T1 and T2 connected in series between the first voltage VM and the second voltage VL, and transistors T3 and T4 connected in series between the first voltage VM and the second voltage VL.

The buffer 320 may include 2-stage inverters 321a and 321b. The first stage inverter 321a may include transistors PT1 and NT1 connected in series between the third voltage VDD and the fourth voltage VSS, and the second stage inverter 321b may include transistors PT2 and NT2 connected in series between the third voltage VDD and the fourth voltage VSS. An input terminal of the first stage inverter 321a may be connected to the output terminal OUT1 of the level shifting circuit 310. An output terminal OUT2 may be connected to a gate of a transistor of the P-type decoder 223a included in the decoder 221a. An input terminal of the second stage inverter 321b may be connected to the output terminal OUT2 of the first stage inverter 321a.

A bit MD [2] A inverted and amplified by the level shifting circuit 310 may be inputted to the input terminal of the first stage inverter 321a. The bit HD [2] A in which the bit MD [2] A is inverted and the amplified may be outputted from the output terminal OUT2 of the first stage inverter 321a.

The bit HD [2] A inverted and amplified by the first stage inverter 321a may be inputted to the input terminal of the second stage inverter 321b. The bit HD [2] A in which the bit HD [2] A is inverted and the amplified may be outputted from the output terminal OUT3 of the second stage inverter 321b. An output terminal OUT3 may be connected to a gate of a transistor of the N-type decoder 222a included in the decoder 221a. If the bit LD [2] A of the image data transitions from the first level V1 to the second level V2, the bit MD [2] A may transition from a first voltage VM to a second voltage VL. Then, a transistor PT1 of the first stage inverter 321a may be turned on, and in order to charge an input capacitor C1 of a gate of a transistor of the P-type decoder 223a, a charging current IC may flow from the third voltage VDD to the input capacitor C1 through the transistor PT1. As the input capacitor C1 is charged, the bit HD [2] A may transition from the fourth voltage VSS to the third voltage VDD. Then, a transistor NT2 of the second stage inverter 321b may be turned on, and in order to discharge an input capacitor C2 of a gate of a transistor of the N-type decoder 222a, a discharge current ID may flow from the input capacitor C2 to the fourth voltage VSS through the transistor NT2. As the input capacitor C2 is discharged, the bit HD [2] B may transition from the third voltage VDD to the fourth voltage VSS.

The bit HD [2] A of the decoded image data may be provided to gates of transistors of four P-type decoders 223a, a bit HD [1] A of the decoded image data may be provided to gates of transistors of the two P-type decoders 223b, and a bit HD [0] A of the decoded image data may be provided to a gate of a transistor of one P-type decoder 223c. Accordingly, a time for charging four input capacitors C1 to which the bit HD [2] A of the decoded image data is applied is the longest. The bit HD [2] B of the decoded image data may be provided to gates of transistors of four N-type decoders 222a, a bit HD [1] B of the decoded image data may be provided to gates of transistors of the two N-type decoders 222b, and a bit HD [0] B of the decoded image data may be provided to a gate of a transistor of one N-type decoder 222c. Accordingly, a time for discharging four input capacitors C2 to which the bit HD [2] B of the decoded image data is applied is the longest. Accordingly, a timing of outputting the analog signal AD may be determined by a timing at which the bits HD [2] A and HD [2] B of the decoded image data transition. In addition, a period between timings at which the bits HD [1] A and HD [1] B and the bits HD [0] A and HD [0] B of the decoded image data transition where a difference in absolute amounts of input capacitance loads is relatively small may be shorter than a period between timings at which the bits HD [2] A and HD [2] B and the bits HD [1] A and HD [1] B of the decoded image data transition. A period between timings at which the bit HD [1] B and the bit HD [0] B transition are relatively short, and thus around bouncing, in which the fourth voltage VSS temporarily increases, may occur due to the discharge current ID. This will be described with reference to FIG. 4.

FIG. 4 illustrates a graph showing an output voltage and a discharging current of an example of a level shifter.

As illustrated in FIG. 4, the bits HD [0:2] B transitions from the third voltage VDD to the fourth voltage VSS at a time point t1. The transition of the bit HD [2] B is completed at a time point t2 after the transition of the bit HD [1] B and the bit HD [0] B is completed. Accordingly, the analog signal AD outputted from the DAC 220 depends on the bit HD [2] B with a lowest slew rate.

A period between the timings at which the bit HD [1] B and the bit HD [0] B transition is short compared to a period between the timings at which the bit HD [2] B and the bit HD [1] B transition, and thus discharge currents ID [1] and ID [0] may be generated within a relatively close time. All discharge currents ID [1] and ID [0] flow in a wire that applies the fourth voltage VSS, a maximum value MC of a total discharge current IDG0 flowing in the wire applying the fourth voltage VSS may exceed a reference value TLC. The fourth voltage VSS may temporarily increase due to the total discharge current IDG0 exceeding the reference value TLC. That is, ground bouncing may occur due to the total discharge current IDG0. This affects the buffers 212a, 212b, and 212c that receive the same fourth voltage VSS, and may also cause noise due to coupling in interfaces physically adjacent to the wire that supplies the fourth voltage VSS.

In some implementations, the buffers 212a, 212b, and 212c may control output bias currents of the decoded image data HD [2:0] A and HD [2:0] B based on a same bias control signal IB. This will be described with reference to FIG. 5.

FIG. 5 illustrates a circuit diagram for recovery of an example of a level shifter.

Referring to FIG. 5, a plurality of buffers 510a, 510b, and 510c output the decoded image data HD [2:0] A and HD [2:0] B. The buffers 510a, 510b, and 510c each include a 2-stage inverter 511a and 511b, 512a and 512b, and 513a and 513b. The buffer 510a outputs the upper bits HD [2] A and HD [2] B of the decoded image data, the buffer 510b outputs the middle bits HD [1] A and HD [1] B of the decoded image data, and the buffer 510c outputs the lower bits HD [0] A and HD [0] B of the decoded image data.

An input terminal of the first stage inverter (511a/512a/513a) may be connected to an output terminal of the level shifting circuit (211a/211b/211c in FIG. 2). An output terminal OUTa of the first stage inverter (511a/512a/513a) may be connected to a gate of a transistor of the P-type decoder (223a/223b/223c). Each of the first stage inverters 511a, 512a, and 513a may include transistors PT1 and NT1 connected in series between the third voltage VDD and the fourth voltage VSS.

The input terminal of the second stage inverter (511b/512b/513b) may be connected to the output terminal OUTa of the first stage inverter (511a/512a/513a). An output terminal OUTb of the second stage inverter (511b/512b/513b) may be connected to a gate of a transistor of the N-type decoder (222a/222b/222c). Each of the second stage inverters 511b, 512b, and 513b may include transistors PT2, NT2, and BTOa/BTOb/BTOc connected in series between the third voltage VDD and the fourth voltage VSS. For example, the transistors PT2 and NT2 may be connected in an inverter structure, gates of transistors PT2 and NT2 may be connected to the output terminal OUTa of the first stage inverter (511a/512a/513a), and drains of transistors PT2 and NT2 may be connected to the output terminal OUTb. The bias transistors (BTOa/BTOb/BTOc) may be connected between a source of the transistor NT2 and the fourth voltage VSS. A bias transistor (BTOa/BTOb/BTOc), which is an amplifier area including the buffers 510a, 510b, and 510c, may be positioned in an amplifier area corresponding to one source line SL. Additionally, the bias transistor (BTOa/BTOb/BTOc) may be positioned between an amplifier area including the buffers 510a, 510b, and 510c and an amplifier area adjacent to the amplifier area. This will be described later in FIG. 13.

In some implementations, the bias transistor (BTOa/BTOb/BTOc) may be positioned on a path that discharges an input capacitor of a transistor of the N-type decoder (222a/222b/222c in FIG. 2). The bias control signal IB may be inputted to a gate of the bias transistor (BTOa/BTOb/BTOc). The bias transistor (BTOa/BTOb/BTOc) may limit a discharge current (ID [2]/ID [1]/ID [0]) based on a voltage level of the bias control signal IB. This will be described with reference to FIG. 6.

FIG. 6 illustrates a graph showing an output voltage and a discharging current of another example of a level shifter.

In FIG. 6, a dotted line represents an output voltage and a discharge current of a level shifter in FIG. 4, and a solid line represents an output voltage and a discharge current of a level shifter. As illustrated in FIG. 6, the bits HD [0:2] B transition from the third voltage VDD to the fourth voltage VSS at a time point t11. The transition of the bit HD [2] B is completed at a time point t12 after the transition of the bit HD [1] B and the bit HD [0] B is completed. Accordingly, the analog signal AD outputted from the DAC 220 (FIG. 2) is dependent on the bit HD [2] B with a lowest slew rate. A time point t12 is later than the time t2, which is a transition completion timing of the bit HD [2] B in FIG. 4 due to a limitation of the discharge current ID [2] by the bias transistor BTOa,

Due to limitations of the discharge currents ID [2], ID [1], and ID [0], slew rates of the bit HD [2] B, the bit HD [1] B, and the bit HD [0] B may be lower compared to the implementation of FIG. 4. As the slew rate of the bit HD [2] B, the bit HD [1] B, and the bit HD [0] B decreases, a difference between a period between timings at which the bit HD [1] B and the bit HD [0] B transition and a period between timings at which the bits HD [2] B and the bits HD [1] B transition may become smaller. That is, a maximum value MC0 of the total discharge current IDG1 flowing through the wire applying the fourth voltage VSS may be less than or equal to the reference value TLC by limiting amounts of discharge currents D [2], ID [1], and ID [0],

Accordingly, ground bouncing due to the total discharge current IDG1 may be reduced. This may reduce an impact on the buffers 510a, 510b, and 510c that receive the same fourth voltage VSS and a noise caused to an interface that is physically adjacent to the wire that supplies the fourth voltage VSS.

FIG. 7 illustrates a block diagram showing an example of a level shifter.

Referring to FIG. 7, the level shifter 700 receives 3-bit image data LD [2:0], and outputs 3-bit decoded image data HD [2:0] A and HD [2:0] B. The level shifter 700 is connected to the DAC 220 (FIG. 2), and outputs decoded image data HD [2:0] A and HD [2:0] B to the DAC 220. The level shifter 700 includes a plurality of level shifting circuits 711a, 711b, and 711c and a plurality of buffers 712a, 712b, and 712c.

The level shifting circuits 711a, 711b, and 711c may receive image data LD [3:0], may level-shift the image data LD [3:0] to a first voltage VM or a second voltage VL, and may supply the level-shifted data MD [2:0] to the buffers 712a, 712b, and 712c.

The buffers 712a, 712b, and 712c receive data MD [2:0], may level-shift data MD [2:0] to a third voltage VDD or a fourth voltage VSS, and may output level-shifted decoded image data HD [2:0] A and HD [2:0] B. The buffers 712a, 712b, and 712c may output decoded image data HD [2:0] A obtained by inverting data MD [2:0] and decode image data HD [2:0] B obtained by inverting decode image data HD [2:0] A. The buffers 712a, 712b, and 712c may respectively output upper bits HD [2] A and HD [2] B, middle bits HD [1] A and HD [1] B, and lower bits HD [0] A and HD [0] B.

In some implementations, the buffers 712b and 712c may control an output bias current of some bits HD [1:0] of the decoded image data based on the same bias control signal IB. The bias control signal IB may not be applied to the buffer 712a that outputs the upper bit HD [2]. This will be described with reference to FIG. 8.

FIG. 8 illustrates a circuit diagram for recovery of another example of a level shifter.

Referring to FIG. 8, a plurality of buffers 810a, 810b, and 810c output the decoded image data HD [2:0] A and HD [2:0] B. A description of the buffers 810a, 810b, and 810c that are the same or similar to the description of the buffers 510a, 510b, and 510c illustrated in FIG. 5 will be omitted.

Among the second stage inverters 811b, 812b, and 813b, the second stage inverters 812b and 813b which receive some bits of data MD [1:0] may include transistors PT2, NT2, and BTOb/BTOc connected in series between the third voltage VDD and the fourth voltage VSS. In some implementations, some bits MD [1:0] may be bits excluding the upper bit MD [2]. For example, the transistors PT2 and NT2 may be connected in an inverter structure, gates of transistors PT2 and NT2 may be connected to the output terminal OUTa of the first stage inverter (812a/813a), and drains of transistors PT2 and NT2 may be connected to the output terminal OUTb. The bias transistor (BTOb/BTOc) may be connected between a source of the transistor NT2 and the fourth voltage VSS. In some implementations, the bias transistor (BTOb/BTOc) may be positioned on a path that discharges an input capacitor of a transistor of the N-type decoder (222b/222c in FIG. 2). The bias control signal IB may be inputted to a gate of the bias transistor (BTOb/BTOc). The bias transistor (BTOb/BTOc) may limit a discharge current (ID [1]/ID [0]) based on a voltage level of the bias control signal IB. This will be described with reference to FIG. 9.

FIG. 9 illustrates a graph showing an output voltage and a discharging current of another example of a level shifter.

In FIG. 9, a dotted line represents an output voltage and a discharge current of a level shifter in FIG. 4, and a solid line represents an output voltage and a discharge current of a level shifter. As illustrated in FIG. 9, the bits HD [0:2] B transition from the third voltage VDD to the fourth voltage VSS at a time point t21. The transition of the bit HD [2] B is completed at a time point t22 after the transition of the bit HD [1] B and the bit HD [0] B is completed. Accordingly, the analog signal AD outputted from the DAC 220 (FIG. 2) is dependent on the bit (HD [2] B) with a lowest slew rate. Since the discharge current ID [2] is not limited, a time point t22 may be substantially the same as the time point t2, which is a transition completion timing of the bit HD [2] B in FIG. 4.

The discharge currents ID [1] and ID [0] may be limited to a same current amount LC. Due to limitations of the discharge currents ID [1] and ID [0], slew rates of the bit HD [1] B and the bit HD [0] B may be lower compared to the implementation of FIG. 4. A maximum value MC1 of the total discharge current IDG2 flowing through the wire applying the fourth voltage VSS may be less than or equal to the reference value TLC by limiting amounts of discharge currents ID [1] and ID [0],

Accordingly, ground bouncing due to the total discharge current IDG2 may be reduced. This may reduce an impact on the buffers 810a, 810b, and 810c that receive the same fourth voltage VSS and a noise caused to an interface that is physically adjacent to the wire that supplies the fourth voltage VSS.

FIG. 10 illustrates a block diagram showing another example of a level shifter.

Referring to FIG. 10, the level shifter 1000 receives 3-bit image data LD [2:0], and outputs 3-bit decoded image data HD [2:0] A and HD [2:0] B. The level shifter 1000 is connected to the DAC 220 (FIG. 2), and outputs decoded image data HD [2:0] A and HD [2:0] B to the DAC 220. A description of the level shifter 1000 that is the same or similar to the description of the level shifter 700 illustrated in FIG. 7 will be omitted.

In some implementations, the buffers 1012b and 1012c may control an output bias current of some bits HD [1:0] of the decoded image data based on different bias control signals IB1 and IB0. The bias control signal IB1 and IB0 may not be applied to the buffer 1012a that outputs the upper bit HD [2]. This will be described with reference to FIG. 11.

FIG. 11 illustrates a circuit diagram for recovery of another example of a level shifter.

Referring to FIG. 11, a plurality of buffers 1110a, 1110b, and 1110c output decoded image data HD [2:0] A and HD [2:0] B. A description of the buffers 1110a, 1110b, and 1110c that are the same or similar to the description of the buffers 510a, 510b, and 510c illustrated in FIG. 5 will be omitted.

Among the second stage inverters 1111b, 1112b, and 1113b, the second stage inverters 112b and 113b which receive some bits of data MD [1:0] may include transistors PT2, NT2, and BTOb/BTOc connected in series between the third voltage VDD fourth voltage VSS. In some implementations, some bits MD [1:0] may be bits excluding the upper bit MD [2]. For example, the transistors PT2 and NT2 may be connected in an inverter structure, gates of transistors PT2 and NT2 may be connected to the output terminal OUTa of the first stage inverter (1112a/1113a), and drains of transistors PT2 and NT2 may be connected to the output terminal OUTb. The bias transistor (BTOb/BTOc) may be connected between a source of the transistor NT2 and the fourth voltage VSS. In some implementations, the bias transistor (BTOb/BTOc) may be positioned on a path that discharges an input capacitor of a transistor of the N-type decoder (222b/222c in FIG. 2). The bias control signal IB1 may be inputted to a gate of the bias transistor BTOb. The bias control signal IB0 may be inputted to a gate of the bias transistor BTOc. The bias transistor (BTOb/BTOc) may limit a discharge current (ID [1]/ID [0]) based on a voltage level of the bias control signal (IB1/IB0). In some implementations, the discharge current ID [0] flowing in the second stage inverter 1113b that outputs the lower bit HD [0] B may be more limited compared to the discharge current ID [1] flowing in the second stage inverter 1112b that outputs the middle bit HD [1] B. For example, a voltage level of the bias control signal IB0 may be lower than a voltage level of the bias control signal IB1. This will be described with reference to FIG. 12.

FIG. 12 illustrates a graph showing an output voltage and a discharging current of another example of a level shifter.

In FIG. 12, a dotted line represents an output voltage and a discharge current of a level shifter in FIG. 4, and a solid line represents an output voltage and a discharge current of a level shifter. As illustrated in FIG. 12, the bits HD [0:2] B transition from the third voltage VDD to the fourth voltage VSS at a time point t31. The transition of the bit HD [2] B is completed at a time point t32 after the transition of the bit HD [1] B and the bit HD [0] B is completed. Accordingly, the analog signal AD outputted from the DAC 220 (FIG. 2) is dependent on the bit HD [2] B with a lowest slew rate. Since the discharge current ID [2] is not limited, a time point t32 may be substantially the same as the time point t2, which is a transition completion timing of the bit HD [2] B in FIG. 4.

The discharge currents ID [1] and ID [0] may be limited to different current amounts LC1 and LC0. Due to limitations of the discharge currents ID [1] and ID [0], slew rates of the bit HD [1] B and the bit HD [0] B may be lower compared to the implementation of FIG. 4. In addition, due to a limitation in the discharge current ID [0], a slew rate of the bit HD [0] B may be lower compared to the implementation of FIG. 9. Since capacity of an input capacitor of a transistor connected to the output terminal OUTb of inverter 1113b that outputs the lower bit HD [0] B is smaller than capacity of an input capacitor of a transistor connected to the output terminal OUTb of inverter 1112b, which outputs the middle bit HD [1] B, the discharge current ID [0] may be limited to a smaller current amount than that of the discharge current ID [1]. A maximum value MC1 of the total discharge current IDG2 flowing through the wire applying the fourth voltage VSS may be less than or equal to the reference value TLC by limiting amounts of discharge currents ID [1] and ID [0],

Accordingly, ground bouncing due to the total discharge current IDG2 may be reduced. This may reduce an impact on the buffers 1110a, 1110b, and 1110c that receive the same fourth voltage VSS and a noise caused to an interface that is physically adjacent to the wire that supplies the fourth voltage VSS.

FIG. 13 illustrates a block diagram showing another example of a level shifter.

As illustrated in FIG. 13, a plurality of level shifters 1310 and 1320 are included in different amplifier areas (132a, 132b, . . . , and 132h in FIG. 1). Each of the level shifters 1310 and 1320 is connected to a different source line SL. Each of the level shifters 1310 and 1320 receives 3-bit image data (LD1 [2:0]/LD2 [2:0]), and outputs 3-bit decoded image data HD1 [2:0] A, HD1 [2:0] B/HD2 [2:0] A, HD2 [2:0] B. Each of the level shifters 1310 and 1320 is connected to the DAC 220 (FIG. 2), and outputs decode image data HD1 [2:0] A, HD1 [2:0] B/HD2 [2:0] A, HD2 [2:0] B to the DAC 220. A description of the level shifter 1300 that is the same or similar to the description of the level shifter 700 illustrated in FIG. 7 will be omitted.

At least one bias transistor BT2b and BT2c may be positioned in an area 1330 between the level shifters 1310 and 1320. For example, at least one bias transistor BT2b and BT2c may be positioned in the area 1330 between two adjacent level shifters 1310 and 1320. In some implementations, the area 1330 between the level shifters 1310 and 1320 may be an area where a repeater is positioned to transmit a signal from one amplifier area to another amplifier area. For example, a repeater may be positioned to performing amplification, inverting, and/or buffering so that a signal applied to a first group including the level shifter 1310 may also be applied to a second group including level shifter 1320 in the area 1330 between the first group and the second group. At least one bias transistor (BT2b, BT2c) connected to the first group including the level shifter 1310 and the second group including the level shifter 1320 may be located in the area 1330 where the repeater is positioned.

A first end of the bias transistor (BT2b/BT2c) may be connected to the corresponding buffer 1312b, 1322b/1312c, and 1322c. A second end of the bias transistor (BT2b/BT2c) may be connected to the fourth voltage VSS. The bias control signal (IB1/IB0) may be inputted to a gate of the bias transistor (BT2b/BT2c). For example, the bias control signal IB1, which controls the discharge current for outputting the middle bit HD [1] B, may be applied to the buffers 1312b and 1322b, and the bias control signal IB0, which controls the discharge current for outputting the lower bit HD [0] B, may be applied to the buffers 1312c and 1322c. The buffers 1312 and 1312c and the buffers 1322b and 1322c may be included in different level shifters 1310 and 1320. That is, buffers included in different level shifters 1310 and 1320 and for outputting same bits may be connected to a same bias transistor. The bias transistors (BTOb/BTOc) may limit a discharge current of the buffers 1312b, 1322b/1312c, and 1322c based on a voltage level of the bias control signal (IB1/IB0). That is, an output bias current of some bits HD [1] of decoded image data may be controlled by the same bias transistor BT2b. An output bias current of some bits HD [1] of decoded image data may be controlled by the same bias transistor BT2c. A bias transistor may not be connected to the buffers 1312a and 1322a that output the upper bits HD1 [2] B and HD2 [2] B.

FIG. 14 illustrates a block diagram showing another example of a level shifter.

Referring to FIG. 14, the level shifter 1400 receives 5-bit image data LD [4:0]), and outputs 5-bit decoded image data HD [4:0] A and HD [4:0] B. The level shifter 1400 is connected to the DAC 220 (FIG. 2), and outputs decoded image data HD [4:0] A and HD [4:0] B to the DAC 220. A description of the level shifter 1400 that is the same or similar to the description of the level shifter 700 illustrated in FIG. 7 will be omitted.

In some implementations, a plurality of buffers 1412a, . . . , and 1412e may be grouped into a plurality of groups. The groups may include buffers that output adjacent bits. For example, the buffers 1412b and 1412c included in a first group may output bits HD [3:2]), and the buffers 1412d and 1412e included in a second group may output bits HD [1:0].

The different bias control signals IB1 and IB0 may be applied to the buffers 1412b and 1412c included in the first group and the buffers 1412d and 1412e included in the second group. The buffers 1412b and 1412c included in the first group may control an output bias current of some bits HD [3:2] of the decoded image data based on the same bias control signal IB0. The buffers 1412d and 1412e included in the second group may control an output bias current of some bits HD [1:0] of the decoded image data based on the same bias control signal IB0. For example, the bias control signal IB1 applied to the buffers 1412b and 1412c included in the first group corresponding to upper bits may have a higher voltage level than that of the bias control signal IB0 applied to the buffers 1412d and 1412e included in the second group corresponding to lower bits. Accordingly, an output bias current of the buffers 1412b and 1412c included in the first group may be greater than an output bias current of the buffers 1412d and 1412e included in the second group. The bias control signal IB1 and IB0 not be applied to the buffer 1412a that outputs the upper bit HD [4].

FIG. 15 illustrates a circuit diagram for recovery of another example of a level shifter.

Referring to FIG. 15, a plurality of buffers 1510a, 1510b, and 1510c output decoded image data HD [2:0] A and HD [2:0] B. A description of the buffers 1510a, 1510b, and 1510c that are the same or similar to the description of the buffers 510a, 510b, and 510c illustrated in FIG. 5 will be omitted.

Each of the first stage inverters 1511a, 1512a, and 1513a may include transistors PT1 and NT1 connected in series between the third voltage VDD fourth voltage VSS.

The input terminal of the second stage inverter (1511b/1512b/1513b) may be connected to the output terminal OUTa of the first stage inverter (1511a/1512a/1513a). An output terminal OUTb of the second stage inverter (1511b/1512b/1513b) may be connected to a gate of a transistor of the N-type decoder (222a/222b/222c). Each of the second stage inverters 1511b, 1512b, and 1513b may include transistors PT2 and NT2 connected in series between the third voltage VDD and the fourth voltage VSS.

A size (W/L) of the transistors PT2 and NT2 included in the inverters 1512b and 1513b that output remaining bits may be smaller than a size (W/L) of the transistors PT2 and NT2 included in the inverter 1511b that outputs an upper bit. Accordingly, sizes of the discharge currents ID [1] and ID [0] may be smaller compared to the discharge current ID [2].

In addition, a size (W/L) of the transistors PT2 and NT2 included in the inverter 1513b that outputs a lower bit may be smaller than a size (W/L) of the transistors PT2 and NT2 included in the inverters 1511b and 1512b that output remaining bits. Accordingly, a size of the discharge current ID [0] of the inverter 1513b that outputs the lower bit ID [0] may be the smallest. Accordingly, ground bouncing due to a total discharge current of the second stage inverters 1511b, 1512b, and 1513b may be reduced. This may reduce an impact on the buffers 1510a, 1510b, and 1510c that receive the same fourth voltage VSS and a noise caused to an interface that is physically adjacent to the wire that supplies the fourth voltage VSS.

In some implementations, each of the inverters 1511b, 1512b, and 1513b may further include a bias transistor. Accordingly, the inverters 1511b, 1512b, and 1513b may control discharge currents ID [2:0] by a bias control signal in addition to the size (W/L) of the transistor.

FIG. 16 illustrates a circuit diagram schematically showing a buffer and a level shifting circuit of another example of a source driver.

Referring to FIG. 16, the level shifting circuit 1610 includes a cross-coupled inverter, and the cross-coupled inverter includes transistors T1 and T2 connected in series between the first voltage VM and the second voltage VL, and transistors T3 and T4 connected in series between the first voltage VM and the second voltage VL. The buffer 1620 includes a two-stage inverter 1621a and 1621b and a single-stage inverter 1621c.

Descriptions of the level shifting circuit 1610 and buffer 1620 that are the same as or similar to those of the level shifting circuit 310 and the buffer 320 illustrated in FIG. 3 will be omitted.

The buffer 1620 may include 2-stage inverters 1621a and 321b. The first stage inverter 1621a may include transistors PT1 and NT1 connected in series between the third voltage VDD fourth voltage VSS. An input terminal of the first stage inverter 1621a may be connected to the output terminal OUT1 of the level shifting circuit 1610. A bit MD [2] A inverted and amplified by the level shifting circuit 1610 may be inputted to the input terminal of the first stage inverter 1621a. The bit in which the bit MD [2] A is inverted and the amplified may be outputted from the output terminal OUT2 of the first stage inverter 1621a.

The second stage inverter 1621b may include transistors PT2, NT2, and BTB connected in series between the third voltage VDD and the fourth voltage VSS. For example, the transistors PT2 and NT2 may be connected in an inverter structure, gates of transistors PT2 and NT2 may be connected to the output terminal OUT2 of the first stage inverter 1621a, and drains of transistors PT2 and NT2 may be connected to the output terminal OUT3. A bias transistor BTB may be connected between a source of the transistor NT2 and the fourth voltage VSS. The bit HD [2] A inverted and amplified by the first stage inverter 1621a may be inputted to the input terminal of the second stage inverter 1621b. The bit HD [2] A in which the bit HD [2] A is inverted and the amplified may be outputted from the output terminal OUT3 of the second stage inverter 1621b. An output terminal OUT3 may be connected to a gate of a transistor of the N-type decoder 222a included in the decoder 221a (FIG. 2). In some implementations, the bias transistor BTB may be positioned on a path that discharges an input capacitor of a transistor of the N-type decoder 222a

The bias control signal IB may be inputted to a gate of the bias transistor BTB. The bias transistor BTB may limit a discharge current ID [1] B based on a voltage level of the bias control signal IB.

The single-stage inverter 1621c may include transistors PT3, NT3, and BTA connected in series between the third voltage VDD and the fourth voltage VSS. For example, transistors PT3 and NT3 may be connected in an inverter structure, gates of transistors PT3 and NT3 may be connected to the output terminal OUT1, and drains of transistors PT3 and NT3 may be connected to an output terminal OUT4. A bias transistor BTA may be connected between a source of the transistor NT3 and the fourth voltage VSS. A bit MD [2] A inverted and amplified by the level shifting circuit 1610 may be inputted to the input terminal of the single-stage inverter 1621c. The bit HD [2] A in which the bit MD [2] A is inverted and the amplified may be outputted from the output terminal OUT4 of the single-stage inverter 1621c. An output terminal OUT4 may be connected to a gate of a transistor of the N-type decoder 222a included in the decoder 221a. In some implementations, the bias transistor BTA may be positioned on a path that discharges an input capacitor of a transistor of the P-type decoder 223a

The bias control signal IB may be inputted to a gate of the bias transistor BTA. The bias transistor BTA may limit a discharge current ID [1] A based on a voltage level of the bias control signal IB.

Implementations described with reference to FIG. 5 to FIG. 15 may be applied to the buffer 1620 of FIG. 16.

FIG. 17 illustrates a circuit diagram schematically showing a buffer and a level shifting circuit of another example of a source driver.

Referring to FIG. 17, the level shifting circuit 1710 includes a cross-coupled inverter, and the cross-coupled inverter includes transistors T1 and T2 connected in series between the first voltage VM and the second voltage VL, and transistors T3 and T4 connected in series between the first voltage VM and the second voltage VL. A buffer 1720 includes single-stage inverters 1721a and 1721b.

Descriptions of the level shifting circuit 1710 and buffer 1720 that are the same as or similar to those of the level shifting circuit 310 and the buffer 320 illustrated in FIG. 3 will be omitted.

A bit LD [2] A of image data may be provided to a gate of the transistor T2, and a bit LD [2] B in which the bit LD [2] A is inverted may be provided to a gate of the transistor T4. The bit LD [2] B in which the bit LD [2] A of the image data is inverted and amplified may be outputted from an output terminal OUT1A. The bit LD [2] B in which the bit LD [2] B of the image data is inverted and amplified may be outputted from an output terminal OUT1B.

A buffer 1720 may include single-stage inverters 1721a and 1721b. The first stage inverter 1721a may include transistors PT1, NT1, and BTA connected in series between the third voltage VDD and the fourth voltage VSS. For example, the transistors PT1 and NT1 may be connected in an inverter structure, gates of transistors PT1 and NT1 may be connected to the output terminal OUT1A, and drains of transistors PT1 and NT1 may be connected to an output terminal OUT2. A bias transistor BTA may be connected between a source of the transistor NT1 and the fourth voltage VSS. A bit MD [2] A inverted and amplified by the level shifting circuit 1710 may be inputted to the input terminal of the single-stage inverter 1721a. The bit HD [2] A in which the bit MD [2] A is inverted and the amplified may be outputted from the output terminal OUT2 of the single-stage inverter 1721a. An output terminal OUT2 may be connected to a gate of a transistor of the N-type decoder 222a included in the decoder 221a (FIG. 2). In some implementations, the bias transistor BTA may be positioned on a path that discharges an input capacitor of a transistor of the P-type decoder 223a

The bias control signal IB may be inputted to a gate of the bias transistor BTA. The bias transistor BTA may limit a discharge current ID [1] A based on a voltage level of the bias control signal IB.

The second inverter 1721b may include transistors PT2, NT2, and BTB connected in series between the third voltage VDD and the fourth voltage VSS. For example, the transistors PT2 and NT2 may be connected in an inverter structure, gates of transistors PT2 and NT2 may be connected to the output terminal OUT1B, and drains of transistors PT2 and NT2 may be connected to an output terminal OUT3. A bias transistor BTB may be connected between a source of the transistor NT2 and the fourth voltage VSS. A bit MD [2] B inverted and amplified by the level shifting circuit 1710 may be inputted to the input terminal of the second inverter 1721b. The bit MD [2] B in which the bit HD [2] A is inverted and the amplified may be outputted from the output terminal OUT3 of the second inverter 1721b. An output terminal OUT3 may be connected to a gate of a transistor of the N-type decoder 222a included in the decoder 221a. In some implementations, the bias transistor BTB may be positioned on a path that discharges an input capacitor of a transistor of the N-type decoder 222a

The bias control signal IB may be inputted to a gate of the bias transistor BTB. The bias transistor BTB may limit a discharge current ID [1] B based on a voltage level of the bias control signal IB.

Implementation described with reference to FIG. 5 to FIG. 15 may be applied to the buffer 1720 of FIG. 17.

FIG. 18 illustrates a graph showing a simulation result of an output voltage and a discharging current of an example of a level shifter, and FIG. 19 illustrates a graph showing a simulation result of an output voltage and a discharging current of another example of a level shifter.

As illustrated in FIG. 18, bits 1810 and 1812 transition from the third voltage VDD to the fourth voltage VSS at a time point t1A. Transition of the uppermost bit 1812 is completed at a time point t2 after transition of the lower bits 1810 is completed.

The discharge current 1820 corresponding to the lower bits 1810 may have a maximum value at timings adjacent to each other while the transition of the lower bits 1810 is performed. Accordingly, a maximum value MC1 of a total discharge current 1830 may be formed while the lower bits 1810 are transitioning.

As illustrated in FIG. 19, bits 1910 and 1912 transition from the third voltage VDD to the fourth voltage VSS at a time point t1B. Transition of the uppermost bit 1912 is completed at a time point t2 after transition of the lower bits 1910 is completed.

Discharge currents 1920 and 1921 corresponding to the lower bits 1910 may be limited to different current amounts LC0 and LC1, respectively. The current amount is limited, and thus a slew rate of the bits 1910 may be lowered. In addition, a maximum value MC2 of a total discharge current 1930 flowing through the wire applying the fourth voltage VSS may be smaller than the maximum value MC1 by limiting amounts of discharge currents 1920 and 1921. Accordingly, in accordance with a display driving device, a source driver, and a display device including the same according to some implementations, ground bouncing due to the total discharge current 1930 may be reduced, and an impact of ground bouncing on adjacent circuits, modules, interfaces, etc. may be reduced.

FIG. 20 illustrates a view for describing an example of a display system.

Referring to FIG. 20, the display system 2000 includes a processor 2010, a memory 2020, a display device 2030, and a peripheral device 2040, which are electrically connected to a system bus 2050.

The processor 2010 may control input and output of data of the memory 2020, the display device 2030, and the peripheral device 2040, and may perform image processing of image data transmitted between the corresponding devices.

The memory 2020 may include a volatile memory such as a dynamic random access memory (DRAM) and/or a non-volatile memory such as a flash memory. The memory 2020 may include a DRAM, a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a NOR flash memory, a NAND flash memory, and a fusion flash memory (e.g., a memory in which a static random access memory (SRAM) buffer, a NAND flash memory, and a NOR interface logic are combined). The memory 2020 may store image data acquired from the peripheral device 2040 or an image signal processed by the processor 2010.

The display device 2030 may include a driving circuit 2031 and a display panel 2032, and the driving circuit 2031 may display image data applied through the system bus 2050 on the display panel 2032. The driving circuit 2031 may include a level shifter that levels-shifts image data to a higher voltage level to transfer it to the DAC. The level shifter according to some implementations may control a discharge current that discharges an input capacitor of the DAC. For example, the level shifter may limit a magnitude of the discharge current corresponding to bits excluding an upper bit. In some implementations, the level shifter may limit discharge currents to the same or different magnitudes. The level shifter may limit discharge currents discharging input capacitors of DACs connected to different source lines to a same amount.

The peripheral device 2040 may be a device that converts a motion picture or still image, such as for a camera, scanner, or webcam, into an electrical signal. The image data acquired through the peripheral device 2040 may be stored in the memory 2020 or may be displayed on the panel 2032 in real time.

The display system 2000 may be provided in a mobile electronic product such as a smart phone, but the present disclosure is not limited thereto, and may be provided in various types of electronic products that display images.

In some implementations, each component or combinations of two or more components described with reference to FIG. 1 to FIG. 20 may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), or the like.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations of particular inventions. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations, one or more features from a combination can in some cases be excised from the combination, and the combination may be directed to a subcombination or variation of a subcombination.

While this disclosure has been described in connection with what is presently considered to be practical implementations, it is to be understood that the disclosure is not limited to the disclosed implementations, but, on the contrary, is intended to cover various modifications and equivalent dispositions included within the spirit and scope of the appended claims.

DISPLAY DRIVING DEVICE, SOURCE DRIVER, AND DISPLAY DEVICE INCLUDING THEREOF

Information

Publication Number

Date Filed

Date Published

Inventors

Original Assignees

CPC

International Classifications

Abstract

Description

Claims

Priority Claims (1)