Patent Grant
9978330
The present invention relates to the field of display, particularly to a display driving method.
With the continuous development of electronic technology, LCD displays have been widely used in various fields. A thin film transistor (TFT) array substrate is an important part of a liquid crystal display. Most TFT array substrate includes a base, common electrode lines, gate lines and data lines and other structures, wherein the gate lines are disposed between the two lines of sub-pixel, the data lines are disposed between the two columns of sub-pixels, the crossing regions of the gate lines and the data lines form the pixel units; the common electrode lines are also disposed between two lines of sub-pixel.
A driving method shown in
The embodiment of the present invention provides a display driving method, which can reduce the coupling effect due to the rapid changes of the voltage on the gate line and improve stability of display.
The present application provides a display driving method using overlapping scan mode, each two lines of pixel units have two gate lines to control the two lines respectively, the two gate lines drive the pixel units connected thereto respectively, each gate line group including N pairs of adjacent two gate lines, N being a natural number, said driving method comprising:
providing switching voltage signals to the odd gate lines in the gate line group sequentially;
providing switching voltage signals to the even gate lines in the gate line group sequentially;
wherein when the switching voltage signal on the odd gate lines is in the falling edge, the switching voltage signal on the even gate lines is in the rising edge.
Further, when N=1, each of the gate line group including four gate lines.
The gate line group comprises a first gate line, a second gate line, a third gate line and the fourth gate line, the driving method comprising:
providing switching voltage signals to the first gate line, and providing a first data voltage signal to the corresponding first line of the pixel units;
providing switching voltage signals to the third gate line, and providing a third data voltage signal to the corresponding third line of the pixel units;
providing switching voltage signals to the fifth gate line, and providing a fifth data voltage signal to the corresponding fifth line of the pixel units;
providing switching voltage signals to the seventh gate line, and providing a seventh data voltage signal to the corresponding seventh line of the pixel units;
providing switching voltage signals to the second gate line, and providing a second data voltage signal to the corresponding second line of the pixel units;
providing switching voltage signals to the fourth gate line, and providing a fourth data voltage signal to the corresponding fourth line of the pixel units;
providing switching voltage signals to the sixth gate line, and providing a sixth data voltage signal to the corresponding sixth line of the pixel units;
providing switching voltage signals to the eighth gate line, and providing a eighth data voltage signal to the corresponding eighth line of the pixel units.
Further, providing a data voltage signal to the corresponding first line of the pixel units comprising: providing a first data voltage signal to the corresponding first line of the pixel units in the second half of the switching voltage signal;
providing a data voltage signal to the corresponding third line of the pixel units comprising: write the first data voltage signal of the first line of the pixel units to the corresponding third line of the pixel units in the first half of the switching voltage signal, and write the third data voltage signal to the third line of the pixel units in the second half of the switching voltage signal;
providing a data voltage signal to the second line of the pixel units comprising: write the third data voltage signal of the third line of the pixel units to the corresponding second line of the pixel units in the first half of the switching voltage signal, and write the second data voltage signal to the second line of the pixel units in the second half of the switching voltage signal;
providing a data voltage signal to the fourth line of the pixel units comprising: write the second data voltage signal of the first line of the pixel units to the corresponding fourth line of the pixel units in the first half of the switching voltage signal, and write the fourth data voltage signal to the fourth line of the pixel units in the second half of the switching voltage signal.
Further, when N=2, each of the gate line group including eight gate lines.
Further, the gate line group comprises a first gate line, a second gate line, a third gate line, a fourth gate line, a fifth gate line, a sixth gate line, a seventh gate line and a eighth gate line, the driving method comprising:
providing switching voltage signals to the first gate line, and providing a data voltage signal to the corresponding first line of the pixel units;
providing switching voltage signals to the third gate line, and providing a data voltage signal to the corresponding third line of the pixel units;
providing switching voltage signals to the fifth gate line, and providing a data voltage signal to the corresponding fifth line of the pixel units;
providing switching voltage signals to the seventh gate line, and providing a data voltage signal to the corresponding seventh line of the pixel units;
providing switching voltage signals to the second gate line, and providing a data voltage signal to the corresponding second line of the pixel units;
providing switching voltage signals to the fourth gate line, and providing a data voltage signal to the corresponding fourth line of the pixel units;
providing switching voltage signals to the sixth gate line, and providing a data voltage signal to the corresponding sixth line of the pixel units;
providing switching voltage signals to the eighth gate line, and providing a data voltage signal to the corresponding eighth line of the pixel units.
Further, providing a data voltage signal to the corresponding first line of the pixel units comprising providing a first data voltage signal to the corresponding first line of the pixel units in the last quarter of the switching voltage signal;
providing a data voltage signal to the corresponding third line of the pixel units comprising: providing the first data voltage signal to a corresponding third line of the pixel units in the third quarter of the switching voltage signal, and providing the third data voltage signal to the corresponding third line of the pixel units in the last quarter of the switching voltage signal;
providing a data voltage signal to the corresponding fifth line of the pixel units comprising: providing the first data voltage signal to a corresponding fifth line of the pixel units in the second quarter of the switching voltage signal, providing the third data voltage signal to the corresponding fifth line of the pixel units in the third quarter of the switching voltage signal, and providing the fifth data voltage signal to the corresponding fifth line of the pixel units in the last quarter of the switching voltage signal;
providing a data voltage signal to the corresponding seventh line of the pixel units comprising: providing the first data voltage signal to a corresponding seventh line of the pixel units in the first quarter of the switching voltage signal, providing the third data voltage signal to the corresponding seventh line of the pixel units in the second quarter of the switching voltage signal, providing the fifth data voltage signal to the corresponding seventh line of the pixel units in the third quarter of the switching voltage signal, and providing the seventh data voltage signal to the corresponding seventh line of the pixel units in the last quarter of the switching voltage signal;
providing a data voltage signal to the corresponding second line of the pixel units comprising: providing the third data voltage signal to a corresponding second line of the pixel units in the first quarter of the switching voltage signal, providing the fifth data voltage signal to the corresponding second line of the pixel units in the second quarter of the switching voltage signal, providing the seventh data voltage signal to the corresponding second line of the pixel units in the third quarter of the switching voltage signal, and providing the second data voltage signal to the corresponding second line of the pixel units in the last quarter of the switching voltage signal;
providing a data voltage signal to the corresponding fourth line of the pixel units comprising: providing the fifth data voltage signal to a corresponding fourth line of the pixel units in the first quarter of the switching voltage signal, providing the seventh data voltage signal to the corresponding fourth line of the pixel units in the second quarter of the switching voltage signal, providing the second data voltage signal to the corresponding fourth line of the pixel units in the third quarter of the switching voltage signal, and providing the fourth data voltage signal to the corresponding fourth line of the pixel units in the last quarter of the switching voltage signal;
providing a data voltage signal to the corresponding sixth line of the pixel units comprising: providing the seventh data voltage signal to a corresponding sixth line of the pixel units in the first quarter of the switching voltage signal, providing the second data voltage signal to the corresponding sixth line of the pixel units in the second quarter of the switching voltage signal, providing the fourth data voltage signal to the corresponding sixth line of the pixel units in the third quarter of the switching voltage signal, and providing the sixth data voltage signal to the corresponding sixth line of the pixel units in the last quarter of the switching voltage signal;
providing a data voltage signal to the corresponding eighth line of the pixel units comprising: providing the second data voltage signal to a corresponding eighth line of the pixel units in the first quarter of the switching voltage signal, providing the fourth data voltage signal to the corresponding eighth line of the pixel units in the second quarter of the switching voltage signal, providing the sixth data voltage signal to the corresponding eighth line of the pixel units in the third quarter of the switching voltage signal, and providing the eighth data voltage signal to the corresponding eighth line of the pixel units in the last quarter of the switching voltage signal.
Furthermore, while providing switching voltage signals sequentially to the odd gate lines in the gate line group, the method further comprising:
storing the switching voltage signal of the even gate lines in the random access memory of the timing controller;
reading from the random access memory of the timing controller the switching voltage signals of the even gate lines.
According to the display driving method of an embodiment of the present invention, all the gate lines are divided into several groups, when scanning the display, firstly the odd gate lines in the first gate line group are provided with switching voltage signals sequentially, then the even gate lines in the first gate line group are provided with switching voltage signals sequentially. In this way, the switching voltage signals on the adjacent two gate lines are set in a manner that one is in rising edge while the other is in falling edge, the magnetic field generated by voltage changes in the two adjacent gate lines are canceled by each other, which improves the stability of display.
In order to illustrate the embodiments of the present invention or the prior art more clearly, the drawings to be referenced in describing the embodiments will be described in brief. Obviously, the drawings to be described hereinafter is merely some embodiments of the present invention; for persons of ordinary skill in the art, without the premise of creative effort, other drawings can be obtained according to these figures.
Embodiments of the present invention provide a display driving method which can reduce the coupling phenomenon due to rapid changes in voltage on the gate lines, improving the stability of display.
In the following description, for illustration rather than limitation, specific details such as system structures, interfaces, techniques are proposed for a thorough understanding of the present invention. However, other embodiments of the present invention without these specific details are apparent to those skilled in the art. In other instances, detailed description to the well-known devices, circuits, and methods is omitted in order to avoid unnecessary detail description from dimming the present invention.
The display driving method according to the present invention can be used for driving a display device, wherein the display device may include: a liquid crystal display or an organic light emitting diode (OLED) panel. Various embodiments of the present invention are described using LCD as example.
The present embodiment provides a display driving method using overlapping scan mode (i.e. the switching voltage signals are overlapped therebetween), each two adjacent lines of pixel units of the LCD have two gate lines, the two gate lines drive the pixel units connected thereto respectively, each gate line group includes N pairs of adjacent two gate lines, N being a natural number. In the present embodiment, two gate line groups comprising a first gate line group and a second gate line group are exemplified. As shown in
Step 101, providing a switching voltage signal to the odd gate lines in the first gate line group sequentially.
In the LCD according to the present embodiment, each two lines of pixel units have two gate lines to control the two lines respectively, the two gate lines drive the pixel units connected thereto respectively, each gate line group including N pairs of adjacent two gate lines, N being a natural number. Specifically, the structure of the array substrate of the present embodiment is shown in
In the present embodiment, all the gate lines are divided into several groups, each of the groups has at least four gate lines and the numbers of gate lines in each group are same. During display of the LCD, firstly the odd gate lines in the first gate line group are provided with switching voltage signals sequentially. Hereinafter, the driving method of the present step will be described in detail with for example, four gate lines in each gate line group.
As shown in
Firstly, providing a switching voltage signal to the first gate line G1, and providing a data voltage signal to the corresponding first line of the pixel units. Specifically, providing a first data voltage signal 1 to a corresponding first line of the pixel units in the second half of the switching voltage signal.
Then, providing a switching voltage signal to the third gate line G3, and providing a data voltage signal to the corresponding third line of the pixel units. Specifically, since the third gate line G3 is turned on when the data signal driving unit provides the first data voltage signal 1 to the first line of the pixel units, thus the first data voltage signal 1 of the first line of the pixel units is written to the corresponding third line of the pixel units in the first half of the switching voltage signal, and the third data voltage signal 3 is written to the third line of the pixel units in the second half of the switching voltage signal.
Besides, then the gate lines are grouped, six or eight gate lines can be divided into one group, other even number can be used as desired. The present invention is not limited hereto.
Step 102, providing switching voltage signals to the even gate lines in the first gate line group sequentially.
After providing switching voltage signals to the odd gate lines in the first gate line group sequentially is completed, the even gate lines in the first gate line group are provided with switching voltage signals sequentially.
Firstly, providing switching voltage signal to the second gate line G2, and providing a data voltage signal to the second line of the pixel units. Specifically, since the second gate line G2 is turned on when the data signal driving unit provides the third data voltage signal 3 to the third line of the pixel units, thus the third data voltage signal 3 of the third line of the pixel units is written to the corresponding second line of the pixel units in the first half of the switching voltage signal, and the second data voltage signal 2 is written to the third line of the pixel units in the second half of the switching voltage signal.
Then, providing a switching voltage signal to the fourth gate line G4, and providing a data voltage signal to the corresponding fourth line of the pixel units. Specifically, since the fourth gate line G4 is turned on when the data signal driving unit provides the second data voltage signal 2 to the second line of the pixel units, thus the second data voltage signal 2 of the second line of the pixel units is written to the corresponding fourth line of the pixel units in the first half of the switching voltage signal, and the fourth data voltage signal 4 is written to the fourth line of the pixel units in the second half of the switching voltage signal.
As shown in
Further, as shown in
Step 103, providing a switching voltage signal to the odd gate lines in the second gate line group sequentially; and
Step 104, providing switching voltage signals to the even gate lines in the second gate line group sequentially.
The second gate line group comprises a fifth gate line G5, a sixth gate line G6, a seventh gate line G7 and a eighth gate line G8, each of the gate lines are provided with switching voltage signal. The above mentioned steps specifically comprise:
Providing a switching voltage signal to the fifth gate line G5, and providing a data voltage signal to the fifth line of the pixel units; specifically, the fourth data voltage signal 4 of G4 is written to the corresponding fifth line of the pixel units in the first half of the switching voltage signal, and the fifth data voltage signal 5 is written to the fifth line of the pixel units in the second half of the switching voltage signal;
Providing a switching voltage signal to the seventh gate line G7, and providing a data voltage signal to the seventh line of the pixel units; specifically, the fifth data voltage signal 5 of G5 is written to the corresponding seventh line of the pixel units in the first half of the switching voltage signal, and the seventh data voltage signal 7 is written to the seventh line of the pixel units in the second half of the switching voltage signal;
Providing a switching voltage signal to the sixth gate line G6, and providing a data voltage signal to the sixth line of the pixel units; specifically, the seventh data voltage signal 7 of G7 is written to the corresponding sixth line of the pixel units in the first half of the switching voltage signal, and the sixth data voltage signal 6 is written to the sixth line of the pixel units in the second half of the switching voltage signal;
Providing a switching voltage signal to the eighth gate line G8, and providing a data voltage signal to the eighth line of the pixel units; specifically, the sixth data voltage signal 6 of G6 is written to the corresponding eighth line of the pixel units in the first half of the switching voltage signal, and the eighth data voltage signal 8 is written to the eighth line of the pixel units in the second half of the switching voltage signal.
Moreover, while providing a switching voltage signal to the odd gate lines in the gate line group sequentially, the method further comprises:
storing the switching voltage signal of the even gate lines in the RAM (random access memory) of the timing controller;
and before providing the switching voltage signals sequentially to the even gate lines in the gate line group, the method further comprising:
reading from the RAM of the timing controller the switching voltage signals of the even gate lines.
In the present embodiment, after providing the switching voltage signal to the first gate line, the third gate line rather than the second gate line is provided with switching voltage signal, therefore the switching voltage signal of the second gate line shall be stored temporarily. Specifically, according to the present embodiment, the switching voltage signals of the even gate lines are stored in the RAM of the timing controller, and when the switching voltage signals shall be provided to the even gate lines, the switching voltage signals of the even gate lines can be read from the RAM of the timing controller.
As shown in
Step 201, providing a switching voltage signal to the first gate line, and providing a data voltage signal to the corresponding first line of the pixel units;
specifically, firstly providing switching voltage signals to the first gate line G10, and then providing a first data voltage signal 1 to a corresponding first line of the pixel units in the last quarter of the switching voltage signal.
Step 202, providing switching voltage signals to the third gate line, and providing a data voltage signal to the corresponding third line of the pixel units;
specifically, after providing switching voltage signals to the third gate line G30, the data signal driving unit is providing the first data voltage signal 1 in the third quarter of the switching voltage signal and the TFT is turned on in this period, therefore the data signal driving unit provides the first data voltage signal to a corresponding third line of the pixel units in the third quarter of the switching voltage signal, and provides the third data voltage signal 3 in the last quarter of the switching voltage signal, thus providing the third data voltage signal 3 to the corresponding third line of the pixel units in the last quarter of the switching voltage signal.
Step 203, providing switching voltage signals to the fifth gate line, and providing a data voltage signal to the corresponding fifth line of the pixel units;
specifically, providing the first data voltage signal 1 to a corresponding fifth line of the pixel units through the fifth gate line G50 in the second quarter of the switching voltage signal, providing the third data voltage signal 3 to the corresponding fifth line of the pixel units in the third quarter of the switching voltage signal, and providing the fifth data voltage signal 5 to the corresponding fifth line of the pixel units in the last quarter of the switching voltage signal.
Step 204, providing switching voltage signals to the seventh gate line, and providing a data voltage signal to the corresponding seventh line of the pixel units;
specifically, providing the first data voltage signal 1 to a corresponding seventh line of the pixel units through the seventh gate line G70 in the first quarter of the switching voltage signal, providing the third data voltage signal 3 to the corresponding seventh line of the pixel units in the second quarter of the switching voltage signal, providing the fifth data voltage signal 5 to the corresponding seventh line of the pixel units in the third quarter of the switching voltage signal, and providing the seventh data voltage signal 7 to the corresponding seventh line of the pixel units in the last quarter of the switching voltage signal.
Step 205, providing switching voltage signals to the second gate line, and providing a data voltage signal to the corresponding second line of the pixel units;
specifically, providing the third data voltage signal 3 to a corresponding second line of the pixel units through the second gate line G20 in the first quarter of the switching voltage signal, providing the fifth data voltage signal 5 to the corresponding second line of the pixel units in the second quarter of the switching voltage signal, providing the seventh data voltage signal 7 to the corresponding second line of the pixel units in the third quarter of the switching voltage signal, and providing the second data voltage signal 2 to the corresponding second line of the pixel units in the last quarter of the switching voltage signal.
Step 206, providing switching voltage signals to the fourth gate line, and providing a data voltage signal to the corresponding fourth line of the pixel units;
specifically, providing the fifth data voltage signal 5 to a corresponding fourth line of the pixel units through the fourth gate line G40 in the first quarter of the switching voltage signal, providing the seventh data voltage signal 7 to the corresponding fourth line of the pixel units in the second quarter of the switching voltage signal, providing the second data voltage signal 2 to the corresponding fourth line of the pixel units in the third quarter of the switching voltage signal, and providing the fourth data voltage signal 4 to a corresponding fourth line of the pixel units in the last quarter of the switching voltage signal.
Step 207, providing switching voltage signals to the sixth gate line, and providing a data voltage signal to the corresponding sixth line of the pixel units;
specifically, providing the seventh data voltage signal 7 to a corresponding sixth line of the pixel units through the sixth gate line G60 in the first quarter of the switching voltage signal, providing the second data voltage signal 2 to a corresponding sixth line of the pixel units in the second quarter of the switching voltage signal, providing the fourth data voltage signal 4 to a corresponding sixth line of the pixel units in the third quarter of the switching voltage signal, and providing the sixth data voltage signal 6 to a corresponding sixth line of the pixel units in the last quarter of the switching voltage signal.
Step 208, providing switching voltage signals to the eighth gate line, and providing a data voltage signal to the corresponding eighth line of the pixel units;
specifically, providing the second data voltage signal 2 to a corresponding eighth line of the pixel units through the eighth gate line G80 in the first quarter of the switching voltage signal, providing the fourth data voltage signal 4 to a corresponding eighth line of the pixel units in the second quarter of the switching voltage signal, providing the sixth data voltage signal 6 to a corresponding eighth line of the pixel units in the third quarter of the switching voltage signal, and providing the eighth data voltage signal 8 to a corresponding eighth line of the pixel units in the last quarter of the switching voltage signal.
According to the display driving method of an embodiment of the present invention, all the gate lines are divided into several groups, when scanning the display, firstly the odd gate lines in the first gate line group are provided with switching voltage signals sequentially, then the even gate lines in the first gate line group are provided with switching voltage signals sequentially. In this way, the switching voltage signals on the adjacent two gate lines are set in a manner that one is in rising edge while the other is in falling edge, the magnetic field generated by voltage changes in the two adjacent gate lines are canceled by each other, such that the coupling effect is significantly reduce and the stability of display is improved.
The above are specific embodiments of the present invention, but the scope of the present invention is not limited thereto, variations or replacement in the technical scope of the present invention are apparent to any person skilled in the art, and should fall within the protective scope of the present invention. Accordingly, the protective scope of the invention should be defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
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This patent application is a continuation of U.S. patent application Ser. No. 14/137,947, filed Dec. 20, 2013, entitled DISPLAY DRIVING METHOD USING OVERLAPPING SCAN MODE TO REDUCE COUPLING EFFECT, which claims priority to Chinese Patent Application No. CN 201210564612.4, filed Dec. 21, 2012.
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| Child | 15464252 | US |
