Patent Application
20060071892
This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 291888/2004 filed in Japan on Oct. 4, 2004, the entire contents of which are hereby incorporated by reference.
The present invention relates to a display element drive unit which drives a plurality of display elements such as liquid crystal display elements, a display device including the display element drive unit, and a display element drive method. Examples of the display device include: an active-matrix liquid crystal display device; an electrophoretic display; a twist ball display; a reflective display using a fine prism film; a display using light modulation device such as a digital mirror device; a display using an element having a variable luminance of light, such as organic light-emitting display, inorganic light-emitting display, LED (Light Emitting Diode); a field emission display (FED); and a plasma display.
Among liquid crystal display devices of various display schemes, there is an active-matrix liquid crystal display device using a TFT (Thin Film Transistor) for a switching element, as a liquid crystal display device capable of providing display with high resolution.
As illustrated in
The liquid crystal display section 110a has a TFT liquid crystal panel 101. The liquid crystal drive circuit 110b includes a source driver 103 and a gate driver 104 each of which is realized by IC (Integrated Circuit; semiconductor integrated circuit), a controller 105, and a liquid crystal drive power source 106.
In the liquid crystal display device 110 of the above arrangement, externally supplied display data is supplied as display data D, which is a digital signal, through the controller 105 to the source driver 103. The source driver 103 latches the supplied display data D by time division into first to n-th source drivers. Thereafter, the source driver 103 performs D/A (digital/analogue) conversion on the time-divided display data D into an analogue voltage for grayscale display (hereinafter, referred to as “grayscale display voltage”) in synchronism with a horizontal synchronizing signal fed from the controller 105. Then, the source driver 103 outputs the grayscale display voltage via source signal lines (not shown) to the respective liquid crystal display elements in the liquid crystal panel 101.
Meanwhile, as illustrated in
To the source signal lines 114, the grayscale display voltages responsive to luminance levels of target pixels are fed from the source driver 103 illustrated in
Next, an n-th source driver that is one of the constituent elements making up the source driver 103 will be described with reference to
As illustrated in
A grayscale display reference voltage generator circuit 139 generates reference voltages of different levels in accordance with a voltage VR fed from an external reference voltage generator circuit (equivalent to the liquid crystal drive power source 106 illustrated in
The grayscale display reference voltage generator circuit 139 which generates the foregoing reference voltages to generate intermediate voltages generates, for example, 64 levels of reference voltages, as illustrated in
The grayscale display reference voltage generator circuit 139 is composed of: nine halftone voltage input terminals represented by V0, V8, V16, V24, V32, V40, V48, V56, and V64; resistor elements R0 through R7 having resistance ratio for γ correction; a total of 64 resistors including groups of 8 resistors connected across each of the resistor elements R0 through R7. In this manner, the source driver 103 includes resistance ratio called γ correction so that liquid crystal drive output voltages for converting into the grayscale display voltages have broken line characteristic. Consequently, optical characteristics of liquid crystal material are corrected by using the resistance ratio, so that natural grayscale displays can be provided according to the optical characteristics of the liquid crystal material.
Next, the gate driver 104, as illustrated in
The control logic 161 generates a signal required for operation of the bidirectional shift register 162 and then supplies the generated signal to the bidirectional shift register 162. When receiving the clock signal CK and the start pulse signal SP, the bidirectional shift register 162 carries out a shift operation to sequentially bring the start pulse signal SP into sync with the clock signal CK. The bidirectional shift register 162 generates a select pulse and then outputs it to the level shifter 163. The select pulse is the one for selecting from the liquid crystal panel 101 a pixel electrode to be driven by voltage applied from the source driver 103 to the source signal line 114. The level shifter 163 converts a voltage of the select pulse into a voltage at a level required for on/off (selected/non-selected) of the TFT element 113 in the liquid crystal panel 101, and outputs it to an output circuit 164.
In accordance with the signal fed from the level shifter 163, the output circuit 164 applies a voltage at a level required for on/off of the TFT element 113, via the respective output terminals OS1 through OSn, to the gate signal lines 115. That is, as illustrated in
Incidentally, in such a conventional display element drive unit, all display control input signals are supplied through the controller 105 illustrated in
For this reason, due to voltage levels of gate elements on the panel at power-on, unstable voltages are added to the source voltages. This might cause instantaneous unexpected displays on part of the scanning lines or over the entire panel.
In order to avoid such a phenomenon, Japanese Laid-Open Patent Application No. 4244/2004 (Tokukai 2004-4244; published on Jan. 8, 2004), for example, adopts a technique of outputting another given voltage to a panel electrode or an external counter electrode CS by a switch of output switch means which is provided between grayscale selection means (D/A converter) and a liquid crystal panel electrode.
However, in the conventional display element drive unit, since a technique of Japanese Laid-Open Patent Application No. 4244/2004 has a necessity for reducing resistance of switch means (analogue switch or the like) to prevent a voltage drop of the grayscale display voltage, it has the problem of an extremely large circuit area for switch means (analogue CMOS or the like) which switches to an analogue voltage converted by the D/A converter.
More specifically, in the arrangement having the voltage level switch means realized by an analogue switch as illustrated in
At the point, in the case where the arrangement of Japanese Laid-Open Patent Application No. 4244/2004 is adopted, for example, provision of a switch 210 for supply of a pixel voltage to a counter electrode is considered as illustrated in
However, in the arrangement where the switch 210 is provided at the subsequent stage of the output circuit 202 in which the analogue grayscale select voltage resulting from analogue conversion is subjected to low-impedance processing, a resistance impedance is applied to the liquid crystal pixel source voltage A that is an analogue voltage having a low impedance, before reach to the corresponding pixel. Since this resistance impedance component affects, for example, analogue time constant, transient characteristic, or a pixel voltage switching speed such as a voltage drop caused due to a delay of a reach time with increase in slew rate, it is necessary to design an extremely low on-resistance of the analogue switch section 211 according to panel characteristics. Therefore, in the arrangement in which this switch is realized by an analogue circuit which needs to withstand a voltage to some extent, a transistor of large size has to be designed with a design of low on-resistance. This causes a relative increase in circuit scale.
in addition, in order that the switch 210 inversely outputs a common voltage to supply it to a common electrode, an analogue switch section 211 needs to be of a buffer having an ability to cause a common voltage to make a transient response, and needs to be of a low impedance. Therefore, it is necessary to decrease a circuit impedance according to a drive performance of the common electrode, which thus causes a relative increase in circuit scale.
An object of the present invention is to provide: a display element drive unit capable of easing a instantaneous display of distorted image that occurs in a given period at power-on of a panel while minimizing increase of a circuit scale; a display device including the display element drive unit; and a display element drive method.
In order to achieve the above object, a display element drive unit of the present invention is a display element drive unit which drives a display panel including a plurality of display elements so that the display panel provides a display, the display element drive unit comprising: a power-on time display section which separately presets grayscale display digital data to output a grayscale display level voltage different from a grayscale display level voltage based on incoming display data signal to the display elements during a given period between power-on of the display panel and output of the grayscale display level voltage based on the incoming display data signal.
In order to solve the above problem, a display element drive method of the present invention is a display element drive method for driving a display panel including a plurality of display elements so that the display panel provides a display, wherein: during a given period between power-on of the display panel and output of a grayscale display level voltage based on incoming display data signal, grayscale display digital data is separately preset and converted into analogue grayscale display level voltage to output the analogue grayscale display level voltage to the display elements.
That is, due to gate voltage levels of the display element on the display panel, unstable voltages are added to the source voltages. This might cause instantaneous unexpected displays on part of the scanning lines or over the entire display panel.
As a measure for preventing this phenomenon, such a measure is considered to be taken that a given voltage is provided separately to an analogue switch section provided between the display element drive unit and the display panel. However, this measure requires reduction in resistance of the analogue switch section to prevent a voltage drop of a grayscale display voltage. This extremely increases a circuit area of the analogue switch section.
In view of this, in the present invention, the power-on time display section separately presets grayscale display digital data to output a grayscale display level voltage different from a grayscale display level voltage based on incoming display data signal to the display elements during a given period between power-on of the display panel and output of the grayscale display level voltage based on the incoming display data signal.
Therefore, in the present invention, a digital section basically fixes the separately preset grayscale display digital data during an unstable display period at the power-on. This makes a circuit configuration designed in a digital manner. Thus, it is possible to design a circuit configuration further smaller than that of the switch section realized by an analogue circuit.
A D/A converter circuit is used in the conventional manner, which does not affect drive performance of analogue output.
Consequently, it is possible to provide: a display element drive unit capable of easing an instantaneous display of distorted image that occurs in a given period at power-on of the panel while minimizing increase of a circuit scale; and a display element drive method.
Further, a display element drive unit of the present invention, in the foregoing display element drive unit, includes: a transfer section which transfers a start pulse signal based on a clock signal; a latch section which receives incoming display data signal in synchronism with the clock signal and then outputs the incoming display data signal as synchronization data; a sampling section which samples the synchronization data in accordance with the transferred start pulse signal and then outputs the sampled synchronization data; a level shift section which increases a voltage of the sampled synchronization data; a digital analogue converter section which carries out digital-analogue conversion of digital data outputted from the sampling section; and an output section which outputs a grayscale display-use analogue voltage obtained by the digital-analogue converter section to the display elements, and the power-on time display section includes: a power-on time judgment section which judges power-on of the display panel; a switch section which switches between the separately preset grayscale display digital data and grayscale display digital data based on the incoming display data signal; and a switch control section which controls, in accordance with the judgment of power-on by the power-on time judgment section, switch between the separately preset grayscale display digital data and the grayscale display digital data based on the incoming display data signal by the switch section.
According to the present invention, the power-on time display section is provided in front of the level shift section. This arrangement makes the digital section to basically fix the separately preset grayscale display digital data during an unstable display period at the power-on. Consequently, it is possible to minimize a circuit increase by providing the power-on time display section for a low voltage drive section that drives with 3V to 5V power voltage at the previous stage of the level shift section.
The arrangements of the transfer section for transferring a start pulse signal based on a clock signal, the latch section, the sampling section, the level shift section, the digital-analogue converter section, and the output section are the same as the arrangement of the conventional display element drive unit. Therefore, it is possible to solve the problem of an instantaneous display at the power-on while maintaining the installation of the existing periphery components of the panel.
Further, the power-on time display section includes: (a) the power-on time judgment section which judges power-on of the display panel; (b) the switch section which switches between the separately preset grayscale display digital data and grayscale display digital data based on incoming display data signal; and (c) the switch control section which controls, in accordance with the judgment of power-on by the power-on judgment section, the switch between the separately preset grayscale display digital data and the grayscale display digital data based on the incoming display data signal performed by the switch section.
Therefore, it is possible to provide a specific arrangement of the power-on time display section.
The digital-analogue converter section which carries out digital-analogue conversion is generally realized by the grayscale display reference voltage generator circuit and an adjustment amplifier so as to generate a desired intermediate voltage. Therefore, a display voltage at the power-on is outputted in accordance with the conventional grayscale conversion scheme. Consequently, it is possible to reduce a circuit scale and terminals count, thus reducing the cost of manufacture.
Further, in order to solve the above problem, a display device of the present invention includes the foregoing display element drive unit.
According to the above invention, it is possible to provide a display device including the display element drive unit capable of easing an instantaneous display of distorted image that occurs in a given period at power-on of the panel while minimizing increase of a circuit scale.
The following description will sufficiently clarify further objects, characteristics, and excellent points of the present invention. Further, advantages of the invention will be clarified with reference to the ensuing detailed description taken in conjunction with the accompanying drawings.
The following will describe one embodiment of the present invention with reference to
As illustrated in
The liquid crystal display section 10a has a liquid crystal panel 1 as a TFT display panel. The liquid crystal drive circuit 10b includes a source driver 3 and a gate driver 4 each of which is realized by IC (Integrated Circuit; semiconductor integrated circuit), a controller 5, and a liquid crystal drive power source 6.
In the liquid crystal display device 10 of the above arrangement, externally supplied display data is supplied as display data D, which is a digital signal, through the controller 5 to the source driver 3. The source driver 3 latches the supplied display data D by time division into first to n-th source drivers. Thereafter, the source driver 3 performs D/A (digital/analogue) conversion on the time-divided display data D into an analogue voltage for grayscale display (hereinafter, referred to as “grayscale display voltage”) in synchronism with a horizontal synchronizing signal fed from the controller 5. Then, the source driver 3 outputs the grayscale display voltage via source signal lines (not show) to the respective liquid crystal display elements in the liquid crystal panel 1.
Meanwhile, as illustrated in
To the source signal lines 14, the grayscale display voltages responsive to luminance levels of target pixels are fed from the source driver 3 illustrated in
Next, a n-th source driver 30 that is one of the constituent elements making up the source driver 3 will be described with reference to
As illustrated in
In the present embodiment, in addition to the conventional structure, a display data/reset display data selector circuit 60 as switch means, a display data/reset display data selector control circuit 50 as switch control means, and a power-on reset circuit 40 as a power-on time judgment means are provided. The display data/reset display data selector circuit 60 is provided between the hold memory circuit 34 and the level shifter circuit 35. The display data/reset display data selector control circuit 50 generates a display data/reset display data selector control signal DSCS for control of the display data/reset display data selector circuit 60. The display data/reset display data selector circuit 60, the display data/reset display data selector control circuit 50, and the power-on reset circuit 40 make up a power-on time display section 20 as power-on time display means of the present invention.
The following will describe details of the power-on reset circuit 40, the display data/reset display data selector control circuit 50, and the display data/reset display data selector circuit 60 in the power-on time display section 20.
First, the structure of the power-on reset circuit 40 is described with reference to
In the power-on reset circuit 40, as illustrated in
The power-on reset signal RS is a signal having a given reset period right after the power-on and is generated based on (i) the time constant conversion signal TS that is an input signal to the inverter buffer circuit 43 and (ii) a gate voltage threshold value of the inverter buffer circuit 43. The reset period is arbitrarily settable by changing element parameters of the resistor element (R) 41, the capacitor element (C) 42, and the inverter buffer circuit 43. The power-on reset circuit 40 generates the power-on reset signal RS at a power-on timing.
Next, the following will describe the structure of the display data/reset display data selector control circuit 50.
The display data/reset display data selector control circuit 50, as illustrated in
The gate combination circuit section 51 has an inner logical structure varying depending upon a generation timing of the display data/reset display data selector control signal DSCS. In the present embodiment, the gate combination circuit section 51 is adapted so as to generate the display data/reset display data selector control signal DSCS so that reset data is written within a time period between the power-on and first operation of the controller 5.
In the display data/reset display data selector control circuit 50, as illustrated in
At timing T2 when operation is initiated by the controller signal CNT, the display data/reset display data selector control signal DSCS is set to an applied voltage “Low”.
In this manner, the gate combination circuit section 51 generates the display data/reset display data selector control signal DSCS, which outputs a pulse, within a time period between the power-on and first operation of the controller 5.
Here, the timing T2 when the display data/reset display data selector control signal DSCS is set to an applied voltage “Low” at the first operation of the controller, depends on how long a reset display time, as described later, is required beginning from the power-on. Moreover, for example, change of a timing of the setting to an applied voltage “Low” from the timing when the controller first operates to a timing after the controller signal CNT of plural pulses is supplied, can be realized by change of an internal gate combination in the gate combination circuit section 51.
Next, the structure of the display data/reset display data selector circuit 60 is described with reference to
The display data/reset display data selector circuit 60, as illustrated in
Switches 63 and 64 in the data select circuit 62 are equivalent to analogue switches or two-bit multiplexer circuit realized in logical level. When an applied voltage “High” is applied to a gate, one of the switches 63 and 64 is brought into conduction, and the other is brought into out of conduction. The switches 63 and 64 are controlled by the display data/reset display data selector control signal DSCS as a gate voltage or a signal resulting from conversion by inverse logic of an inverter 65. Because of this operation, either the switch 63 or the switch 64 is brought into conduction.
The data select circuit 62 outputs a data signal as a result of switching operation for selecting between (a) the display data stored by normal operation in the one-bit hold memory circuit 61 and (b) reset display data to be displayed during a reset period. The switching operation is controlled by the display data/reset display data selector control signal DSCS.
In the display data/reset display data selector circuit 60, when an applied voltage of the display data/reset display data selector control signal DSCS is set to “Low”, the switch 63 is brought into conduction, but the switch 64 is brought out of conduction. With this arrangement, data latched in the one-bit hold memory circuit 61 is selected for output.
On the other hand, an applied voltage of the display data/reset display data selector control signal DSCS is set to “High”, the switch 63 is brought out of conduction, but the switch 64 is brought into conduction. With this arrangement, the reset display data is selected for output.
As to setting of the reset display data, a voltage level is preset corresponding to a color displayed in a display reset state. This setting is performed by internally fixed setting or by externally supplied setting.
That is, the following function is provided: the function of selectively outputting display data corresponding to a reset display only in a period during which an applied voltage of the display data/reset display data selector control signal DSCS is set to “High”, by using the display data/reset display data selector control signal DSCS generated in a time period between the power-on and first operation of the controller 5 illustrated in
As to the setting of the reset display data, conversion into a state close to a non-illuminated state of the panel is carried out. That is, for a normally white-mode module, display data on white display or display data on display close to white display is set. For a normally black-mode module, display data on black display or display data on display close to black display is set.
With the display data at the reset time set to these states, display at the power-on of the panel is fixed to a normal state, and an internal data condition is made stable. This initiates the operation without distortions on the display.
Here, as to the method of setting the foregoing reset display data, the following will present specific arrangements of the internally fixed setting and the externally supplied setting.
First, the following will present two examples for the internally fixed setting. In the present embodiment, it is assumed that data is fixed to display color data in the normal non-illuminated state of the liquid crystal panel 1 during an unstable period right after the power-on. A first example is shown in
As illustrated in
A second example is shown in
As illustrated in
In the external setting of non-illuminated state data, it is possible to externally supply the non-illuminated state data to reset data fixing parts (parts indicated by circles in
Further, all of the display data/reset display data selector circuit 60, the display data/reset display data selector control circuit 50, and the power-on reset circuit 40 in the present embodiment are realized by logic circuits. Under a normal operation, the voltage for display is an analogue voltage which is converted from the reset display data. However, in the present embodiment, the reset data at the power-on is controlled by the digital section. Thus, a special voltage for reset, i.e. common voltage, is neither supplied nor used.
Since the analogue display voltage is resulted from the conversion of the reset display data through the D/A converter circuit 36 and the output circuit 37 used under normal operation, the arrangement in which a voltage level that is one of the grayscale display voltage levels is selected is adopted. Therefore, the level shifter circuit 35, the D/A converter circuit 36, the output circuit 37, and the grayscale reference voltage generator circuit 39, all of which are equivalent to the liquid crystal drive system circuit, are realized with the conventional arrangements. Accordingly, it is possible to reduce a circuit scale and reduce terminals count, thus reducing the cost of manufacture.
That is, in the present embodiment, display data/reset display data selector circuit 60, the display data/reset display data selector control circuit 50, and the power-on reset circuit 40, which are provided back of the hold memory circuit 34 and internally generate and switch to a period during which reset is carried out in the non-illuminated state of the panel right after the power-on, are realized by digital circuits.
As a result of this, it is possible to provide (i) the liquid crystal drive circuit 10b which easing the problem of a instantaneous display at the power-on and (ii) the liquid crystal display device 10 including the liquid crystal drive circuit 10b, by being provided with means for setting an internal scanning signal to grayscale data in the non-illuminated state of the liquid crystal panel 1 (black for the normally black mode and white for the normally white mode) and then outputting the converted voltage for the grayscale display level from the source driver, during a given period at the power-on of the panel.
Thus, in the liquid crystal drive circuit 10b of the present embodiment, the power-on time display section 20 presets grayscale display digital data separately to output a grayscale display level voltage, which is different from a grayscale display level voltage based on incoming display data, to a plurality of liquid crystal display elements A during a period between the power-on of the liquid crystal panel 1 and output of the grayscale display level voltage based on the incoming display data.
Therefore, in the present embodiment, the digital section basically fixes the separately preset grayscale display digital data during an unstable display period at the power-on. This makes a circuit configuration designed in a digital manner. Thus, it is possible to design a circuit configuration further smaller than that of switch means realized by an analogue circuit.
The D/A converter circuit 36 is used in the conventional manner, which does not affect drive performance of analogue output.
Consequently, it is possible to provide the liquid crystal drive circuit 10b capable of easing an instantaneous display of distorted image that occurs in a given period at power-on of a panel while minimizing increase of a circuit scale; a display element drive method.
In the present embodiment, the power-on time display section 20 is provided in front of the level shifter circuit 35. This arrangement makes the digital section to basically fix the separately preset grayscale display digital data during an unstable display period at the power-on. Consequently, it is possible to minimize a circuit increase by providing the power-on time display section 20 for a low voltage drive section that drives with 3V to 5V power voltage at the previous stage of the level shift section.
The arrangements of the shift register circuit 32 for transferring a start pulse signal based on a clock signal, the input latch circuit 31, the sampling memory circuit 33, the level shifter circuit 35, the D/A converter circuit 36, and the output circuit 37 are the same as the arrangement of the conventional display element drive unit. Therefore, it is possible to solve the problem of an instantaneous display at the power-on while maintaining the installation of the existing periphery components of the panel.
Further, the power-on time display section 20 includes: (a) the power-on reset circuit 40 which judges power-on of the liquid crystal panel 1; (b) the display data/reset display data selector circuit 60 which switches between a separately preset grayscale display digital data and grayscale display digital data based on incoming display data signal; and (c) the display data/reset display data selector control circuit 50 which controls, in accordance with the judgment of power-on by the power-on reset circuit 40, the switch between the separately preset grayscale display digital. data and the grayscale display digital data based on the incoming display data signal performed by the display data/reset display data selector circuit 60. Therefore, it is possible to provide a specific arrangement of the power-on time display section 20.
The D/A converter circuit 36 which carries out digital-analogue conversion is generally realized by the grayscale reference voltage generator circuit 39 and an adjustment amplifier so as to generate a desired intermediate voltage. Therefore, a display voltage at the power-on-is outputted in accordance with the conventional grayscale conversion scheme. Consequently, it is possible to reduce a circuit scale and terminals count, thus reducing the cost of manufacture.
In the liquid crystal drive circuit 10b of the present embodiment, the display data/reset display data selector circuit 60 is provided at the subsequent stage of the hold memory circuit 34 which is provided to hold the output of the sampling memory circuit 33 and provided at the previous stage of the level shifter circuit 35.
Therefore, in generating the separately preset display element drive voltage, the present invention provides a solution in such a manner that the conventional liquid crystal drive unit which converts display data into analogue voltage is made to perform switching of display data prior to the analogue conversion. Thus, it is possible to easily solve the problem without increasing a circuit scale.
Further, in the liquid crystal drive circuit 10b and the display element drive method of the present embodiment, the display data/reset display data selector control circuit 50 controls switch to display data close to a non-illuminated state of the display elements, as the separately preset grayscale display digital data. Here, the display data close to a non-illuminated state of the display elements is black data in the normally black mode and white data in the normally white mode. With this arrangement, it is possible to bring a display maintaining a power-off state at the power-on.
Still further, in the liquid crystal drive circuit 10b of the present embodiment, the display element is a liquid crystal display element A. Therefore, the liquid crystal drive circuit 10b which drives the liquid crystal display element A, is capable of easing the problem of an instantaneous display of distorted image that occurs in a given period at power-on of a panel while minimizing increase of a circuit scale.
Yet further, the liquid crystal display device 10 of the present embodiment includes the liquid crystal drive circuit 10b. Consequently, it is possible to provide the liquid crystal display device 10 including the liquid crystal drive circuit 10b capable of easing the problem of an instantaneous display of distorted image that occurs in a given period at power-on of a panel while minimizing increase of a circuit scale.
As described above, in a display element drive unit of the present invention, the switch means is provided at the subsequent stage of the scanning data hold means which is provided to hold output of the sampling means, and provided at the previous stage of the level shift means.
According to the above invention, the switch means is provided at the subsequent stage of the scanning data hold means which is provided to hold output of the sampling means, and provided at the previous stage of the level shift means.
Therefore, in generating the separately preset display element drive voltage, the present invention provides a solution in such a manner that the conventional liquid crystal drive unit which converts display data into analogue voltage is made to perform switching of display data prior to the analogue conversion. Thus, it is possible to easily solve the problem without increasing a circuit scale.
Further, in a display element drive unit of the present invention, the switch control means controls switch to display data close to a non-illuminated state of the display elements, as a separately preset grayscale display digital data.
Still further, in a display element drive method of the present invention, display data close to a non-illuminated state of the display elements is used as the separately preset grayscale display digital data.
According to the above invention, the switch control means controls switch to the display data close to a non-illuminated state of the display elements, as the separately preset grayscale display digital data. Here, the display data close to a non-illuminated state of the display elements is black data in the normally black mode and white data in the normally white mode.
With this arrangement, it is possible to bring a display maintaining a power-off state at the power-on.
Yet further, in a display element drive unit of the present invention, the display element is a liquid crystal display element.
According to the above invention, it is possible to provide a display element drive unit driving the liquid crystal display element, the display element drive unit capable of easing an instantaneous display of distorted image that occurs in a given period at power-on of a panel while minimizing increase of a circuit scale.
Specific embodiments or examples implemented in the description of the embodiments only show technical features of the present invention and are not intended to limit the scope of the invention. Variations can be effected within the spirit of the present invention and the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-291888 | Oct 2004 | JP | national |
