Between the electrodes 102 and 104 is a display mechanism 106. In the embodiment of
The display mechanism 106 has a number of individually turned-on steps 112A, 112B, 112C, and 112D, collectively referred to as the individually turned-on steps 112. While there are four such steps 112 in the example of
The steps 112 can further correspond to different pillars or other types of structures within the display mechanism 106. That is, the terminology step as used herein is used in a broad, encompassing sense. As such, this terminology encompasses different types of structures that can be implemented within the display mechanism 106, such as pillars.
The individually turned-on steps 112 are defined by varying the heights of the layers 108 and 110, from top to bottom in
Furthermore, the larger the gap between a given step of the conductive steps 112 and the opposing electrode 102 in
Thus, the positive turn-on voltage thresholds for the steps 112 are ordered from a lowest turn-on voltage threshold PVD to a highest turn-on voltage threshold PVA. No two of the positive turn-on voltage thresholds are equal to one another. A positive voltage applied between the electrodes 102 and 104 turns on those of the steps 112 having positive turn-on voltage thresholds less than or equal to the positive voltage applied.
Likewise, the negative turn-off voltage thresholds for the steps are ordered from a highest, or greatest, or least negative turn-off voltage NVD to a lowest, or most negative turn-off voltage NVA. No two of the negative turn-off voltage thresholds are equal to one another. A negative voltage applied between the electrodes 102 and 104 turns off those of the steps 112 having negative turn-off voltage thresholds having absolute magnitudes less than or equal to the absolute magnitude of the negative voltage applied.
For example, consider the situation in which just the step 112B is desired to be turned on. First, a positive voltage PV is applied between the electrodes 102 and 104 of
Next, a negative voltage NV is applied between the electrodes 102 and 104, where NVC>NV>NVB. Because the negative voltage NV is less than the negative turn-off voltage thresholds NVC and NVD for the steps 112C and 112D, respectively, both of the steps 112C and 112D are turned off. That is, the negative voltage NV has an absolute magnitude such that |NVD|<|NVC|<|NV|<|NVB|, where |x| denotes the absolute magnitude of x. The step 112B remains on, because its negative turn-off voltage threshold NVB is less than the negative voltage NV applied (i.e., the absolute magnitude of NVB is greater than the absolute magnitude of NV). The step 112A still remains off, as before. Thus, just the step 112B is ultimately turned on. If the step 112D is also to be turned on, in addition to the step 112B, a second positive voltage PV is applied, where PVD<=PV<PVC.
In general, the steps 112 are turned on in a desired combination as follows. First, a positive voltage is applied that is equal to or greater than the step having the highest positive turn-on voltage threshold that is to be turned on. This positive voltage turns on all the steps having positive turn-on voltage thresholds less than the positive voltage applied. Next, a negative voltage is applied that is equal to or less than the step having the lowest, most negative turn-off voltage threshold that has been turned on but should be turned off. That is, a negative voltage is applied that has an absolute magnitude that is greater than or equal to the step having a turn-off voltage threshold that has the highest absolute magnitude and that has been turned on but should be turned off. This negative voltage turns off all the steps having negative turn-off voltage thresholds having absolute magnitudes less than the absolute magnitude of the negative voltage applied. This process is then repeated for the step having the next-highest positive turn-on voltage threshold that is to be turned on, the next-lowest negative turn-off voltage threshold (i.e., the negative turn-off voltage having the next-highest absolute magnitude) that is to be turned off, and so on, until the steps 112 have been turned on in the desired combination.
For example, consider the situation where the steps 112A and 112C are to be turned on, and the steps 112B and 112D are to remain off. A positive voltage is applied that is equal to or greater than PVA, the positive turn-on voltage threshold for the step 112A. This turns on all the steps 112. Next, a negative voltage is applied that is equal to or less than NVB, the negative turn-off voltage threshold for the step 112B, but greater than NVA, the negative turn-off voltage threshold for the step 112A. (That is, the negative voltage has an absolute magnitude that is equal to or greater than the absolute magnitude of NVB, but that is less than the absolute magnitude of NVA.) This turns off the steps 112B, 112C, and 112D, while the step 112A remains on.
However, the step 112C is also to be turned on. Therefore, another positive voltage is applied, which is equal to or greater than PVC, the positive turn-on voltage threshold for the step 112C, but is less than PVB, the positive turn-on voltage threshold for the step 112B. This turns on the steps 112C and 112D. However, the step 112D is not supposed to be turned on. Therefore, a negative voltage is applied that is equal to or less than NVD, the negative turn-off voltage threshold for the step 112D, but greater than NVC, the negative turn-off voltage threshold for the step 112C. (I.e., the negative voltage has an absolute magnitude that is greater than the absolute magnitude of NVD, but less than the absolute magnitude of NVC.) This turns off the step 112D, while the steps 112A and 112C remain on, and the step 112B remains off.
This process of sequentially turning on and off the steps 112 so that any combination of the steps 112 is on provides the display element 100 to have a bit depth, such as a grayscale bit depth, that is greater than the number of the steps 112 themselves. For instance, in the examples that have been described, there are four of the steps 112. However, because any combination of these steps 112 can be turned on, the display element 100 has a bit depth of 24, or sixteen. That is, the steps 112 can be individually turned on and off as desired using the process that has been described above, to realize a display element 100 that has a bit depth equal to all the different combinations of the steps 112 being turned on or off.
Therefore, the display element 100 is advantageous as compared to prior art bi-stable display elements, because it provides for multiple individually turned-on steps within a single display element addressable by a pair of addressable lines 114 and 116 of a display. For instance, as has been described in relation to
By comparison, in the prior art, four such individually turned-on steps would be realized by having individual pairs of addressable lines for each of these steps. In effect, a separately addressable display element would implement each of the steps within the prior art. As such, embodiments of the invention provide for a significant reduction in the number of addressable lines that are needed for each realized individually turned-on step. For instance, the embodiment described in relation to
In one embodiment, each of the individually turned-on steps of a display element corresponds to a single color of a pixel of a display. For instance, the steps of the display element may correspond to the color red of the pixel, the color green of the pixel, or the color blue of the pixel. As such, the steps provide for multiple-bit contrast depth of the display element for this color of the pixel. For example, where there are N steps, the steps provide for 2N-bit contrast depth for the color of the pixel to which the display element corresponds.
In another embodiment, the individually turned-on steps of a display element may be divided into groups, where each group corresponds to a different color of a pixel of a display to which the display element itself corresponds. For instance, the steps of the display element may be grouped into three groups: a red group corresponding to the color red of the pixel, a green group corresponding to the color green of the pixel, and a blue group corresponding to the color blue of the pixel. In this way, the steps provide for multiple-bit contrast depth of the display element for each of the three colors of the pixel. For example, where there are R steps in the red group, G steps in the green group, and B steps in the blue group, the steps provide for 2R-bit contrast depth for red, 2G-bit contrast depth for green, and 2B-bit contrast depth for blue of the pixel to which the display element corresponds.
The steps 112A, 112B, 112C, 112D, and 112E belong to a green group. The steps 112F, 112G, and 112H belong to a blue group, and the steps 112I, 112J, and 112K belong to a red group. The area of the green group is twice that of the area of the blue group. The area of the blue group is equal to the area of the red group. Thus, twice as much contrast depth is provided for green as for red or blue within the display element of
Each of the display elements 402 can be implemented as the display element 100 as has been described. The display elements 402 can be bi-stable display elements, such that they retain their current states being displayed even if power is removed from the elements 402. Thus, power is needed only to change the states of the display elements 402, and not to retain the states of the display element 402.
The display device 400 also includes addressable lines 408A, 408B, . . . , 408J, collectively referred to as the addressable lines 408 and corresponding to the rows 404 into which the display elements 402 are organized. The display device 400 further includes addressable lines 410A, 410B, . . . , 410K, collectively referred to as the addressable line 410 and corresponding to the columns 406 into which the display elements 402 are organized. The display device 400 can and typically will include other components, in addition to the display elements 402 and the addressable lines 408 and 410, as can be appreciated by those of ordinary skill within the art.
The addressable lines 408 are connected to all of the display elements 402 within their respective rows 404. Thus, the addressable line 408A is connected to all of the display elements 402 within the row 404A, the addressable line 408B is connected to all of the display elements 402 within the row 404B, and so on. Similarly, the addressable lines 410 are connected to all of the display elements within their respective columns 406. Thus, the addressable line 410A is connected to all of the display elements 402 within the column 406A, the addressable line 410B is connected to all of the display elements 402 within the column 406B, and so on.
In this way, each of the display elements 402 is addressable by a unique pair of addressable lines, including one of the addressable lines 408 and one of the addressable lines 410. That is, no two display elements are connected to both the same one of the addressable lines 408 and the same one of the addressable lines 410. To change the state of a given display element, positive and/or negative voltages are applied between the addressable lines to which the display element in question is connected. This process is performed for each of the display elements 402, to change the states of all of the display elements 402.
Embodiments of the invention thus provide for advantages over other approaches to achieve multiple-bit contrast depth display elements, particularly to achieve multiple-bit contrast depth bi-stable display elements. Within the prior art, a given bi-stable display element has just two states, on and off. As a result, to achieve multiple-bit contrast depth, a number of such display elements may need to be used to correspond to a given pixel or a given pixel color. However, where these display elements each is addressable by a unique pair of addressable lines of the display device, the resulting number of addressable lines needed can be quite large, resulting in a cost-prohibitive display device design.
By comparison, embodiments of the invention provide for a bi-stable display element that has more than two states. Multiple-bit contrast depth can then be achieved by using a single display element. All of the states of such a display element are controlled by the same unique pair of addressable lines of the display device connected to this display element. As a result, as compared to the prior art, less addressable lines are needed to achieve the same multiple-bit contrast depth, which renders the resulting display device design more cost effective.