Patent Application
20130286314
The present invention relates to a display element.
A liquid crystal panel used in a liquid crystal display device has a configuration in which a liquid crystal layer is sandwiched between a pair of glass substrates, and the two main types of liquid crystal panels are the VA (vertical alignment) type and the IPS (in-plane switching) type, differentiated by the direction in which the electric field is applied to the liquid crystal layer. Of these types, in an IPS-type liquid crystal panel, pixel electrodes and opposite electrodes are provided in the same layer as each other on one of the pair of glass substrates, and the orientation of the liquid crystal molecules is controlled by applying to the liquid crystal layer an electric field that is substantially parallel to the glass substrate. A so-called FFS (fringe field switching) type is a further improvement on the IPS type, in which the pixel electrodes and the opposite electrodes are disposed in different layers through an interlayer insulating layer, and slits are formed in the pixel electrodes, thus generating a fringe electric field having a component perpendicular to the surface of the glass substrate in addition to a component parallel to the surface of the glass substrate. One known example of this type of liquid crystal panel is that disclosed in Patent Document 1 below.
The liquid crystal display device disclosed in Patent Document 1 has a so-called top gate TFT. The top gate TFT has a configuration in which a semiconductor layer, a gate insulating layer, a gate electrode, a first interlayer insulating layer, and a source electrode and a drain electrode are layered in this order on a glass substrate, and on the source electrode and the drain electrode, a protective layer, an opposite electrode, a second interlayer insulating layer, and a pixel electrode are layered in this order. Of these, the drain electrode is connected to the semiconductor layer through a first contact hole formed in the first interlayer insulating layer, while the pixel electrode is connected to the drain electrode through a second contact hole formed in the second interlayer insulating layer and the protective layer, and thus, the pixel electrode is connected to the semiconductor layer of the TFT through the drain electrode.
In the liquid crystal display device disclosed in Patent Document 1, the first contact hole and the second contact hole are aligned in the horizontal direction, or in other words, the direction along the surface of the glass substrate. Thus, the drain electrode has a portion connected to the semiconductor layer therebelow and a portion connected to the pixel electrode thereabove, aligned horizontally to each other along the direction parallel to the surface of the glass substrate, which results in a tendency for the drain electrode to have a large area, thus resulting in a lower aperture ratio for the pixel.
The present invention was made in view of the above-mentioned situation, and an object thereof is to increase the aperture ratio of the pixels.
A display element of the present invention further includes: a substrate; a first conductive layer provided on the substrate; a first insulating layer provided over the first conductive layer and having a first contact hole; a second conductive layer provided over the first insulating layer, the second conductive layer being connected to the first conductive layer through the first contact hole and having a step section raised onto an edge of the first contact hole; a second insulating layer provided over the second conductive layer and having a second contact hole positioned over the first contact hole; and a third conductive layer provided over the second insulating layer and connected to the second conductive layer through the second contact hole, wherein the second insulating layer is configured such that an edge of the second contact hole is interposed between the step section of the second conductive layer and the third conductive layer.
With this configuration, the second conductive layer is connected to the first conductive layer through the first contact hole formed in the first insulating layer, whereas the third conductive layer is connected to the second conductive layer through the second contact hole formed in the second insulating layer. As a result, the third conductive layer is connected to the first conductive layer through the second conductive layer. Here, the first contact hole and the second contact hole are disposed one over the other, and thus, the part of the second conductive layer connected to the first conductive layer corresponds in position to the part of the second conductive layer connected to the third conductive layer. Therefore, compared to a case in which the contact holes are not disposed one over the other and instead are aligned in a direction along the substrate, it is possible to make the area of the second conductive layer smaller, thus improving the aperture ratio of the pixels.
If the first contact hole and the second contact hole are disposed one over the other as described above, then there is a possibility that the third conductive layer connected to the second conductive layer through the second contact hole is layered directly on the step section of the second conductive layer raised onto the edge of the first contact hole, which causes the portion layered on the step section to have a bend, which means that the third conductive layer is susceptible to disconnections and the like. In the present invention, in the second insulating layer, the edge of the second contact hole is interposed between the step section of the second conductive layer and the third conductive layer, which prevents the third conductive layer from being directly layered on the step section. Therefore, it is possible to prevent disconnections from occurring in the third conductive layer.
As embodiments of the present invention, the following configurations are preferable.
(1) The second conductive layer has a flat first contact section in contact with the first conductive layer, whereas the third conductive layer has a flat second contact section in contact with the first contact section, and the first contact section is larger in area than the second contact section. With this configuration, between the portion of the third conductive layer raised up from the second contact section in contact with the first contact section of the second conductive layer, and the step section of the second conductive layer, a gap corresponding to the difference in area between both contact sections is ensured, which allows the edge of the second contact hole in the second insulating layer to be interposed therebetween. This makes it possible to prevent disconnection in the third conductive layer more reliably.
(2) The second insulating layer is configured such that the edge of the second contact hole covers the entire step section. With this configuration, the portion of the third conductive layer raised up from the second contact section can be reliably prevented from being directly layered on the step section, thus more reliably preventing disconnections in the third conductive layer.
(3) The step section is raised up from an entire edge of the first contact section, and the second insulating layer is configured such that the edge of the second contact hole covers the entire step section. With this configuration, the portion of the third conductive layer raised up from the second contact section can be reliably prevented from being directly layered on the step section raised up from the entire edge of the first contact section, and therefore, it is possible to more reliably prevent disconnection in the third conductive layer.
(4) The step section is raised up from an edge of the first contact section such that portions of the step section face each other, and the second contact section is disposed on the first contact section in a center between the portions of the step section facing each other. With this configuration, even if manufacturing variation were to occur in the area and position of both contact sections, it is possible to more reliably interpose the edge of the second contact hole in the second insulating layer between the portion of the third conductive layer raised up from the second contact section, and the step section with portions that face each other.
(5) The second contact section is disposed such that a center thereof matches a center of the first contact section. With this configuration, even if manufacturing variation were to occur in the area and position of both contact sections, it is possible to even more reliably interpose the edge of the second contact hole in the second insulating layer between the portion of the third conductive layer raised up from the second contact section, and the step section with portions that face each other.
(6) The second insulating layer is made of an organic material. With this configuration, compared to a case in which the second insulating layer is made of an inorganic material, the edge of the second contact hole formed in the second insulating layer becomes smoother, which makes it more difficult for disconnections to occur in the third conductive layer formed along the edge of the second contact hole. Also, from the perspective of planarizing the third conductive layer, this configuration is preferable.
(7) The second insulating layer is configured such that the edge of the second contact hole has a curved shape in a cross-sectional view. With this configuration, it is even more difficult for disconnections to occur in the third conductive layer formed along the edge of the second contact hole.
(8) A third insulating layer disposed on the third conductive layer and a fourth conductive layer disposed on the third insulating layer are further included. With this configuration, because the third conductive layer is prevented from being directly layered on the step section, thus preventing disconnections from occurring in the third conductive layer, it is possible to prevent cracks from forming in the third insulating layer formed on the third conductive layer. Therefore, it is possible to prevent short-circuiting between the third conductive layer and the fourth conductive layer with the third insulating layer interposed therebetween.
(9) At least one of the third conductive layer and the fourth conductive layer has a slit therein. With this configuration, if a difference in potential is generated between the third conductive layer and the fourth conductive layer, an electric field including a component in a direction along a surface of the substrate is applied as a result of the slit. Thus, if the substrate is disposed opposite to the opposite substrate and the liquid crystal layer is sealed between both substrates, it is possible to control the orientation of the liquid crystal molecules with the electric field with a component in the direction along the surface of the substrate, and thus, this technique is suitably applicable to a liquid crystal panel of the so-called FFS (fringe field switching) type or the like.
(10) The third conductive layer and the fourth conductive layer are both made of a transparent conductive material. With this configuration, it is possible to attain a higher aperture ratio for the pixel compared to a case in which a light-shielding metal material is used.
(11) The transparent conductive material is ITO (indium tin oxide). With this configuration, lower resistivity and excellent heat resistance, acid resistance, and alkali resistance, and the like can be attained, compared to a case in which ZnO (zinc oxide) is used, for example.
(12) The third conductive layer constitutes an opposite electrode, whereas the fourth conductive layer constitutes a pixel electrode. With this configuration, by applying a voltage between the opposite electrode and the pixel electrodes, it is possible to generate an electric field including a component in a direction along the surface of the substrate.
(13) The first conductive layer is a common wiring line that supplies a reference potential to the opposite electrode (third conductive layer) through the second conductive layer. With this configuration, the common wiring lines (first conductive layer) are connected to the opposite electrode (third conductive layer) through the second conductive layer, and thus, the reference potential can be supplied to the opposite electrode.
(14) The common wiring line is made of a light-shielding metal. With this configuration, compared to a case in which a transparent conductive material is used, the wiring resistance is lower, and thus, it is possible to prevent defects such as signal lag.
(15) A TFT constituted of a drain electrode connected to the pixel electrode that is the fourth conductive layer, a semiconductor layer having one end connected to the drain electrode, a source electrode connected to another end of the semiconductor layer, and a gate electrode that applies a gate voltage to the semiconductor layer is further included, wherein the second conductive layer is made of the same material as the drain electrode and the source electrode. With this configuration, by applying a gate voltage to the gate electrodes at a prescribed timing while supplying data signals to the source electrodes of the TFTs, it is possible for a drain current to flow between the source electrode and the drain electrode through the semiconductor layer therebetween, and as a result, it is possible to apply a prescribed potential to the pixel electrodes. Thus, an electric field based on the difference between the potential of the pixel electrode and the reference potential of the opposite electrode can be generated. According to the present invention, the second conductive layer is made of the same material as the drain electrode and the source electrode, and thus, in the manufacturing process of the display element, it is possible to form the second conductive layer in the same step as forming the drain electrode and the source electrode. Therefore, it is possible to reduce the manufacturing cost for the display element.
According to the present invention, it is possible to increase the aperture ratio of the pixels.
Embodiment 1 of the present invention will be described with reference to
First, a configuration of the liquid crystal display device 10 will be explained. As shown in
The liquid crystal panel 11 will be described. As shown in
First, the array substrate 20 will be described, mainly focusing on the plan view configuration of the pixels thereof. As shown in
As shown in
As shown in
On an edge of the array substrate 20, a terminal drawn from the gate wiring lines 26 and the common wiring lines 31 and a terminal drawn from the source wiring lines 27 are formed, and by inputting signals from external circuits that are not shown in drawings to these terminals, the driving of the TFTs 24 is controlled. On the inner surface of the array substrate 20, an alignment film 33 for orienting the liquid crystal molecules included in the liquid crystal layer 22 is formed (refer to
On the other hand, as shown in
Next, the layered configuration of the TFTs 24 formed on the array substrate 20 will mainly be described in detail. As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
Next, the connective configuration of the common wiring lines 31 to the opposite electrode 32 will be described in detail. As shown in
As shown in
As shown in
As shown in
As shown in
The substantially flat portion of the contact electrode 42 that enters the first contact hole 39b and is connected to the common wiring line 31 (including the pad section 31a) is the first contact section 42a as shown in
As shown in
As shown in
The second contact section 43a has a plan view shape similar to the first contact hole 39b, the first contact section 42a, and the second contact hole 40b, and is a square slightly smaller than the first contact hole 39b and the first contact section 42a. As shown in
As shown in
In addition, in the present embodiment, the edge 40b1 of the second contact hole 40b in the second interlayer insulating layer 40 is interposed between the recessed section 43 in the opposite electrode 42 and the step section 42b of the contact electrode 42. Specifically, the edge 40b1 of the second contact hole 40b in the second interlayer insulating layer 40 is interposed between the raised section 43b, which is a portion of the recessed section 43 of the opposite electrode 32 that is raised from the second contact section 43a, and the step section 42b that is raised from the first contact section 42a of the contact electrode 42, over the entire periphery thereof, and the recessed section 43 is not directly layered on the step section 42b. If the recessed section of the opposite electrode were directly layered on the step section of the contact electrode, a bent portion would be formed in the layered section, which reduces the coverage of the recessed section in the bent portion, which increases the susceptibility of the recessed section to disconnection. If disconnection occurs in the recessed section, the third interlayer insulating layer thereabove is susceptible to cracking, which can cause short-circuiting between the opposite electrode and the pixel electrode. According to the present embodiment, the step section 42b is covered over the entire area thereof by the edge 40b1 of the second contact hole 40b in the second interlayer insulating layer 40, and thus, the recessed section 43 is prevented in advance from being directly raised onto the step section 42b, thus allowing disconnections in the recessed section 43 to be prevented. If disconnection in the recessed section 43 is prevented, then cracks in the third interlayer insulating layer 41 thereabove is also prevented, which can prevent the occurrence of short-circuiting between the opposite electrode 32 and the pixel electrode 25 sandwiching the third interlayer insulating layer 41. Thus, it is possible to attain a high display quality.
Furthermore, the first contact section 42a and the second contact section 43a are disposed such that the centers thereof match, and therefore, the distance between the raised section 43b of the recessed section 43 and the step section 42b in the contact electrode 42, or in other words, the thickness of the edge 40b1 of the second contact hole 40b in the second interlayer insulating layer 40 is even throughout the entire edge. Thus, even if a portion of the raised section 43b and a portion of the step section 42b were formed closer to each other than designed due to variations in manufacturing, it is possible to interpose the edge 40b1 of the second contact hole 40b in the second interlayer insulating layer 40 between the raised section 43b and the step section 42b, and therefore, it is possible to more reliably prevent the recessed section 43 from being disposed directly on the step section 42b.
As described above the liquid crystal panel (display element) 11 of the present embodiment includes: an array substrate (substrate) 20; a common wiring line 31 (first conductive layer) provided on the array substrate 20; a first interlayer insulating layer 39 (first insulating layer) provided over the common wiring line 31 (first conductive layer) and having a first contact hole 39b; a contact electrode 42 (second conductive layer) provided over the first interlayer insulating layer 39 (first insulating layer), connected to the common wiring line 31 (first conductive layer) through the first contact hole 39b, and having a step section 42b raised onto an edge of the first contact hole 39b; a second interlayer insulating layer 40 (second insulating layer) provided over the contact electrode 42 (second conductive layer) and having a second contact hole 40b positioned over the first contact hole 39b; and an opposite electrode 32 (third conductive layer) provided over the second interlayer insulating layer 40 (second insulating layer) and connected to the contact electrode 42 (second conductive layer) through the second contact hole 40b, the second interlayer insulating layer 40 (second insulating layer) being configured such that the edge 40b1 of the second contact hole 40b is interposed between the step section 42b of the contact electrode 42 (second conductive layer) and the opposite electrode 32 (third conductive layer).
With this configuration, the contact electrode 42 (second conductive layer) is connected to the common wiring line 31 (first conductive layer) through the first contact hole 39b formed in the first interlayer insulating layer 39 (first insulating layer), whereas the opposite electrode 32 (third conductive layer) is connected to the contact electrode 42 (second conductive layer) through the second contact hole 40b formed in the second interlayer insulating layer 40 (second insulating layer). With this configuration, the opposite electrode 32 (third conductive layer) is connected to the common wiring line 31 (first conductive layer) through the contact electrode 42 (second conductive layer). Here, because the first contact hole 39b and the second contact hole 40b are disposed one over the other, a portion of the contact electrode 42 (second conductive layer) connected to the common wiring line 31 (first conductive layer) corresponds in position to the portion of the contact electrode 42 that is connected to the opposite electrode 32 (third conductive layer). Thus, compared to a case in which the contact holes are not disposed one over the other and are instead aligned with respect to each other in a direction along the array substrate 20, it is possible reduce the area of the contact electrode 42 (second conductive layer), and thus, it is possible to improve the aperture ratio of the pixel.
If the first contact hole 39b and the second contact hole 40b are disposed one over the other as described above, there is a risk that the opposite electrode 32 (third conductive layer), which is connected to the contact electrode 42 (second conductive layer) through the second contact hole 40b, is directly layered onto the step section 42b of the contact electrode 42 (second conductive layer) that is raised onto the edge of the first contact hole 39b. If this happens, a bent portion or the like is formed in the portion of the opposite electrode 32 layered on the step portion 42b, which can cause disconnection or the like in the opposite electrode 32 (third conductive layer). However, in the present embodiment, the second interlayer insulating layer 40 (second insulating layer) is formed such that the edge 40b1 of the second contact hole 40b is interposed between the step section 42b of the contact electrode 42 (second conductive layer) and the opposite electrode 32 (third conductive layer). Thus, it is possible to prevent the opposite electrode 32 (third conductive layer) from being directly layered onto the step section 42b. Therefore, it is possible to prevent disconnections from occurring in the opposite electrode 32 (third conductive layer).
Also, the contact electrode 42 (second conductive layer) has the flat first contact section 42a, which is connected to the common wiring line 31 (first conductive layer), whereas the opposite electrode 32 (third conductive layer) has the flat second contact section 43a, which is connected to the first contact section 42a, and the first contact section 42a is greater in area than the second contact section 43a. With this configuration, a gap corresponding to the difference in area between the contact sections 42a and 43a is ensured between the portion of the opposite electrode 32 (third conductive layer) that is raised up from the second contact section 43a (raised section 43b), which is connected to the first contact section 42a of the contact electrode 42 (second conductive layer), and the step section 42b of the contact electrode 42 (second conductive layer). Thus, it is possible to interpose the edge 40b1 of the second contact hole 40b in the second interlayer insulating layer 40 (second insulating layer) between the raised section 43b and the step section 42b. As a result, it is possible to reliably prevent disconnection in the opposite electrode 32 (third conductive layer).
The second interlayer insulating layer 40 (second insulating layer) is configured such that the entire step section 42b is covered by the edge 40b1 of the second contact hole 40b. With this configuration, the portion of the opposite electrode 32 (third conductive layer) raised up from the second contact section 43a can be reliably prevented from being directly layered onto the step section 42b, and therefore, it is possible to more reliably prevent disconnection in the opposite electrode 32 (third conductive layer).
The step section 42b is raised up from the entire edge of the first contact section 42a, and the second interlayer insulating layer 40 (second insulating layer) is configured such that the entire step section 42b is covered by the edge 40b1 of the second contact hole 40b. With this configuration, the section of the opposite electrode 32 (third conductive layer) raised from the second contact section 43a can be reliably prevented from being directly layered on the step section 42b that is raised from the entire edge of the first contact section 42a. Thus, it is possible to more reliably prevent disconnection in the opposite electrode 32 (third conductive layer).
The step section 42b is raised up from the edge of the first contact section 42a such that portions thereof face each other, and the second contact section 43a is disposed in the center of the first contact section 42a between the portions of the step section 42b facing each other. With this configuration, even if manufacturing variation occurs in the area or position of the contact sections, it is possible to reliably interpose the edge 40b1 of the second contact hole 40b in the second interlayer insulating layer 40 (second insulating layer) between the section of the opposite electrode 32 (third conductive layer) raised up from the second contact section 43a, and the step section 42b, portions thereof facing each other.
The second contact section 43a is disposed such that the center thereof matches that of the first contact section 42a. With this configuration, even if manufacturing variation occurs in the area or position of the contact sections, it is possible to more reliably interpose the edge 40b1 of the second contact hole 40b in the second interlayer insulating layer 40 (second insulating layer) between the section of the opposite electrode 32 (third conductive layer) raised up from the second contact section 43a, and the step section 42b, portions thereof facing each other.
The second interlayer insulating layer 40 (second insulating layer) is made of an organic material. Compared to a case in which an inorganic material is used, the shape of the edge 40b1 of the second contact hole 40b formed in the second interlayer insulating layer 40 (second insulating layer) is made smoother, and thus, it is more difficult for disconnections to occur in the opposite electrode 32 (third conductive layer) formed along the edge 40b1 of the second contact hole 40b. An organic material is also preferable from the perspective of planarizing the opposite electrode 32 (third conductive layer).
The second interlayer insulating layer 40 (second insulating layer) has a curved shape in a cross-sectional view of the edge 40b1 of the second contact hole 40b. With this configuration, it is more difficult for disconnections to occur in the opposite electrode 32 (third conductive layer) formed along the edge 40b1 of the second contact hole 40b.
Also, the third interlayer insulating layer 41 (third insulating layer) formed on the opposite electrode 32 (third conductive layer) and the pixel electrodes 25 (fourth conductive layer) formed on the third interlayer insulating layer 41 (third insulating layer) are provided. With this configuration, because it is possible to prevent the opposite electrode 32 (third conductive layer) from being directly layered onto the step section 42b, thus preventing disconnections in the opposite electrode 32 (third conductive layer), the third interlayer insulating layer 41 (third insulating layer) formed on the opposite electrode 32 (third conductive layer) can also be prevented from cracking. Thus, it is possible to prevent short-circuiting between the opposite electrode 32 (third conductive layer) and the pixel electrode 25 (fourth conductive layer) sandwiching the third interlayer insulating layer 41 (third insulating layer).
At least one of the opposite electrode 32 (third conductive layer) and the pixel electrode 25 (fourth conductive layer) has slits 25a formed therein. With this configuration, when a difference in potential is generated between the opposite electrode 32 (third conductive layer) and the pixel electrode 25 (fourth conductive layer), the slits 25a cause an electric field with a component in a direction along the surface of the array substrate 20 to be applied. Thus, if the array substrate 20 is disposed opposite to the opposite substrate 21 and the liquid crystal layer 22 is sealed between the substrates 20 and 21, it is possible to control the orientation of the liquid crystal molecules with the electric field including a component in a direction along the surface of the array substrate 20, and thus, this technique is suitably applicable to a liquid crystal panel 11 of the so-called FFS (fringe field switching) type or the like.
Also, the opposite electrode 32 (third conductive layer) and the pixel electrode 25 (fourth conductive electrode) are both made of a transparent conductive material. With this configuration, it is possible to attain a higher aperture ratio for the pixel compared to a case in which a light-shielding metal material is used.
The transparent conductive material is ITO (indium tin oxide). With this configuration, lower resistivity and excellent heat resistance, acid resistance, and alkali resistance, and the like can be attained, compared to a case in which ZnO (zinc oxide) is used, for example.
The third conductive layer constitutes the opposite electrode 32, whereas the fourth conductive layer constitutes the pixel electrodes 25. With this configuration, by applying a voltage between the opposite electrode 32 and the pixel electrodes 25, it is possible to generate an electric field including a component in a direction along the surface of the array substrate 20.
The first conductive layer is the common wiring line 31 that supplies a reference potential to the opposite electrode 32 (third conductive layer) through the contact electrode 42 (second conductive layer). With this configuration, the common wiring lines 31 (first conductive layer) are connected to the opposite electrode 32 (third conductive layer) through the contact electrodes 42 (second conductive layer), and thus, the reference potential can be supplied to the opposite electrode 32.
The common wiring line 31 is made of a light-shielding metal. With this configuration, compared to a case in which a transparent conductive material is used, the wiring resistance is lower, and thus, it is possible to prevent defects such as signal lag.
The TFTs 24 are provided, each being constituted of the drain electrode 30 connected to the pixel electrode 25 (fourth conductive layer), the semiconductor layer 37 having one end connected to the drain electrode 30, the source electrode 29 connected to the other end of the semiconductor layer 37, and the gate electrode 28 that applies a gate voltage to the semiconductor layer 37. The contact electrode 42 (second conductive layer) is made of the same material as the drain electrode 30 and the source electrode 29. With this configuration, a gate voltage is applied to the gate electrode 28 at a prescribed timing in addition to supplying data signals to the source electrode 29 in the TFT 24, and thus, drain currents flow through the semiconductor layer 37 between the source electrode 29 and the drain electrode 30, which allows a prescribed potential to be applied to the pixel electrode 25. Thus, an electric field based on the difference between the potential of the pixel electrode 25 and the reference potential of the opposite electrode 32 is generated. In the present embodiment, the contact electrode 42 (second conductive layer) is made of the same material as the drain electrode 30 and the source electrode 29, and thus, in the manufacturing process of the liquid crystal panel 11, it is possible to form the contact electrode 42 (second conductive layer) in the same step as forming the drain electrode 30 and the source electrode 29. Therefore, it is possible to reduce the manufacturing cost for the liquid crystal panel 11.
Embodiment 2 of the present invention will be described with reference to
As shown in
The present invention is not limited to the embodiments shown in the drawings and described above, and the following embodiments are also included in the technical scope of the present invention, for example.
(1) In the embodiments above, a case was described in which a characteristic configuration according to the present invention was applied to the connective configuration between the opposite electrode and the common wiring line, but it is also possible to apply the characteristic configuration according to the present invention to the connective configuration between the pixel electrode and the semiconductor layer through the drain electrode of the TFT, for example. In such a case, the semiconductor layer constitutes the “first conductive layer,” the gate insulating layer and the first interlayer insulating layer constitute the “first insulating layer,” the drain electrode constitutes the “second conductive layer,” the third interlayer insulating layer constitutes the “second insulating layer,” and the pixel electrode constitutes the “third conductive layer.” A configuration may be used in which the edge of the third TFT contact hole (second contact hole) in the third interlayer insulating layer is interposed between the step section that is raised onto the edge of the first TFT contact hole (first contact hole) at the drain electrode and the TFT contact section at the pixel electrode.
(2) In the embodiments above, an FFS-type liquid crystal panel was described as an example, but the present invention is also naturally applicable to an IPS-type liquid crystal panel. In an IPS-type liquid crystal panel, the opposite electrodes and the pixel electrodes provided on the array substrate are in the same layer, and thus, an electric field in a direction parallel to the surface of the substrate is applied to the liquid crystal layer. Thus, in an IPS-type device, the opposite electrodes and the pixel electrodes are both the “third conductive layer,” and therefore, characteristic configurations of the present invention can be applied to a part that connects the pixel electrode to the semiconductor layer through the drain electrode, and a part that connects the opposite electrodes to the common wiring lines through the contact electrodes.
(3) Besides (2), the present invention is applicable to a VA (vertical alignment) liquid crystal panel.
(4) In the embodiments above, a case was described in which only the pixel electrodes and not the opposite electrode were provided with slits, but slits may also be provided in the opposite electrode. In such a case, it is preferable that the slits formed in the opposite electrode intersect perpendicularly with the slits formed in the pixel electrodes.
(5) In the embodiments above, a case was described in which only the pixel electrodes and not the opposite electrode were provided with slits, but slits may be formed only in the opposite electrode.
(6) In the embodiments above, a case in which the opposite electrode is provided in a lower layer and the pixel electrodes are provided in an upper layer was described, but the present invention is also applicable to a case in which the layers are reversed such that the pixel electrodes are provided in a lower layer and the opposite electrode is provided in an upper layer.
(7) In the embodiments above, an array substrate having top gate (staggered type, forward staggered type) TFTs was described, but the present invention is also applicable to an array substrate having bottom gate (reverse staggered) TFTs.
(8) In the embodiments above, a case was described in which the semiconductor layer in the TFT is made of p-Si, but a-Si (amorphous silicon) may be used instead.
(9) In the embodiments above, the first contact section has a greater area than the second contact section, but it is possible to have a configuration in which the first contact section and the second contact section have approximately the same area, for example.
(10) In the embodiments above, the edge of the second contact hole covers the entire step section, but a configuration in which the edge of the second contact hole partially covers the step section is also included in the present invention.
(11) In the embodiments above, the step section is raised up from the entire outer edge of the first contact section, but a configuration can be used in which the step section is raised up from only a portion of the outer edge of the first contact section. Even in such a case, it is preferable that the entire step section be covered by the edge of the second contact hole.
(12) In the embodiments above, the center of the first contact hole matches the center of the second contact hole, but the present invention also includes a configuration in which the center of the first contact hole is offset from the center of the second contact hole.
(13) In the embodiments above, the center of the first contact section matches the center of the second contact section, but the present invention also includes a configuration in which the center of the first contact section is offset from the center of the second contact section.
(14) In the embodiments above, a case was described in which the second interlayer insulating layer is made of an organic material, but the second insulating layer can be made of an inorganic material or the like.
(15) In the embodiments above, the gate insulating layer, the first interlayer insulating layer, and the third interlayer insulating layer are all made of an inorganic material, but it is possible to make at least one or all of these of an organic material.
(16) In the embodiments above, the edge of the second contact hole in the second interlayer insulating layer has an arc shape in a cross-sectional view, but it is possible to have a curved shape such as a wave shape. Additionally, it is possible to provide the edge of the second contact hole with a tapered cross-sectional shape.
(17) In the embodiments above, the contact holes (contact sections) and the contact electrodes are square in a plan view, but it is possible to make the shape thereof be a rectangle, a non-quadrilateral polygon, a circle, an ellipse, or the like, for example.
(18) In the embodiments above, the contact electrode juts out from the common wiring line and a pad section is therefore formed in the common wiring line, but if the contact electrode fits within the width of the common wiring line and does not jut out, it is possible to omit the pad section in the common wiring line.
(19) The present invention is also applicable to liquid crystal display devices of the embodiments above, further including a touch panel.
(20) The present invention is applicable to liquid crystal display devices of the embodiments above, further including a parallax barrier (switching liquid crystal panel) in order to attain 3D display.
(21) The present invention is applicable to liquid crystal display devices of the embodiments above, further including a tuner to receive a television signal, or in other words, a television receiver.
(22) In the embodiments above, small- or mid-sized liquid crystal panels were described as examples, but the present invention is applicable to liquid crystal panels that are large or ultra-large.
(23) In the embodiments above, a manufacturing method for an array substrate included in a liquid crystal panel was described, but besides the liquid crystal panel, the present invention is also applicable to an EL display device, a plasma display device, or the like that includes TFTs for driving pixels, for example.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-290645 | Dec 2010 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2011/079493 | 12/20/2011 | WO | 00 | 7/15/2013 |
