Patent Application
20140002373
The subject matter described herein relates generally to the field of electronic devices and more particularly to a display assembly for one or more electronic devices.
Many electronic devices incorporate network interface cards or other network access technology which permits the devices to remain connected to an electronic communication network even when in a low-power operating state. This feature is sometimes referred to as “always on, always connected” or by the acronym AOAC, and enables an electronic device to receive network-based information updates such as electronic mail, status updates, and the like even when the device is in a low-power operating mode.
Further, some electronic devices utilize a “clamshell” housing. By way of example, many laptop computers and mobile electronic devices utilize a clamshell housing in which a keyboard and/or other input/output mechanisms are disposed on a first section and a display is disposed on a second section coupled to the first section, typically by a hinge. Alternatively, a “clamshell” can consist of displays, one on a first section that can also be utilized as a touch keyboard and one display on a second section coupled to the first section by a hinge. Electronic devices with clamshell housings are commonly designed to switch automatically to a low-power state when the clamshell housing is closed and to revert automatically to a power-on state when the clamshell housing is opened.
Users of electronic devices may wish to check the status of network-based information updates on a periodic basis. In most electronic devices this requires waking the electronic device to a full power-on state such that the device's display may be activated to present information updates. For example, in most laptops this requires opening the clamshell housing of the laptop computer.
Accordingly techniques to enable electronic devices to present network based information updates efficiently may find utility.
The detailed description is described with reference to the accompanying figures.
Described herein are exemplary systems and methods to lock, or at least to inhibit the rotation of a display on a clamshell housing. In the following description, numerous specific details are set forth to provide a thorough understanding of various embodiments. However, it will be understood by those skilled in the art that the various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been illustrated or described in detail so as not to obscure the particular embodiments.
In various embodiments, the electronic device 108 may be embodied as a personal computer, a laptop computer, a personal digital assistant, a mobile telephone, an entertainment device, or another computing device. The electronic device 108 includes system hardware 120 and memory 130, which may be implemented as random access memory and/or read-only memory. A file store 180 may be communicatively coupled to computing device 108. File store 180 may be internal to computing device 108 such as, e.g., one or more hard drives, CD-ROM drives, DVD-ROM drives, or other types of storage devices. File store 180 may also be external to computer 108 such as, e.g., one or more external hard drives, network attached storage, or a separate storage network.
System hardware 120 may include one or more processors 122, graphics processors 124, network interfaces 126, and bus structures 128. In one embodiment, processor 122 may be embodied as an Intel® Core2 Duo® processor available from Intel Corporation, Santa Clara, Calif., USA. As used herein, the term “processor” means any type of computational element, such as but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or any other type of processor or processing circuit.
Graphics processor(s) 124 may function as adjunct processor that manages graphics and/or video operations. Graphics processor(s) 124 may be integrated into the packaging of processor(s) 122, onto the motherboard of computing system 100 or may be coupled via an expansion slot on the motherboard.
In one embodiment, network interface 126 could be a wired interface such as an Ethernet interface (see, e.g., Institute of Electrical and Electronics Engineers/IEEE 802.3-2002) or a wireless interface such as an IEEE 802.11a, b or g-compliant interface (see, e.g., IEEE Standard for IT-Telecommunications and information exchange between systems LAN/MAN—Part H: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band, 802.11G-2003). Another example of a wireless interface would be a general packet radio service (GPRS) interface (see, e.g., Guidelines on GPRS Handset Requirements, Global System for Mobile Communications/GSM Association, Ver. 3.0.1, December 2002).
Bus structures 128 connect various components of system hardware 128. In one embodiment, bus structures 128 may be one or more of several types of bus structure(s) including a memory bus, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, 11-bit bus, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association bus (PCMCIA), and Small Computer Systems Interface (SCSI).
Memory 130 may include an operating system 140 for managing operations of computing device 108. In one embodiment, operating system 140 includes a hardware interface module 154 that provides an interface to system hardware 120. In addition, operating system 140 may include a file system 150 that manages files used in the operation of computing device 108 and a process control subsystem 152 that manages processes executing on computing device 108.
Operating system 140 may include (or manage) one or more communication interfaces that may operate in conjunction with system hardware 120 to transceive data packets and/or data streams from a remote source. Operating system 140 may further include a system call interface module 142 that provides an interface between the operating system 140 and one or more application modules resident in memory 130. Operating system 140 may be embodied as a UNIX operating system or any derivative thereof (e.g., Linux, Solaris, etc.) or as a Windows® brand operating system, or other operating systems.
In some embodiments system 100 may comprise a low-power embedded processor, referred to herein as a trusted execution complex 170. The trusted execution complex 170 may be implemented as an independent integrated circuit located on the motherboard of the system 100. In the embodiment depicted in
In some embodiments the trusted execution complex 170 may manage processes to receive and present network-based information updates.
As illustrated in
The architecture of
Embodiments of a hinge assembly 166 suitable for use with the embodiments depicted in
In some embodiments a portion of the second section 162 of the housing is curved to define a hinge pin cover 512 which wraps around hinge pin 510 such that the second section 162 of the housing can rotate about hinge pin 510 to open and close the housing. Further, as illustrated in
In some embodiments the hinge assembly 500 may comprise a bias mechanism such as a compression spring 512 to bias the second section 162 in a position such that the first section 160 and the second section 162 are aligned A releasable latch block 514 may hold the second section 162 in place when it has been translated across the hinge pin 510 to reveal a portion of the display 104. In alternate embodiments a spring blade mechanism that springs to hold the screen in either the open or closed position may be used to secure the alignment of the first section 160 and the second section 162. In further embodiments one or more magnets may be used to align the first section 160 and the second section 162 in both the open and closed position. In further embodiments the hinge assembly 500 is capable of rotational motion only in the first position.
In some embodiments the status update module 176 implements logic to detect when the second section 162 is translated laterally along the hinge pin 510 from the first position to the second position and, in response thereto, to activate the portion of the display 104.
Referring to
In response to the signal, at operation 615, the controller activates the ancillary display on the electronic device 108. By way of example, in some embodiments the status update module 176 may invoke the services of a secure sprite generator 179 to generate a dialog box 280 on a portion of the display 104. In the embodiments depicted in
Assuming a successful login, at operation 620 the controller presents at least one network-based information update on the dialog box 280. By way of example, in some embodiments a user may wish to receive notifications of electronic mail received, status updates, stock prices, weather information, or the like, as well as basic system info like battery status, wireless connectivity, and any location based activity. These information updates may be presented on the dialog box for viewing by a user.
At operation 625 the controller receives user input from a user of the electronic device 108. By way of example, in some embodiments a user may indicate that he or she wants to view one or more electronic mails that have arrived, or to otherwise view an information update. If, at operation 630, the user input does not indicate that the main processor needs to be activated then the user may continue interacting with the electronic device 108 via the dialog box 280. Thus, control may pass back to operation 610 and the controller may continue to monitor for signals which indicate that the ancillary display should be activated.
By contrast, if at operation 630 the user input received at operation 625 indicates that the main processor needs to be activated then control passes to operation 635 and the controller passes an interrupt to the operating system 140 to wake the main processor(s) 172 in the untrusted execution complex, and at operation 640 control of the display is passed to the main processor(s) in the untrusted execution complex.
As described above, in some embodiments the electronic device may be embodied as a computer system.
Electrical power may be provided to various components of the computing device 702 (e.g., through a computing device power supply 706) from one or more of the following sources: one or more battery packs, an alternating current (AC) outlet (e.g., through a transformer and/or adaptor such as a power adapter 704), automotive power supplies, airplane power supplies, and the like. In some embodiments, the power adapter 704 may transform the power supply source output (e.g., the AC outlet voltage of about 110 VAC to 240 VAC) to a direct current (DC) voltage ranging between about 5 VDC to 12.6 VDC. Accordingly, the power adapter 704 may be an AC/DC adapter.
The computing device 702 may also include one or more central processing unit(s) (CPUs) 708. In some embodiments, the CPU 708 may be one or more processors in the Pentium® family of processors including the Pentium® II processor family, Pentium® III processors, Pentium® IV, or CORE2 Duo processors available from Intel® Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used, such as Intel's Itanium®, XEON, and Celeron® processors. Also, one or more processors from other manufactures may be utilized. Moreover, the processors may have a single or multi core design.
A chipset 712 may be coupled to, or integrated with, CPU 708. The chipset 712 may include a memory control hub (MCH) 714. The MCH 714 may include a memory controller 716 that is coupled to a main system memory 718. The main system memory 718 stores data and sequences of instructions that are executed by the CPU 708, or any other device included in the system 700. In some embodiments, the main system memory 718 includes random access memory (RAM); however, the main system memory 718 may be implemented using other memory types such as dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like. Additional devices may also be coupled to the bus 710, such as multiple CPUs and/or multiple system memories.
The MCH 714 may also include a graphics interface 720 coupled to a graphics accelerator 722. In some embodiments, the graphics interface 720 is coupled to the graphics accelerator 722 via an accelerated graphics port (AGP). In some embodiments, a display (such as a flat panel display) 740 may be coupled to the graphics interface 720 through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display. The display 740 signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display.
A hub interface 724 couples the MCH 714 to an platform control hub (PCH) 726. The PCH 726 provides an interface to input/output (I/O) devices coupled to the computer system 700. The PCH 726 may be coupled to a peripheral component interconnect (PCI) bus. Hence, the PCH 726 includes a PCI bridge 728 that provides an interface to a PCI bus 730. The PCI bridge 728 provides a data path between the CPU 708 and peripheral devices. Additionally, other types of I/O interconnect topologies may be utilized such as the PCI Express® architecture, available through Intel® Corporation of Santa Clara, Calif.
The PCI bus 730 may be coupled to an audio device 732 and one or more disk drive(s) 734. Other devices may be coupled to the PCI bus 730. In addition, the CPU 708 and the MCH 714 may be combined to form a single chip. Furthermore, the graphics accelerator 722 may be included within the MCH 714 in other embodiments.
Additionally, other peripherals coupled to the PCH 726 may include, in various embodiments, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), universal serial bus (USB) port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), and the like. Hence, the computing device 702 may include volatile and/or nonvolatile memory.
The terms “logic instructions” as referred to herein relates to expressions which may be understood by one or more machines for performing one or more logical operations. For example, logic instructions may comprise instructions which are interpretable by a processor compiler for executing one or more operations on one or more data objects. However, this is merely an example of machine-readable instructions and embodiments are not limited in this respect.
The terms “computer readable medium” as referred to herein relates to media capable of maintaining expressions which are perceivable by one or more machines. For example, a computer readable medium may comprise one or more storage devices for storing computer readable instructions or data. Such storage devices may comprise storage media such as, for example, optical, magnetic or semiconductor storage media. However, this is merely an example of a computer readable medium and embodiments are not limited in this respect.
The term “logic” as referred to herein relates to structure for performing one or more logical operations. For example, logic may comprise circuitry which provides one or more output signals based upon one or more input signals. Such circuitry may comprise a finite state machine which receives a digital input and provides a digital output, or circuitry which provides one or more analog output signals in response to one or more analog input signals. Such circuitry may be provided in an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). Also, logic may comprise machine-readable instructions stored in a memory in combination with processing circuitry to execute such machine-readable instructions. However, these are merely examples of structures which may provide logic and embodiments are not limited in this respect.
Some of the methods described herein may be embodied as logic instructions on a computer-readable medium. When executed on a processor, the logic instructions cause a processor to be programmed as a special-purpose machine that implements the described methods. The processor, when configured by the logic instructions to execute the methods described herein, constitutes structure for performing the described methods. Alternatively, the methods described herein may be reduced to logic on, e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or the like.
In the description and claims, the terms coupled and connected, along with their derivatives, may be used. In particular embodiments, connected may be used to indicate that two or more elements are in direct physical or electrical contact with each other. Coupled may mean that two or more elements are in direct physical or electrical contact. However, coupled may also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate or interact with each other.
Reference in the specification to “one embodiment” or “some embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.
Although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.
