This relates generally to electronic devices and, more particularly, to electronic devices with displays.
Electronic devices often include displays for displaying information to users. The display function in such devices is typically performed by a liquid crystal display (LCD), plasma, or organic light emitting diode (OLED) display element array that is connected to a grid of source (data) and gate (select) metal traces. The display element array is often formed on a transparent panel such as a glass panel, which serves as a protective shield. The data and select lines of the display element array may be driven by a display driver integrated circuit (IC). The driver IC receives an image or video signal, which it then decodes into raster scan pixel values (color or gray scale) and writes them to the display element array during each frame, by driving the data and select lines. This process is repeated at a high enough frame rate so as to render video.
The select lines are sometimes driven using gate driver circuits that are formed directly on the glass panel. Such types of gate driver configuration are sometimes referred to as “gate driver on array” (GOA) technology, which helps to enable a narrower border design for the display. A conventional gate driver typically includes an output transistor that selectively passes through a clock signal. The clock signal is conveyed via a clock routing path that is connected to an entire column of gate drivers. In order to ensure that the amount of capacitive loading on the clock routing path remains below a desired threshold (i.e., to keep power consumption low), the output transistor in each gate driver of the entire column is limited to a certain size.
In high resolution displays with high refresh rates (i.e., refresh rates equal to or greater than 60 Hz) and especially for displays with integrated touch sensing capabilities, it may be challenging to design a gate driver with an output transistor that does not exceed the maximum allowable sizing while meeting performance requirements. It is within this context that the embodiments herein arise.
In accordance with an embodiment, an electronic device is provided that includes an array of display pixels arranged in rows and columns and gate driver circuitry that is coupled to the array of display pixels and that includes a gate driver having an output at which a corresponding gate line output signal is provided to display pixels arranged along a corresponding row in the array. The gate driver may include a buffer transistor having a first source-drain terminal that receives a clock signal and a second source-drain terminal that is connected to the output and a pulldown transistor that is connected in series with the buffer transistor and that exhibits greater drive strength than the buffer transistor (e.g., the pulldown transistor may be larger in size compared to the buffer transistor).
The gate driver may also include a capacitor having a first terminal that is connected to a gate terminal of the buffer transistor and a second terminal that is connected to the output. The gate driver may also include a clock isolation transistor that receives an additional clock signal that is complementary to the clock signal and that is connected to a gate terminal of the pulldown transistor. The clock isolation transistor may exhibit a smaller drive strength than the buffer transistor (e.g., the clock isolation transistor may be smaller in size compared to the buffer transistor). The buffer transistor and the clock isolation transistor may have gate terminals that are shorted to one another.
The gate driver may also include a first transistor that is coupled in series with the clock isolation transistor and that has a gate terminal, a second transistor that is connected to the buffer transistor and the clock isolation transistor, and a third transistor that is connected in series with the second transistor. The second transistor may have a gate terminal that is shorted to the gate terminal of the first transistor, whereas the third transistor may receive another gate line output signal from a preceding gate driver in the gate driver circuitry.
In accordance with another embodiment, a method for operating a gate driver is provided. The gate driver may include a buffer transistor and a pulldown transistor coupled in series. The method includes generating an output signal at a node that is coupled between the buffer transistor and the pulldown transistor, using only the buffer transistor to pull the output signal high, and using both the buffer transistor and the pulldown transistor to pull the output signal low.
The method also includes receiving a first clock signal at a source-drain terminal of the buffer transistor. The gate driver may further include a clock isolation transistor that is configured to receive a second clock signal that is inverted with respect to the first clock signal and to selectively pass through a low voltage to deactivate the pulldown transistor. The method also includes receiving an asserted set signal to turn on the buffer transistor and the clock isolation transistor, and receiving an asserted reset signal to turn off the buffer transistor, the clock isolation transistor, and the pulldown transistor.
Further features of the present invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.
An illustrative electronic device of the type that may be provided with a display is shown in
Input-output circuitry in device 10 such as input-output devices 12 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 12 may include buttons, joysticks, scrolling wheels, touch pads, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user can control the operation of device 10 by supplying commands through input-output devices 12 and may receive status information and other output from device 10 using the output resources of input-output devices 12.
Input-output devices 12 may include one or more displays such as display 14. Display 14 may be a touch screen display that includes a touch sensor for gathering touch input from a user or display 14 may be insensitive to touch. A touch sensor for display 14 may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor, or other suitable touch sensor arrangements.
Control circuitry 16 may be used to run software on device 10 such as operating system code and applications. During operation of device 10, the software running on control circuitry 16 may display images on display 14. Display 14 may be a liquid crystal display, a plasma display, an organic light-emitting diode display, an electrophoretic display, a quantum dot display, or other types of display.
Display driver circuitry may be used to control the operation of pixels 22. The display driver circuitry may be formed from integrated circuits, thin-film transistor circuits, or other suitable circuitry. Display driver circuitry 28 of
To display the images on display pixels 22, display driver circuitry 28 may supply image data to data lines D while issuing clock signals and other control signals to supporting display driver circuitry such as gate driver circuitry 18 over path 50. If desired, circuitry 28 may also supply clock signals and other control signals to gate driver circuitry on an opposing edge of display 14 (e.g., in a split gate driver configuration).
Gate driver circuitry 18 (sometimes referred to as horizontal control line control circuitry) may be implemented as part of an integrated circuit and/or may be implemented using thin-film transistor circuitry. Horizontal control lines G in display 14 may provide suitable control signals to display pixels 22 arranged along corresponding rows in the array. There may be any suitable number of horizontal control signals per row of pixels 22 (e.g., one or more, two or more, three or more, four or more, etc.).
Each column of pixels 22 preferably includes a sufficient number of data lines to supply image data for all of the subpixels of that column (e.g., a red data line for carrying red data signals to red subpixels, a green data line for carrying green data signals to green subpixels, and a blue data line for carrying blue data signals to blue subpixels).
Each subpixel may be configured depending on the display technology that is being implemented. For example, an organic light-emitting diode (OLED) display subpixel may include an organic light-emitting diode, a drive transistor that controls current flow through the diode, and supporting transistors (e.g., switching transistors and emission enable control transistors). The supporting transistors may be used in performing data loading operations and threshold voltage compensation operations for the drive transistors. Storage capacitors may be used to store data signals between successive frames of data.
As another example, a liquid crystal display (LCD) subpixel may include a storage capacitor and a switching transistor that selectively passes a data signal to the storage capacitor when the corresponding gate line signal is asserted. Depending on the amount of potential that is stored at the capacitor, associated pixel electrode structures may emit an electric field through the liquid crystal material, thereby controlling the amount of light that is transmitted through that subpixel.
As described above, the gate lines may be driven using gate driver circuits.
Transistor 106 has a drain terminal that is connected to the gate driver output, a gate terminal that receives reset signal RST, and a source terminal that is connected to a ground line 110. Transistor 108 has a drain terminal that is connected to the gate driver output, a gate terminal that receives hold signal HOLD, and a source terminal that is connected to ground 110. Transistor 112 has a source terminal that is connected to node X and a gate terminal and a drain terminal that receive control signal SET. Transistor 114 has a drain terminal that is connected to node X, a gate terminal that receives the reset signal RST, and a source terminal that is connected to ground 110.
In high resolution displays operating at high refresh rates (e.g., refresh rates at or above 60 Hz), a stringent requirement may be imposed on the fall time of the gate output pulses. For example, performance criteria may specify that the fall time of gate output falling edge 150 in
As described above, transistor 102 is directly connected to clock routing path 116. Clock routing path 116 is also connected to every other gate driver 100 in a column of gate drivers (see, e.g., gate driver circuitry 18 of
In accordance with an embodiment of the present invention, a gate driver such as gate driver circuit 200 is provided that can help reduce clock loading while improving fall times (see, e.g.,
Transistors 212 and 214 may be coupled in series. Transistor 212 may have a source terminal that is coupled to node X, a drain terminal, and a gate terminal that is shorted to its drain terminal. The gate terminal of transistor 212 may be coupled to a feed-forward path on which gate output signal G(n−4) is routed from a preceding gate driver circuit that is four rows above. The signal that is received via the feed-forward path may be used for setting node X to a high potential and is therefore sometimes referred to as a “set” control signal. Transistor 214 may have a drain terminal that is coupled to node X, a source terminal that is coupled to a ground power supply line 210, and a gate terminal that is coupled to a feed-back path on which gate output signal G(n+6) is routed back from a succeeding gate driver circuit that is six rows below. The signal that is received via the feedback path may be used for resetting node X back down to a low potential and is therefore sometimes referred to as a “reset” control signal.
An exemplary routing arrangement showing how different gate driver circuits 200 may be interconnected in a chain to form gate driver circuitry 18 (
In the example of
The output of each gate driver unit may also be fed back to another input (e.g., the reset input) of a corresponding gate driver unit that is six rows above that gate driver unit (as an example). As shown in
The feed-forward and feedback routing scheme of
Still referring to
In the example of
Referring back to
Transistor 220 may have a first source-drain terminal that receives signal CLKb via clock routing path 218, a second source-drain terminal that is coupled to another intermediate node Y, and a gate terminal that is coupled to node X. Transistor 222 may have a drain terminal that is coupled to node Y, a gate terminal that receives the reset signal (e.g., signal G(n+6)) via the feedback path, and a source terminal that is coupled to ground 210. Last but not least, transistor 206 may have a drain terminal that is coupled to the gate driver output, a gate terminal that is coupled to node Y, and a source terminal that is coupled to ground line 210.
At time t2, signal CLKa pulses high while signal CLKb pulses low. In particular, signal CLKb falling low will drive node Y down to ground (see, interval 300) using activated transistor 220 as a pulldown path. Node Y being pulled down to ground then shuts off transistor 206. When transistor 206 is turned off, the gate output G(n) can be driven high following the waveform of signal CLKa. Since there is nowhere for the voltage on capacitor 204 to discharge (i.e., node X is floating since transistors 212 and 214 are both deactivated during interval 300), the rise in voltage at output G(n) will cause node X to rise further to an even higher voltage level V2.
At time t3, signal CLKa clocks low while signal CLKb clocks high. Signal CLKb rising high will drive node Y back high using activated transistor 220 now as a pull-up path. Node Y being pulled back high reactivates transistor 206 to help pull G(n) back down to ground. Since the voltage on capacitor 204 still has nowhere to discharge, the drop in voltage at output G(n) will cause node X to drop back down to voltage level V1. At time t4, the reset signal (e.g., the feedback signal G(n+6)) may be pulsed high. As a result of the reset signal being asserted, transistors 214 and 222 are turned on to pull node X and node Y back down to ground, respectively. Each row in the gate driver chain may be activated successively in this way to sequentially assert the gate driver output lines.
Configured and operated in this way, transistor 206 can be sized relatively large to help meet fall time requirements for the gate driver output signal (e.g., to help ensure that falling edge 304 meets performance criteria). In other words, at time t3, both the buffer transistor 202 and transistor 206 can serve as pulldown transistors to help pull output G(n) down to ground. The use of a dual pulldown arrangement can help the display achieve high refresh rates (e.g., refresh rates of 120 Hz and beyond). If transistor 206 is appropriately sized to provide the desired pulldown drive strength, buffer transistor 202 may be configured with a relatively small size to help reduce clock loading (e.g., to minimize the parasitic capacitive loading at clock routing path 216), which can help substantially reduce dynamic power consumption. As an example, transistor 206 may be five to ten times the size of transistor 202.
Transistor 220 is interposed between transistor 206 and clock routing path 218. In general, transistor 220 should be sized relatively small compared to the buffer transistor to minimize the amount of clock loading on path 218. As an example, transistor 220 may be five to ten times smaller than the size of transistor 202. Configured in this way, transistor 220 serves as a clock isolation circuit that isolates the large parasitic capacitance associated with transistor 206 from clock routing path 218, which also helps to reduce dynamic power consumption. In other words, transistor 206 can be sized sufficiently large without increasing clock loading because of isolation transistor 220. Moreover, it might be worth noting that node X is only asserted once per frame, so node Y is only driven high once per frame. As a result, large pulldown transistor 206 is not constantly exposed to a time-varying signal such as a clock signal, which helps to substantially improve its reliability over time.
Since transistor 202 is sized much smaller than a conventional gate driver output transistor (i.e., transistor 102 of
The circuit configuration of
The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. The foregoing embodiments may be implemented individually or in any combination.
This application claims the benefit of provisional patent application No. 62/188,259 filed on Jul. 2, 2015, which is hereby incorporated by reference herein in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
5949398 | Kim | Sep 1999 | A |
6545653 | Takahara et al. | Apr 2003 | B1 |
6894673 | Koga et al. | May 2005 | B2 |
7046224 | Monomohshi | May 2006 | B2 |
7242432 | Watanabe | Jul 2007 | B2 |
7406253 | Ueda et al. | Jul 2008 | B2 |
7443944 | Tobita et al. | Oct 2008 | B2 |
7477226 | Kim | Jan 2009 | B2 |
7532701 | Moon | May 2009 | B2 |
7639226 | Kim | Dec 2009 | B2 |
7696974 | Moon et al. | Apr 2010 | B2 |
7696975 | Yang et al. | Apr 2010 | B2 |
8362999 | Huang et al. | Jan 2013 | B2 |
8373483 | Daily | Feb 2013 | B2 |
8766961 | Huang et al. | Jul 2014 | B2 |
9318219 | Yang | Apr 2016 | B2 |
20060022933 | Endo | Feb 2006 | A1 |
20080198961 | Collins | Aug 2008 | A1 |
20080218502 | Lee | Sep 2008 | A1 |
20090167741 | Tsai | Jul 2009 | A1 |
20100171728 | Han | Jul 2010 | A1 |
20100238143 | Liu | Sep 2010 | A1 |
20100328281 | Okada | Dec 2010 | A1 |
20110193832 | Hirabayashi | Aug 2011 | A1 |
20120154322 | Yang et al. | Jun 2012 | A1 |
20120176360 | Yamashita | Jul 2012 | A1 |
20120229444 | Ochiai | Sep 2012 | A1 |
20130063404 | Jamshidi Roudbari | Mar 2013 | A1 |
20130328757 | Matsumoto et al. | Dec 2013 | A1 |
20140192039 | Wang | Jul 2014 | A1 |
20140300399 | Miyake | Oct 2014 | A1 |
20140354590 | Wang et al. | Dec 2014 | A1 |
20140361962 | Yamashita et al. | Dec 2014 | A1 |
20140362052 | McCaughan et al. | Dec 2014 | A1 |
20150036784 | Qing | Feb 2015 | A1 |
20150220194 | Lin et al. | Aug 2015 | A1 |
20150255014 | Lin | Sep 2015 | A1 |
20150269897 | Kitsomboonloha et al. | Sep 2015 | A1 |
20150294733 | Tan | Oct 2015 | A1 |
20150371716 | Shao | Dec 2015 | A1 |
20160125954 | Gu | May 2016 | A1 |
20160217757 | Tanaka | Jul 2016 | A1 |
20160293090 | Long | Oct 2016 | A1 |
20160300542 | Zhang | Oct 2016 | A1 |
20160314850 | Gu | Oct 2016 | A1 |
20160322116 | Jang | Nov 2016 | A1 |
Number | Date | Country |
---|---|---|
103455201 | Dec 2013 | CN |
Entry |
---|
Kitsomboonloha et al., U.S. Appl. No. 14/677,531, filed Apr. 2, 2015. |
Number | Date | Country | |
---|---|---|---|
20170004790 A1 | Jan 2017 | US |
Number | Date | Country | |
---|---|---|---|
62188259 | Jul 2015 | US |