Patent Grant
11488538
This relates generally to electronic devices with displays and, more particularly, to display driver circuitry for displays such as organic-light-emitting diode displays.
Electronic devices often include displays. For example, cellular telephones and portable computers include displays for presenting information to users.
Displays such as organic light-emitting diode displays have an array of display pixels based on light-emitting diodes. In this type of display, each display pixel includes a light-emitting diode and thin-film transistors for controlling application of a signal to the light-emitting diode to produce light.
The display includes row driver circuits configured to output control signals to the thin-film transistors within each display pixel. The row driver circuits generate one or more scan control signals and emission control signals for selectively enabling and disabling the thin-film transistors during different phases of operation of the display pixels. In low refresh rate displays, the row driver circuits need to output a low voltage signal during blanking times. In practice, however, one or more leakage paths within the row driver circuits may cause the low voltage signal to be inadvertently driven high. It is within this context that the embodiments herein arise.
An electronic device may include a display having an array of display pixels. The display pixels may receive data signals from display driver circuitry and may receive control signals (e.g., row control signals) from gate driver circuitry. The gate driver circuitry may include a chain of gate driver circuits.
Each gate driver circuit may include a scan driver circuit and a scan inverter circuit. The scan driver circuit may be configured to generate a scan signal, whereas the scan inverter circuit may be configured to receive the scan signal from the scan driver circuit and generate a corresponding inverted scan signal to a row of display pixels in the array.
The scan inverter circuit may include first, second, third, and fourth transistors coupled in series between a high power supply line and a low power supply line. The first and second transistors may have gate terminals configured to receive the scan signal from the scan driver circuit. The third and fourth transistors have gate terminals configured to receive the same clock signal.
The scan inverter circuit may further include a leakage reduction circuit having a first terminal connected to a source terminal of the second transistor and a second terminal connected to the low power supply terminal. In one suitable arrangement, the leakage reduction circuit has a third terminal connected to a drain terminal of the second transistor. In another suitable arrangement, the leakage reduction circuit has a third terminal connected to an output port of the scan inverter circuit. In yet another suitable arrangement, the leakage reduction circuit has a third terminal connected to a drain terminal of the second transistor and a fourth terminal connected to an output port of the scan inverter circuit.
An enable transistor may optionally be coupled between the scan driver circuit and the scan inverter circuit. The enable transistor may be turned on during a first scan mode when the scan driver circuit and the scan inverter circuit operate at the same frequency and may be turned off in a second scan mode when the scan driver circuit and the scan inverter circuit operate independently at different frequencies.
An illustrative electronic device of the type that may be provided with a display is shown in
Input-output circuitry in device 10 such as input-output devices 12 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 12 may include buttons, joysticks, scrolling wheels, touch pads, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user can control the operation of device 10 by supplying commands through input-output devices 12 and may receive status information and other output from device 10 using the output resources of input-output devices 12.
Input-output devices 12 may include one or more displays such as display 14. Display 14 may be a touch screen display that includes a touch sensor for gathering touch input from a user or display 14 may be insensitive to touch. A touch sensor for display 14 may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor, or other suitable touch sensor arrangements.
Control circuitry 16 may be used to run software on device 10 such as operating system code and applications. During operation of device 10, the software running on control circuitry 16 may display images on display 14 using an array of pixels in display 14.
Device 10 may be a tablet computer, laptop computer, a desktop computer, a display, a cellular telephone, a media player, a wristwatch device or other wearable electronic equipment such as a head-mounted device, or other suitable electronic device.
Display 14 may be an organic light-emitting diode display or may be a display based on other types of display technology. Configurations in which display 14 is an organic light-emitting diode display are sometimes described herein as an example. This is, however, merely illustrative. Any suitable type of display may be used in device 10, if desired.
Display 14 may have a rectangular shape (i.e., display 14 may have a rectangular footprint and a rectangular peripheral edge that runs around the rectangular footprint) or may have other suitable shapes. Display 14 may be planar or may have a curved profile.
A top plan view of a portion of display 14 is shown in
Display driver circuitry may be used to control the operation of pixels 22. The display driver circuitry may be formed from integrated circuits, thin-film transistor circuits, or other suitable electronic circuitry. Display driver circuitry 30 of
To display the images on display pixels 22, display driver circuitry 30 may supply image data to data lines D (e.g., data lines that run down the columns of pixels 22) while issuing clock signals and other control signals to supporting display driver circuitry such as gate driver circuitry 34 over path 38. If desired, circuitry 30 may also supply clock signals and other control signals to gate driver circuitry 34 on an opposing edge of display 14 (e.g., the gate driver circuitry may be formed on more than one side of the display pixel array).
Gate driver circuitry 34 (sometimes referred to as horizontal line control/driver circuitry or row control/driver circuitry) may be implemented as part of an integrated circuit and/or may be implemented using thin-film transistor circuitry. Horizontal/row control lines G in display 14 may carry gate line signals (scan line signals), emission enable control signals, and other horizontal control signals for controlling the pixels of each row. There may be any suitable number of horizontal control signals per row of pixels 22 (e.g., one or more row control lines, two or more row control lines, three or more row control lines, four or more row control lines, five or more row control lines, etc.).
In the example of
Control signals from display driver circuitry such as row driver circuitry 34 of
The pixel structure of
Display 14 may optionally be configured to support low refresh rate operation. Operating display 14 using a relatively low refresh rate (e.g., a refresh rate of 1 Hz, less than 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other suitable low frequency) may be suitable for applications outputting content that is static or nearly static and/or for applications that require minimal power consumption.
Scan driver circuit 500 may include thin-film transistors such as transistors M1-1, M1-2, and M2-8. Transistors M1-1 and M1-2 may be coupled in series between node Q2 and a terminal configured to receive the scan signal output from one of the previous gate driver circuit in the chain (e.g., signal SCAN(n-1) from the preceding gate driver row) or to receive a scan driver start pulse signal SP_SCAN. Transistors M1-1 and M1-2 may have gate terminals configured to receive a scan driver gate clock signal GCLK2_SCAN.
Transistors M2 and M3 are coupled in series between node Q2 and a high power supply terminal 590 (e.g., a positive power supply line on which positive power supply voltage VGH is provided). For example, power supply voltage VGH may be 5 V, 10 V, 15 V, 20 V, 5-15 V, more than 15 V, or other suitable high voltage level. Transistor M3 may have a gate terminal configured to receive another scan driver gate clock signal GCLK1_SCAN. Transistor M2 may have a gate terminal connected to node QB, which is complementary to node Q.
Transistors M7 and M8 are coupled in series between a node configured to receive signal GLK1_SCAN and power supply line 590. Transistor M8 has a gate terminal at node Q, which is coupled to node Q2 via transistor M6. Transistor M6 has a gate terminal configured to receive low power supply voltage VGL. For example, power supply voltage VGL may be 0 V, −5 V, −10 V, −15 V, −20 V, negative 5-15 V, less than 15 V, +1 V, +2 V, or other suitable low voltage level. Capacitor C1 may be coupled across the gate and source terminals of transistor M8. Transistor M7 may have a gate terminal connected to node QB. Capacitor C2 may be coupled across the gate and source terminals of transistor M7. A scan driver circuit output signal SCAN(n) may be provided at the node interposed between transistors M7 and M8. The terms “source” and “drain” terminals of a transistor may sometimes be used interchangeably.
Transistor M5 may have a source terminal configured to receive low voltage VGL, a drain terminal connected to node QB, and a gate terminal configured to receive clock signal GCLK2_SCAN. Transistor M4 may have a first source-drain terminal configured to receive signal GCLK2_SCAN, a second source-drain terminal connected to node QB, and a gate terminal connected to node Q2.
Scan inverter circuit 502 may be configured to invert the signal SCAN(n) generated at the output of circuit 500 to generate a corresponding inverted output SCAN_INV(n). Scan inverter circuit 502 may include thin-film transistors such as transistors P1-1, P1-2, P2-1, P2-2, and P3-P5. Transistors P1-1 and P1-2 may be coupled in series between low power supply line 592 (e.g., a low power supply terminal on which VGL is provided) and node Q2′. Transistors P1-1 and P1-2 may have gate terminals configured to receive a scan inverter gate clock signal GCLK1_INV.
Transistors P2-1 and P2-2 may be coupled in series between node Q2′ and power supply terminal 590. Transistors P2-1 and P2-2 may have gate terminals that are shorted together and connected to node Y. Node Y may be configured to selectively receive the SCAN(n) signal output from scan driver circuit 500.
Transistors P4 and P5 may be coupled in series between low power supply terminal 592 and high power supply terminal 590. Transistor P4 may have a gate terminal at node Q′, which is coupled to node Q2′ via transistor P3. Transistor P3 has a gate terminal configured to receive low power supply voltage VGL. Capacitor CQ may be coupled across the gate and source terminals of transistor P4. Transistor P5 may have a gate terminal connected to node Y. The scan inverter circuit output signal SCAN_INV(n) may be provided at the node interposed between transistors P4 and P5.
In accordance with an embodiment, a mode switching transistor such as transistor 504 may be coupled between scan driver circuit 500 and scan inverter circuit 502. In the example of
The use of transistors 504 and 506 enable gate driver circuit 35 to be operated in at least two different modes, as illustrated in
When configured in the second scan mode 602, the enable transistor 504 is turned off by deasserting signal EN (e.g., by driving signal EN high assuming transistor 504 is a p-type transistor). Driving signal EN high to turn off transistor 504 will force inverted signal ENB low, which turns on auxiliary p-type transistor 506. Activating transistor 506 will pull node Y high, which turns off transistors P5, P2-1, and P2-2. Deactivating transistor 504 decouples the scan driver circuit 500 from the scan inverter circuit 502 and allows them to operate independently at different refresh rates or at different operating frequencies. For example, scan driver circuit 500 might output SCAN(n) signal pulses at 60 Hz while scan inverter circuit 502 output SCAN_INV(n) signal pulses at a much lower rate of 1 Hz.
The example of
In certain embodiments, gate driver circuit 35 may be used to control semiconducting-oxide transistor Tsw of
In accordance with an embodiment, a gate driver circuit may be provided with additional circuitry configured to reduce the leakage current.
Scan inverter circuit 702 may be configured to invert the signal SCAN(n) generated at the output of circuit 700 to generate a corresponding inverted output SCAN_INV(n). Scan inverter circuit 702 may include thin-film transistors such as transistors P1-1, P1-2, P2-1, P2-2, and P3-P7. Transistors P1-1 and P1-2 may be coupled in series between low power supply line 792 (e.g., a low power supply terminal on which VGL is provided) and node Q2′. Transistors P1-1 and P1-2 may have gate terminals configured to receive scan inverter gate clock signal GCLK1_INV.
Transistors P2-1 and P2-2 may be coupled in series between node Q2′ and power supply terminal 790 (e.g., a power supply line on which high power supply voltage VGH or another positive power supply voltage VSH is provided). Power supply voltage VSH may be less than VGH (as an example). Transistors P2-1 and P2-2 may have gate terminals that are shorted together and connected to node Y. Node Y may be configured to selectively receive the SCAN(n) signal output from scan driver circuit 500. Gate driver circuit 35 may optionally be provided with transistors 704 and 706, which can be selectively enabled/disabled to operate circuit 35 in the different scan modes described in connection with
Transistors P4 and P5 may be coupled in series between low power supply terminal 792 and high power supply terminal 790. Transistor P4 may have a gate terminal at node Q′, which is coupled to node Q2′ via transistor P3. Transistor P3 has a gate terminal configured to receive low power supply voltage VGL. Capacitor CQ may be coupled across the gate and source terminals of transistor P4. Transistor P5 may have a gate terminal connected to node Y. The scan inverter circuit output signal SCAN_INV(n) may be provided at the node interposed between transistors P4 and P5.
The example of
Furthermore, transistors P6 and P7 may be coupled in series between low power supply line 792 and the node interposed between transistors P2-1 and P2-2. Transistors P6 and P7 may have gate terminals that are connected to node Q2′ via connection path 710. As described above, nodes Q′ and Q2′ should be kept low during blanking times T_blank. If node Q2′ is low, transistors P6 and P7 will be turned on to pull the source node of transistor P2-1 down to VGL. As a result, the drain-to-source voltage VDS of transistor P2-1 will be kept low or minimized during blanking times, which will dramatically reduce the amount of leakage current through transistor P2-1. Transistors P6 and P7 connected in this way to suppress leakage may be said to be connected in a “negative feedback” arrangement. Transistors P6 and P7 may therefore sometimes be referred to as a leakage reduction or leakage suppression circuit within scan inverter circuit 702.
Scan inverter circuit 802 may be configured to invert the signal SCAN(n) generated at the output of circuit 800 to generate a corresponding inverted output SCAN_INV(n). Scan inverter circuit 802 may include thin-film transistors such as transistors P1-1, P1-2, P2-1, P2-2, and P3-P7. Transistors P1-1 and P1-2 may be coupled in series between low power supply line 892 (e.g., a low power supply terminal on which VGL is provided) and node Q2′. Transistors P1-1 and P1-2 may have gate terminals configured to receive scan inverter gate clock signal GCLK1_INV.
Transistors P2-1 and P2-2 may be coupled in series between node Q2′ and power supply terminal 890 (e.g., a power supply line on which high power supply voltage VGH or another positive power supply voltage VSH is provided). Power supply voltage VSH may be less than VGH (as an example). Transistors P2-1 and P2-2 may have gate terminals that are shorted together and connected to node Y. Node Y may be configured to selectively receive the SCAN(n) signal output from scan driver circuit 800. Gate driver circuit 35 may optionally be provided with transistors 804 and 806, which can be selectively enabled/disabled to operate circuit 35 in the different scan modes described in connection with
Transistors P4 and P5 may be coupled in series between low power supply terminal 892 and high power supply terminal 890. Transistor P4 may have a gate terminal at node Q′, which is coupled to node Q2′ via transistor P3. Transistor P3 has a gate terminal configured to receive low power supply voltage VGL. Capacitor CQ may be coupled across the gate and source terminals of transistor P4. Transistor P5 may have a gate terminal connected to node Y. The scan inverter circuit output signal SCAN_INV(n) may be provided at the node interposed between transistors P4 and P5.
The example of
Furthermore, leakage reduction/suppression transistors P6 and P7 may be coupled in series between low power supply line 892 and the node interposed between transistors P2-1 and P2-2. Transistors P6 and P7 may have gate terminals that are connected to the scan inverter output node via connection path 810. As described above, node Q′ should be kept low during blanking times T_blank. If node Q′ is low, transistor P4 will be turned on to pull the scan inverter output node down to VGL. As a result, transistors P6 and P7 will be turned on to pull the source terminal of transistor P2-1 down to VGL, which would minimize the drain-to-source voltage VDS of transistor P2-1, thereby dramatically reducing the amount of leakage current through transistor P2-1 during blanking times. Transistors P6 and P7 may therefore sometimes be referred to as a leakage reduction or leakage suppression circuit within scan inverter circuit 802.
Scan inverter circuit 902 may be configured to invert the signal SCAN(n) generated at the output of circuit 900 to generate a corresponding inverted output SCAN_INV(n). Scan inverter circuit 902 may include thin-film transistors such as transistors P1-1, P1-2, P2-1, P2-2 P3, P4, P5-1, P5-2, and P6-P9. Transistors P1-1 and P1-2 may be coupled in series between low power supply line 992 (e.g., a low power supply terminal on which VGL is provided) and node Q2′. Transistors P1-1 and P1-2 may have gate terminals configured to receive scan inverter gate clock signal GCLK1_INV.
Transistors P2-1 and P2-2 may be coupled in series between node Q2′ and power supply terminal 990 (e.g., a power supply line on which high power supply voltage VGH or another positive power supply voltage VSH is provided). Power supply voltage VSH may be less than VGH (as an example). Transistors P2-1 and P2-2 may have gate terminals that are shorted together and connected to node Y. Node Y may be configured to selectively receive the SCAN(n) signal output from scan driver circuit 900. Gate driver circuit 35 may optionally be provided with transistors 904 and 906, which can be selectively enabled/disabled to operate circuit 35 in the different scan modes described in connection with
Transistors P4, P5-1, and P5-2 may be coupled in series between low power supply terminal 992 and high power supply terminal 990. Transistor P4 may have a gate terminal at node Q′, which is coupled to node Q2′ via transistor P3. Transistor P3 has a gate terminal configured to receive low power supply voltage VGL. Capacitor CQ may be coupled across the gate and source terminals of transistor P4. Transistors P5-1 and P5-2 may have gate terminals connected to node Y. The scan inverter circuit output signal SCAN_INV(n) may be provided at the node interposed between transistors P4 and P5-1.
The example of
Furthermore, transistors P6-P7 may be coupled in series between low power supply line 992 and the node interposed between transistors P2-1 and P2-2, whereas transistors P8-P9 may be coupled in series between low power supply line 992 and the node interposed between transistors P5-1 and P5-2. Transistors P6-P9 (collectively referred to as a leakage reduction or leakage suppression circuit) may have gate terminals that are connected to the scan inverter output node via connection path 910. As described above, node Q′ should be kept low during blanking times T_blank. If node Q′ is low, transistor P4 will be turned on to pull the scan inverter output node down to VGL. As a result, transistors P6-P7 will be turned on to pull the source terminal of transistor P2-1 down to VGL while transistors P7-P8 will be turned on to pull the source terminal of transistor P5-1 down to VGL, which would force the drain-to-source voltage VDS of transistors P2-1 and P5-1 to be low, thereby dramatically reducing the amount of leakage currents flowing through transistors P2-1 and P5-1, respectively. Configured in this way, the leakage currents through both pull-up paths through transistors P2-1 and P5-1 in scan inverter circuit 902 can be reduced. Transistors P6-P9 may therefore sometimes be referred to as a leakage reduction or leakage suppression circuit within scan inverter circuit 902.
Scan inverter circuit 1002 may be configured to invert the signal SCAN(n) generated at the output of circuit 1000 to generate a corresponding inverted output SCAN_INV(n). Scan inverter circuit 1002 may include thin-film transistors such as transistors P1-1, P1-2, P2-1, P2-2 P3, P4, P5-1, P5-2, and P6-P9. Transistors P1-1 and P1-2 may be coupled in series between low power supply line 1092 (e.g., a low power supply terminal on which VGL is provided) and node Q2′. Transistors P1-1 and P1-2 may have gate terminals configured to receive scan inverter gate clock signal GCLK1_INV.
Transistors P2-1 and P2-2 may be coupled in series between node Q2′ and power supply terminal 1090 (e.g., a power supply line on which high power supply voltage VGH or another positive power supply voltage VSH is provided). Power supply voltage VSH may be less than VGH (as an example). Transistors P2-1 and P2-2 may have gate terminals that are shorted together and connected to node Y. Node Y may be configured to selectively receive the SCAN(n) signal output from scan driver circuit 1000. Gate driver circuit 35 may optionally be provided with transistors 1004 and 1006, which can be selectively enabled/disabled to operate circuit 35 in the different scan modes described in connection with
Transistors P4, P5-1, and P5-2 may be coupled in series between low power supply terminal 1092 and high power supply terminal 1090. Transistor P4 may have a gate terminal at node Q′, which is coupled to node Q2′ via transistor P3. Transistor P3 has a gate terminal configured to receive low power supply voltage VGL. Capacitor CQ may be coupled across the gate and source terminals of transistor P4. Transistors P5-1 and P5-2 may have gate terminals connected to node Y. The scan inverter circuit output signal SCAN_INV(n) may be provided at the node interposed between transistors P4 and P5-1.
The example of
Furthermore, transistors P6-P7 may be coupled in series between low power supply line 1092 and the node interposed between transistors P2-1 and P2-2, whereas transistors P8-P9 may be coupled in series between low power supply line 1092 and the node interposed between transistors P5-1 and P5-2. Leakage reducing transistors P6 and P7 may have gate terminals connected to node Q2′ via connection path 1012, whereas leakage reducing transistors P8 and P9 may have gate terminals connected to the scan inverter output node via connection path 1010. As described above, nodes Q2′ and Q′ should be kept low during blanking times T_blank. If node Q′ is low, transistor P4 will be turned on to pull the scan inverter output node down to VGL and will also pull node Q2′ low as well. As a result, transistors P6-P7 will be turned on to pull the source terminal of transistor P2-1 down to VGL while transistors P7-P8 will be turned on to pull the source terminal of transistor P5-1 down to VGL, which would force the drain-to-source voltage VDS of transistors P2-1 and P5-1 to be low, thereby dramatically reducing the amount of leakage currents flowing through transistors P2-1 and P5-1, respectively. Configured in this way, the leakage currents through both pull-up paths through transistors P2-1 and P5-1 in scan inverter circuit 902 can be reduced. Transistors P6-P9 may therefore sometimes be referred to as a leakage reduction or leakage suppression circuit within scan inverter circuit 1002.
Although the methods of operations are described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.
The foregoing is merely illustrative and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented individually or in any combination.
This application claims the benefit of provisional patent application No. 63/033,024, filed Jun. 1, 2020, which is hereby incorporated by reference herein in its entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 8937489 | Park et al. | Jan 2015 | B2 |
| 9319036 | Chang et al. | Apr 2016 | B2 |
| 9805657 | Kwon et al. | Oct 2017 | B2 |
| 10692437 | Liu | Jun 2020 | B2 |
| 20120169954 | Liu | Jul 2012 | A1 |
| 20160005359 | Kwon | Jan 2016 | A1 |
| 20160260378 | Tsuge | Sep 2016 | A1 |
| 20180348959 | Lin | Dec 2018 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 63033024 | Jun 2020 | US |
