This application claims priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2016-0074435, filed on Jun. 15, 2016 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated by reference herein.
The present disclosure generally relates to displaying images, and more particularly to display panels and display apparatuses including the display panels.
A liquid crystal display apparatus is a type of flat panel display (FPD), which has been widely used in recent years. For example, FPDs may include, but are not limited to, a liquid crystal display (LCD), a plasma display panel (PDP) and an organic light emitting display (OLED).
A display apparatus includes a display panel in which a plurality of pixels are connected to respective gate lines and to respective data lines crossing the gate lines which are formed on the display panel. There are also circuits provided, for example, a gate driver circuit configured for outputting gate signals to the gate lines and a data driver circuit configured for outputting data signals to the data lines. Display panels designed with a reduced number of data lines tend to display a higher quality image and operate more reliably.
Accordingly, at least one exemplary embodiment of the inventive concept provides a display panel capable of enhancing display quality without excessive design change.
At least one exemplary embodiment of the inventive concept provides a display apparatus including the display panel.
According to exemplary embodiments of the inventive concept, a display panel includes a plurality of pixels arranged in a matrix including a plurality of pixel rows and a plurality of pixel columns, in which each pixel of the plurality of pixels has a short side and a long side that is longer than the short side; a plurality of data lines extending in a first direction substantially parallel with the plurality of pixel columns along the short side of the pixels, each of the data lines is connected to at least two adjacent pixels included in a single pixel row. The plurality of gate lines extend in a second direction parallel with the plurality of pixel rows. Each of the gate lines is connected to at least one pixel included in a single pixel row. At least two of the gate lines are disposed between two adjacent pixel rows. The gate driver generates a plurality of gate signals for driving the plurality of gate lines. A plurality of terminals receive the plurality of gate signals to transmit the plurality of gate signals to the plurality of gate lines. Some of the terminals are connected to some of the gate lines with a cross-coupled structure.
In an exemplary embodiment of the inventive concept, the plurality of gate lines may include, for example, first, second, third, fourth, fifth and sixth gate lines that are sequentially arranged in the first direction. The plurality of terminals may include first, second, third, fourth, fifth and sixth terminals that sequentially receive first, second, third, fourth, fifth and sixth gate signals among the plurality of gate signals, respectively. The first terminal may be connected to the first gate line, the second terminal may be connected to the third gate line, the third terminal may be connected to the fifth gate line, the fourth terminal may be connected to the second gate line, the fifth terminal may be connected to the fourth gate line, and the sixth terminal may be connected to the sixth gate line.
In an exemplary embodiment of the inventive concept, the display panel may further include a first connection pattern, a second connection pattern, a third connection pattern, a fourth connection pattern, a fifth connection pattern and a sixth connection pattern. The first connection pattern may connect, for example, the first terminal with the first gate line. The second connection pattern may connect the second terminal with the third gate line. The third connection pattern may connect a wiring connected to the third terminal with the fifth gate line. The fourth connection pattern may connect the fourth terminal with the second gate line. The fifth connection pattern may connect the fifth terminal with the fourth gate line. The sixth connection pattern may connect the sixth terminal with the sixth gate line. The second connection pattern may overlap the second gate line, and the fourth and fifth connection patterns may overlap the wiring connected to the third terminal.
In an exemplary embodiment of the inventive concept, the plurality of pixels may include first and second pixels, third and fourth pixels, and fifth and sixth pixels. The first and second pixels may be adjacent to each other, may be included in a first pixel row among the plurality of pixel rows, and may be connected to the first and second gate lines, respectively. The arrangement of, for example, the third and fourth pixels may be adjacent to each other, may be adjacent to the first and second pixels, may be included in a second pixel row adjacent to the first pixel row among the plurality of pixel rows, and may be connected to the third and fourth gate lines, respectively. The fifth and sixth pixels, for example, may be adjacent to each other, may be adjacent to the third and fourth pixels, may be included in a third pixel row adjacent to the second pixel row from among the plurality of pixel rows, and may be connected to the fifth and sixth gate lines, respectively.
In an exemplary embodiment of the inventive concept, during a first frame period for displaying a first frame image, the first through sixth gate signals may be sequentially activated, for example, in an order of the first, second, third, fourth, fifth and sixth gate signals, and the first through sixth pixels may be sequentially driven, for example, in an order of the first, third, fifth, second, fourth and sixth pixels based on the activated first through sixth gate signals.
In an exemplary embodiment of the inventive concept, the first through sixth gate signals may have an ON level during at least two consecutive or successive horizontal periods, and activation periods of the first through sixth gate signals may partially overlap each other. In another exemplary embodiment, the ON level comprises at least six consecutive or horizontal periods.
In an exemplary embodiment of the inventive concept, the activation periods of the first through sixth gate signals may partially overlap each other.
In an exemplary embodiment of the inventive concept, during a second frame period for displaying a second frame image after the first frame period, the first through sixth gate signals may be sequentially activated, for example, in an order of the fourth, fifth, sixth, first, second and third gate signals, and the first through sixth pixels may be sequentially driven, for example, in an order of the second, fourth, sixth, first, third and fifth pixels based on the activated first through sixth gate signals.
In an exemplary embodiment of the inventive concept, the second and third gate lines may be disposed between the first and second pixel rows. The fourth and fifth gate lines may be disposed between the second and third pixel rows.
In an exemplary embodiment of the inventive concept, the first and second gate lines may be disposed between the first and second pixel rows. The third and fourth gate lines may be disposed between the second and third pixel rows.
In an exemplary embodiment of the inventive concept, the plurality of data lines may include first and second data lines that are adjacent to each other. The first, second, fifth and sixth pixels may be connected to the first data line, and the third and fourth pixels may be connected to the second data line.
In an exemplary embodiment of the inventive concept, the plurality of gate lines may include first through 6*n gate lines that are sequentially arranged in the first direction, where n is a natural number equal to or greater than two. The plurality of terminals may include, for example, first through 6*n terminals that sequentially receive first through 6*n gate signals among the plurality of gate signals, respectively. A k-th terminal among the first through 6*n terminals may be connected to a (2k−1)-th gate line, where k is a natural number equal to or greater than one and equal to or less than 3*n. A m-th terminal among the first through 6*n terminals may be connected to a 2*(m−3n)-th gate line, where m is a natural number equal to or greater than (3n+1) and equal to or less than 6*n.
In an exemplary embodiment of the inventive concept, the plurality of pixels may be disposed in a display region of the display panel. In addition, the gate driver and the plurality of terminals may be disposed in a peripheral region surrounding the display region of the display panel.
According to exemplary embodiments of the inventive concept, a display apparatus includes a gate driver and a display panel. The gate driver may generate a plurality of gate signals. The display panel is connected to the gate driver. The display panel includes a plurality of pixels, a plurality of data lines, a plurality of gate lines and a plurality of terminals. The plurality of pixels are arranged to form a plurality of pixel rows and a plurality of pixel columns. The plurality of data lines may extend in a first direction parallel with the plurality of pixel columns. Each of the data lines may be connected to at least two adjacent pixels included in a single pixel row. The plurality of gate lines extend in a second direction parallel with the plurality of pixel rows and are driven by the plurality of gate signals. Each of the gate lines is connected to at least one pixel included in a single pixel row. At least two of the gate lines may be disposed between two adjacent pixel rows. The plurality of terminals receives the plurality of gate signals to transmit the plurality of gate signals to the plurality of gate lines. Some of the terminals may be connected to some of the gate lines with a cross-coupled structure.
In an exemplary embodiment of the inventive concept, the plurality of gate lines may include first, second, third, fourth, fifth and sixth gate lines that are sequentially arranged in the first direction. The plurality of terminals may include, for example, first, second, third, fourth, fifth and sixth terminals that sequentially receive first, second, third, fourth, fifth and sixth gate signals among the plurality of gate signals, respectively. The first terminal may be connected to the first gate line, the second terminal may be connected to the third gate line, the third terminal may be connected to the fifth gate line, the fourth terminal may be connected to the second gate line, the fifth terminal may be connected to the fourth gate line, and the sixth terminal may be connected to the sixth gate line.
In an exemplary embodiment of the inventive concept, the display panel may further include a first connection pattern, a second connection pattern, a third connection pattern, a fourth connection pattern, a fifth connection pattern and a sixth connection pattern.
The first connection pattern may connect the first terminal with the first gate line. The second connection pattern may connect the second terminal with the third gate line. The third connection pattern may connect a wiring connected to the third terminal with the fifth gate line. The fourth connection pattern may connect the fourth terminal with the second gate line. The fifth connection pattern may connect the fifth terminal with the fourth gate line. The sixth connection pattern may connect the sixth terminal with the sixth gate line. The second connection pattern may overlap the second gate line, and the fourth and fifth connection patterns may overlap the wiring connected to the third terminal.
In an exemplary embodiment of the inventive concept, the plurality of pixels may include first and second pixels, third and fourth pixels, and fifth and sixth pixels. The first and second pixels may be adjacent to each other, may be included in a first pixel row among the plurality of pixel rows, and may be connected to the first and second gate lines, respectively. The third and fourth pixels may be adjacent to each other, may be adjacent to the first and second pixels, may be included in a second pixel row adjacent to the first pixel row among the plurality of pixel rows, and may be connected to the third and fourth gate lines, respectively. The fifth and sixth pixels may be adjacent to each other, may be adjacent to the third and fourth pixels, may be included in a third pixel row adjacent to the second pixel row among the plurality of pixel rows, and may be connected to the fifth and sixth gate lines, respectively.
In an exemplary embodiment of the inventive concept, during a first frame period for displaying a first frame image, the first through sixth gate signals may be sequentially activated in an order of the first, second, third, fourth, fifth and sixth gate signals, and the first through sixth pixels may be sequentially driven in an order of the first, third, fifth, second, fourth and sixth pixels based on the activated first through sixth gate signals.
In an exemplary embodiment of the inventive concept, during a second frame period for displaying a second frame image after the first frame period, the first through sixth gate signals may be sequentially activated in an order of the fourth, fifth, sixth, first, second and third gate signals, and the first through sixth pixels may be sequentially driven in an order of the second, fourth, sixth, first, third and fifth pixels based on the activated first through sixth gate signals.
In an exemplary embodiment of the inventive concept, the second and third gate lines may be disposed between the first and second pixel rows, and the fourth and fifth gate lines may be disposed between the second and third pixel rows. Or, the first and second gate lines may be disposed between the first and second pixel rows, and the third and fourth gate lines may be disposed between the second and third pixel rows.
In an exemplary embodiment of the inventive concept, the plurality of gate lines may include first through 6*n gate lines that are sequentially arranged in the first direction, where n is a natural number equal to or greater than two. The plurality of terminals may include first through 6*n terminals that sequentially receive first through 6*n gate signals among the plurality of gate signals, respectively. A k-th terminal among the first through 6*n terminals may be connected to a (2k−1)-th gate line, where k is a natural number equal to or greater than one and equal to or less than 3*n. A m-th terminal among the first through 6*n terminals may be connected to a 2*(m−3n)-th gate line, where m is a natural number equal to or greater than (3n+1) and equal to or less than 6*n.
In an exemplary embodiment of the inventive concept, a display panel may include a plurality of pixels in which each pixel has a first side comprising a short-side and a second side comprising a long-side substantially perpendicular to the short side, the plurality of pixels arranged in matrix including a plurality of pixel rows and a plurality of pixel columns; a plurality of data lines extending substantially parallel to a short-side direction of the pixels, and each of the data lines is connected to at least two adjacent pixels in one of the plurality of pixel rows; and a plurality of gate lines extending substantially parallel to a long-side direction of the pixels, each of the gate lines is connected to at least one pixel included in a single pixel row, and at least two of the gate lines are disposed between two adjacent pixel rows.
In an exemplary embodiment of the inventive concept, a plurality of terminals may be configured to receive a plurality of gate signals to transmit a plurality of gate signals to the plurality of gate lines, wherein one or more of the plurality of terminals is connected respectively with one of the plurality of gate lines with a cross-coupled structure.
In an exemplary embodiment of the inventive concept, the plurality of gate lines may include at least six gate lines that are sequentially arranged in the short-side direction.
In the display panel and the display apparatus according to exemplary embodiments of the inventive concepts, the data lines may extend in a direction parallel with a short side of each pixel, and thus the number of the data lines may be reduced. In addition, a single data line may be shared by at least two adjacent pixels included in a single pixel row, and thus the number of the data lines may also be reduced. Further, in the display panel and the display apparatuses having a configuration of reducing the number of the data lines, some of the terminals may be connected to some of the gate lines with a cross-coupled structure, and thus a driving order of the gate lines may be efficiently changed without excessive design change.
Illustrative, non-limiting exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Various exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings, in which embodiments are shown. This inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout this application.
Referring to
The display panel 100 operates (e.g., display an image) based on output image data DAT. The display panel 100 includes a plurality of pixels PX, a plurality of data lines DL, a plurality of gate lines GL and a plurality of terminals 120.
The plurality of pixels PX are arranged to form a plurality of pixel rows PR and a plurality of pixel columns PC. For example, the plurality of pixels PX may be arranged in a matrix form, as shown in
With continued reference to
Each of the plurality of gate lines GL extends in the first direction DR1 parallel with the plurality of pixel rows PR. The plurality of gate lines GL are driven by a plurality of gate signals that are generated from the gate driver 300. For example, each of the gate lines GL is connected to at least one pixel included in a single pixel row, and at least two of the gate lines GL are disposed between two adjacent pixel rows. For example, pixels included in a single pixel row may be connected to at least two adjacent gate lines, and then may receive gate signals through at least two adjacent gate lines.
The plurality of terminals 120 receive the plurality of gate signals from the gate driver 300 to transmit the plurality of gate signals to the plurality of gate lines GL. Each of the terminals 120 is electrically connected to a respective one of the gate lines GL, and some of the terminals 120 are connected to some of the gate lines GL with a cross-coupled structure. The cross-coupled structure according to exemplary embodiments will be described with reference to
In some exemplary embodiments of the inventive concept, the plurality of pixels PX may be disposed in a display region of the display panel 100, and the plurality of terminals 120 may be disposed in a peripheral region of the display panel 100. The peripheral region may partially or fully surround the display region. For example, the plurality of terminals 120 may be disposed in the peripheral region of the display panel, and may be adjacent to a first side (e.g., a relatively short side on the left) of the display panel 100.
The timing controller 200 controls an operation of the display panel 100, the gate driver 300 and the data driver 400. The timing controller 200 receives an input image data IDAT and an input control signal ICONT from an external device (e.g., a host or a graphic processor). The input image data IDAT may include a plurality of pixel data for the plurality of pixels PX. The input control signal ICONT may include a master clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, etc.
The timing controller 200, for example, may generate the output image data DAT based on the input image data IDAT. For example, the timing controller 200 may selectively perform an image quality compensation, a spot compensation, an adaptive color correction (ACC), and/or a dynamic capacitance compensation (DCC) on the input image data IDAT to generate the output image data DAT. The timing controller 200 may generate a first control signal GCONT and a second control signal DCONT based on the input control signal ICONT. For example, the first control signal GCONT may include, for example, a vertical start signal, a gate clock signal, etc. The second control signal DCONT may include, for example, a horizontal start signal, a data clock signal, a polarity control signal, a data load signal, etc.
With continued reference to
The data driver 400 generates the plurality of data voltages (e.g., analog voltages) for driving the data lines DL based on the output image data DAT (e.g., digital data) and the second control signal DCONT. For example, the data driver 400 may sequentially provide the data voltages to a plurality of lines (e.g., horizontal lines) in the display panel 100 through the data lines DL. For example, the data driver 400 may include structure such as a shift register, a data latch, an analog-to-digital converter and an output buffer.
Referring to
The display apparatus 10a of
The gate driver 300a may be an amorphous silicon gate (ASG) unit that is integrated in the display panel 100a. In some exemplary embodiments, the plurality of pixels PX may be disposed in a display region of the display panel 100a, and the gate driver 300a and the plurality of terminals 120 may be disposed in a peripheral region of the display panel 100a. The peripheral region may surround the display region. For example, the gate driver 300a may be disposed in the peripheral region, and may be adjacent to a first side (e.g., a relatively short side on the left) of the display panel 100a. The plurality of terminals 120 may be disposed in peripheral region between the gate driver 300a and the display region.
The timing controller 200 may be mounted, for example, on the PCB 201. The data driver 400 may be mounted on the FPCB 401. The FPCB 401 may electrically connect the PCB 201 with the display panel 100a. For example, the PCB 201 and the FPCB 401 may be electrically connected by an anisotropic conductive film (ACF), and the FPCB 401 and the display panel 100a may be electrically connected by the ACF. For example, the FPCB 401 may be adjacent to a second side (e.g., a relatively long side on the upper) of the display panel 100a crossing the first side of the display panel 100a. In other words, the data driver 400 may be connected to the display panel 100a in a tape carrier package (TCP) type.
Although
Although not illustrated in
In the display apparatuses 100 and 100a according to exemplary embodiments, shown in
Referring to
Each of the first through sixth gate lines GL1˜GL6 may extend in a first direction DR1 (see
Each of the first through sixth pixels P11-P16 may be included in a respective one pixel row and a respective one pixel column. For example, the first and second pixels P11 and P12 may be included in a first pixel row, and may be adjacent to each other. The third and fourth pixels P13 and P14 may be included in a second pixel row, and may be adjacent to each other. The fifth and sixth pixels P15 and P16 may be included in a third pixel row, and may be adjacent to each other. With the aforementioned arrangement, the second pixel row may be adjacent to the first pixel row, and the third pixel row may be adjacent to the second pixel row. The first, third and fifth pixels P11, P13 and P15 may be included in a first pixel column. The second, fourth and sixth pixels P12, P14 and P16, for example, may be included in a second pixel column that is adjacent to the first pixel column.
Each of the first through sixth pixels P11˜P16 may be electrically connected to a respective one of the first through sixth gate lines GL1˜GL6 and a respective one of the first and second data lines DL1 and DL2. For example, the first and second pixels P11 and P12 may be electrically connected to the first data line DL1, and may be electrically connected to the first and second gate lines GL1 and GL2, respectively. The third and fourth pixels P13 and P14 may be electrically connected to the second data line DL2, and may be electrically connected to the third and fourth gate lines GL3 and GL4, respectively. The fifth and sixth pixels P15 and P16 may be, for example, electrically connected to the first data line DL1, and may be electrically connected to the fifth and sixth gate lines GL5 and GL6, respectively.
The first and second gate lines GL1 and GL2 may be connected to the pixels P11 and P12 that are included in the first pixel row. The first gate line GL1 may be disposed at a first side (e.g., an upper side) with respect to the first pixel row, and the second gate line GL2 may be disposed at a second side (e.g., a lower side) with respect to the first pixel row. In this example, the first gate line GL1 may be referred to as a “top gate line” of the first pixel row, and the second gate line GL2 may be referred to as a “bottom gate line” of the first pixel row. Similarly, the third and fourth gate lines GL3 and GL4 may be referred to as a top gate line of the second pixel row and a bottom gate line of the second pixel row, respectively, and the fifth and sixth gate lines GL5 and GL6 may be referred to as a top gate line of the third pixel row and a bottom gate line of the third pixel row, respectively.
In some exemplary embodiments of the inventive concept, the second and third gate lines GL2 and GL3 may be disposed between the first and second pixel rows, and the fourth and fifth gate lines GL4 and GL5 may be disposed between the second and third pixel rows.
In
The first through sixth terminals 120a˜120f may sequentially receive first, second, third, fourth, fifth and sixth gate signals G1, G2, G3, G4, G5 and G6. Similar to the first through sixth gate lines GL1-GL6, the first through sixth terminals 120a˜120f may be sequentially arranged in the second direction DR2.
In some exemplary embodiments, the first terminal 120a may be connected to the first gate line GL1, the second terminal 120b may be connected to the third gate line GL3, the third terminal 120c may be connected to the fifth gate line GL5, the fourth terminal 120d may be connected to the second gate line GL2, the fifth terminal 120e may be connected to the fourth gate line GL4, and the sixth terminal 120f may be connected to the sixth gate line GL6. In other words, the middle terminals 120b˜120e other than the first and last terminals 120a and 120f may be cross-coupled to the middle gate lines GL2˜GL5 other than the first and last gate lines GL1 and GL6. In an example of
Based on the cross-coupled structure in
In some exemplary embodiments, each of the first and second pixels P11 and P12 may be a red pixel outputting red light, each of the third and fourth pixels P13 and P14 may be a green pixel outputting green light, and each of the fifth and sixth pixels P15 and P16 may be a blue pixel outputting blue light.
In some exemplary embodiments, the first repeating pixel group RPG1 may be repeated in the first and second directions DR1 and DR2 to form the display panel according to exemplary embodiments. In other exemplary embodiments, a second repeating pixel group in which the first, second, fifth and sixth pixels P11, P12, P15 and P16 are connected to the second data line DL2, and the third and fourth pixels P13 and P14 are connected to the first data line DL1 may exist, and then the first repeating pixel group RPG1 and the second repeating pixel group may be alternately repeated in the first and second directions DR1 and DR2 to form the display panel according to exemplary embodiments. In the display panel according to exemplary embodiments, the connection of the terminals 120a˜120f with the gate lines GL1˜GL6 in
Referring now to
As shown in
Each of the first through sixth connection patterns 130a˜130f may electrically connect a respective one of the first through sixth terminals 120a˜120f with a respective one of the first through sixth gate lines GL1˜GL6. For example, the first connection pattern 130a may electrically connect the first terminal 120a with the first gate line GL1, and may be electrically connected to the first wiring 142a and the first gate line GL1 through the contacts 132a and 134a, respectively. The second connection pattern 130b may electrically connect the second terminal 120b with the third gate line GL3, and may be electrically connected to the second wiring 142b and the third gate line GL3 through the contacts 132b and 134b, respectively. The third connection pattern 130c may electrically connect the third terminal 120c with the fifth gate line GL5, and may be electrically connected to the third wiring 142c and the fifth gate line GL5 through the contacts 132c and 134c, respectively. The fourth connection pattern 130d may electrically connect the fourth terminal 120d with the second gate line GL2, and may be electrically connected to the fourth wiring 142d and the second gate line GL2 through the contacts 132d and 134d, respectively. The fifth connection pattern 130e may electrically connect the fifth terminal 120e with the fourth gate line GL4, and may be electrically connected to the fifth wiring 142e and the fourth gate line GL4 through the contacts 132e and 134e, respectively. The sixth connection pattern 130f may electrically connect the sixth terminal 120f with the sixth gate line GL6, and may be electrically connected to the sixth wiring 142f and the sixth gate line GL6 through the contacts 132f and 134f, respectively.
In some exemplary embodiments of the inventive concept, the gate lines GL1˜GL6 and the wirings 142a˜142f may be disposed in a first wiring layer (e.g., in the same layer), and the connection patterns 130a˜130f may be disposed in a second wiring layer that is different from the first wiring layer. Thus, the second connection pattern 130b may overlap the second gate line GL2 without being electrically connected to the second gate line GL2. The fourth and fifth connection patterns 130d and 130e may overlap the third wiring 142c connected to the third terminal 120c without being electrically connected to the third wiring 142c. An overlapping structure of the second connection pattern 130b and the second gate line GL2 may correspond to the wiring overlapping region A in
For example, as illustrated in
In some exemplary embodiments, the insulation layer 150 may include a plurality of insulation layers. For example, a first insulation layer may be formed on the substrate 100 on which the gate lines GL2 and GL3 and the wirings 142b are formed, and then may be partially etched to form openings. The contacts 132b and 134b may be formed by filling the openings with conductive material, and then the second connection pattern 130b may be formed to electrically connect the wirings 142b with the gate line GL3. A second insulation layer may be formed on the substrate 100 on which the second connection pattern 130b is formed.
Although not illustrated in
Referring to
The display panel of
In some exemplary embodiments, as illustrated in
Although
Referring to
Referring to
Referring to
In some exemplary embodiments of the inventive concept, the examples of
Although not illustrated in
Referring to
The repeating pixel group RPG2 of
With continued reference to
In the repeating pixel group RPG2 of
Referring to
The repeating pixel group RPG3 of
Switching elements (e.g., ▪) of the first and fifth pixels P31 and P35 may be arranged adjacent to the first data line DL1. A switching element (e.g., □) of the fourth pixel P34 may be arranged adjacent to the second data line DL2. Although not illustrated in
Referring to
The repeating pixel group RPG4 of
Each of the first through sixth pixels P41˜P46 may be included in a respective one (e.g. first) pixel row and a respective one (e.g. first) pixel column, and may be electrically connected to a respective one of the first through sixth gate lines GL1˜GL6 and a respective one of the first and second data lines DL1 and DL2. For example, the first and second pixels P41 and P42 may be included in a first pixel row. The third and fourth pixels P43 and P44 may be included in a second pixel row that is adjacent to the first pixel row. The fifth and sixth pixels P45 and P46 may be included in a third pixel row that is adjacent to the second pixel row. The first, fourth and fifth pixels P41, P44 and P45 may be included in a first pixel column. Similarly, the second, third and sixth pixels P42, P43 and P46 may be included in a second pixel column that is adjacent to the first pixel column. The first and second pixels P41 and P42 may be electrically connected to the first data line DL1, and may be electrically connected to the first and second gate lines GL1 and GL2, respectively. The third and fourth pixels P43 and P44 may be electrically connected to the second data line DL2, and may be electrically connected to the third and fourth gate lines GL3 and GL4, respectively. The fifth and sixth pixels P45 and P46 may be electrically connected to the first data line DL1, and may be electrically connected to the fifth and sixth gate lines GL5 and GL6, respectively.
In some exemplary embodiments of the inventive concept, the first and second gate lines GL1 and GL2 may be disposed between the first and second pixel rows, and the third and fourth gate lines GL3 and GL4 may be disposed between the second and third pixel rows. In this example, all switching elements (e.g., □) of the first through sixth pixels P41˜P46 may be connected to the bottom gate lines.
Although not illustrated in
In the examples shown in
Referring to
With continued reference to
Each of the first through twelfth pixels P51˜P5C may be included in a respective one pixel row and a respective one pixel column. For example, the first and second pixels P51 and P52 may be included in a first pixel row. The first, third, fifth, seventh, ninth and eleventh pixels P51, P53, P55, P57, P59 and P5B may be included in a first pixel column.
Each of the first through twelfth pixels P51˜P5C shown in
The first through twelfth terminals 120a˜120l shown in
In some exemplary embodiments of the inventive concept, the first terminal 120a may be connected to the first gate line GL1, the second terminal 120b may be connected to the third gate line GL3, the third terminal 120c may be connected to the fifth gate line GL5, the fourth terminal 120d may be connected to the seventh gate line GL7, the fifth terminal 120e may be connected to the ninth gate line GL9, and the sixth terminal 120f may be connected to the eleventh gate line GL11. The seventh terminal 120g may be connected to the second gate line GL2, the eighth terminal 120h may be connected to the fourth gate line GL4, the ninth terminal 120i may be connected to the sixth gate line GL6, the tenth terminal 120j may be connected to the eighth gate line GL8, the eleventh terminal 120k may be connected to the tenth gate line GL10, and the twelfth terminal 120l may be connected to the twelfth gate line GL12. It should be understood by a person of ordinary skill in the art that other arrangements of terminal connections than the cross-coupled structure shown in
Based on the cross-coupled structure shown in
In some exemplary embodiments of the inventive concept, the cross-coupled structure in
The exemplary embodiments may be employed in any display panel and/or display apparatus where the plurality of gate lines GL are driven in units of 6*n. For example, the plurality of gate lines GL may include first through 6*n gate lines that are sequentially arranged in the first direction DR1, where n is a natural number equal to or greater than two. The plurality of terminals 120 may include first through 6*n terminals that sequentially receive first through 6*n gate signals among the plurality of gate signals, respectively. A k-th terminal among the first through 6*n terminals may be connected to a (2k−1)-th gate line, where k is a natural number equal to or greater than one and equal to or less than 3*n. A m-th terminal among the first through 6*n terminals is connected to a 2*(m−3n)-th gate line, where m is a natural number equal to or greater than (3n+1) and equal to or less than 6*n. Accordingly, the cross-coupled structure according to exemplary embodiments may be implemented.
The above described embodiments may be utilized in a display apparatus and/or a system including the display apparatus, for example, in a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation device, a personal computer (PC), a server computer, a workstation, a tablet computer, a laptop computer, etc., just to name a few non-limiting examples. The foregoing is illustrative of exemplary embodiments of the inventive concept and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed, and that the modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are to be included within the scope of the appended claims.
Number | Date | Country | Kind |
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10-2016-0074435 | Jun 2016 | KR | national |