Patent Application
20240389413
The present disclosure is a U.S. National Phase Entry of International Application No. PCT/CN2023/111467 having an international filing date of Aug. 7, 2023, which claims priority to Chinese Patent Application No. 202211064682.3, filed to the CNIPA on Aug. 29, 2022 and entitled “Display Panel and Display Apparatus”. The above-identified applications are incorporated herein by reference in their entireties.
The present disclosure relates to, but is not limited to, the field of display technologies, and more particularly, to a display panel and a display apparatus.
An Organic Light Emitting Diode (OLED for short) and a Quantum dot Light Emitting Diode (QLED for short) are active light emitting display devices and have advantages such as self-luminescence, wide viewing angle, high contrast ratio, low power consumption, very high response speed, lightness and thinness, flexibility, and low cost. With constant development of display technologies, a flexible display apparatus (Flexible Display) in which an OLED or a QLED is used as a light emitting device and signal control is performed through a Thin Film Transistor (TFT for short) has become a mainstream product in the field of display at present.
The following is a summary of subject matter described herein in detail. This summary is not intended to limit the protection scope of the claims.
In a first aspect, the present disclosure provides a display panel including a display region and a peripheral region located at a side of the display region, wherein the peripheral region includes a bending region and a fan-out region; the fan-out region is located at a side of the bending region away from the display region; the display panel includes: a base substrate, circuit units arranged in an array on the base substrate, a plurality of data signal lines extending along a first direction, and a plurality of data fan-out lines located in the fan-out region.
The data signal lines extend from the display region to at least the bending region, and are electrically connected with the circuit units and the data fan-out lines, respectively.
In an exemplary implementation, the display panel further includes a plurality of high-voltage power supply lines extending along the first direction, and at least one high-voltage power supply line extending from the display region to the fan-out region.
A plurality of circuit units extending along the first direction are a column of circuit units, one high-voltage power supply line is electrically connected with a column of circuit units, and the at least one high-voltage power supply line is electrically connected with a plurality of columns of circuit units.
In an exemplary implementation, the display panel further includes a plurality of light emitting devices and a plurality of low-voltage power supply lines extending along the first direction, wherein the low-voltage power supply lines extend from the display region to the fan-out region, and the circuit unit is electrically connected with the light emitting devices.
The plurality of low-voltage power supply lines are electrically connected with cathodes of the light emitting devices connected to a plurality of columns of circuit units.
In an exemplary implementation, the number of high-voltage power supply lines and the number of low-voltage power supply lines extending to the fan-out region are equal to the number of data signal lines, respectively.
The i-th high-voltage power supply line and the i-th low-voltage power supply line are respectively located at opposite sides of the i-th data signal line, wherein 1≤i≤N, and N is the number of data signal lines.
In an exemplary implementation, the sum of the number of high-voltage power supply lines and the number of low-voltage power supply lines extending to the fan-out region is equal to the number of data signal lines.
The m-th high-voltage power supply line extending to the fan-out region is connected to the (2m−1)-th column of circuit units, the m-th high-voltage power supply line extending to the fan-out region is located between the (2m−1)-th data signal line and the (2m)-th data signal line, the n-th low-voltage power supply line is located between the (2n)-th data signal line and the (2n+1)-th data signal line, or the m-th high-voltage power supply line extending to the fan-out region is connected to the (2m)-th column of circuit units, the m-th high-voltage power supply line extending to the fan-out region is located between the (2m)-th data signal line and the (2m+1)-th data signal line, the n-th low-voltage power supply line is located between the (2n−1)-th data signal line and the (2n)-th data signal line, wherein 1≤m≤N1, 1≤n≤N2, N1 is the number of high-voltage power supply lines extending to the fan-out region, and N2 is the number of low-voltage power supply lines.
In an exemplary implementation, the display panel further includes: a high-voltage signal line located in the fan-out region and extending along a second direction, wherein the first direction intersects with the second direction.
The high-voltage signal line is electrically connected with at least one high-voltage power supply line extending to the fan-out region, and an orthographic projection of the high-voltage signal line on the base substrate is overlapped with orthographic projections of the data fan-out lines on the base substrate.
A length of the high-voltage signal line along the first direction is greater than length of the high-voltage power supply lines along the second direction.
In an exemplary implementation, the display panel further includes: a low-voltage signal line located in the fan-out region and extending along the second direction.
The low-voltage signal line is electrically connected with a plurality of low-voltage power supply lines, and an orthographic projection of the low-voltage signal line on the base substrate is overlapped with the orthographic projections of the data fan-out lines on the base substrate.
A length of the low-voltage signal line along the first direction is greater than lengths of the low-voltage power supply lines along the second direction.
In an exemplary implementation, the low-voltage signal line and the high-voltage signal line are arranged in different layers.
In the fan-out region, the low-voltage signal line is located at a side of the high-voltage signal line away from the display region.
In an exemplary implementation, the peripheral region further includes: a bending transition region, and the bending transition region is located between the display region and the bending region.
The data signal lines include: a first data signal line located at least in the display region, a second data signal line located at least in the bending transition region and a third data signal line located at least in the bending region.
The second data signal line is arranged in a layer different from the first data signal line and the third data signal line respectively, the third data signal line is arranged in a layer different from the data fan-out line, an orthographic projection of the second data signal line on the base substrate is partially overlapped with an orthographic projection of the first data signal line and an orthographic projection of the third data signal line on the base substrate, respectively, the orthographic projection of the third data signal line on the base substrate is partially overlapped with the orthographic projections of the data fan-out lines on the base substrate, the second data signal line is electrically connected with the first data signal line and the third data signal line, respectively, the first data signal line is electrically connected with the circuit units, and the third data signal line is electrically connected with the data fan-out lines.
In an exemplary implementation, the high-voltage power supply line includes a first high-voltage power supply line located at least in the display region, a second high-voltage power supply line located at least in the bending transition region and a third high-voltage power supply line located at least in the bending region and the fan-out region.
The second high-voltage power supply line is arranged in a layer different from the first high-voltage power supply line and the third high-voltage power supply line, respectively, the third high-voltage power supply line is arranged in the same layer with the high-voltage signal line, an orthographic projection of the second high-voltage power supply line on the base substrate is partially overlapped with an orthographic projection of the first high-voltage power supply line on the base substrate and an orthographic projection of the third high-voltage power supply line on the base substrate, respectively, the second high-voltage power supply line is electrically connected with the first high-voltage power supply line and the third high-voltage power supply line, respectively, the first high-voltage power supply line is electrically connected with the circuit units, and the third high-voltage power supply line is electrically connected with the high-voltage signal line.
In an exemplary implementation, the low-voltage power supply lines include a first low-voltage power supply line located at least in the display region and the bending transition region and a second low-voltage power supply line located at least in the bending region and the fan-out region.
The first low-voltage power supply line and the second low-voltage power supply line are arranged in different layers, the second low-voltage power supply line and the low-voltage signal line are arranged in the same layer, an orthographic projection of the first low-voltage power supply line on the base substrate is partially overlapped with orthographic projections of cathodes of the light emitting devices on the base substrate and an orthographic projection of the second low-voltage power supply line on the base substrate, respectively, the first low-voltage power supply line is electrically connected with the cathodes of the light emitting devices and the second low-voltage power supply line, respectively, and the second low-voltage power supply line is electrically connected with the low-voltage signal line.
In an exemplary implementation, the display panel further includes a drive circuit layer and a light emitting structure layer arranged on the base substrate, wherein the drive circuit layer is provided with a circuit unit, a data signal line, a data fan-out line, a high-voltage power supply line, a low-voltage power supply line, a high-voltage signal line and a low-voltage signal line, the light emitting structure layer is provided with a light emitting device, and the drive circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially stacked on the base substrate.
The first data signal line is located in the third conductive layer and/or the fourth conductive layer, the second data signal line is located in the first conductive layer or the second conductive layer, the third data signal line is located in the third conductive layer or the fourth conductive layer, and the data fan-out line is located in the first conductive layer or the second conductive layer.
In an exemplary implementation, the first high-voltage power supply line is located in the third conductive layer and/or the fourth conductive layer, the second high-voltage power supply line is located in the first conductive layer or the second conductive layer, and the third high-voltage power supply line is located in the third conductive layer or the fourth conductive layer.
In an exemplary implementation, the first low-voltage power supply line is located in the first conductive layer or the second conductive layer; and the second low-voltage power supply line is located in the third conductive layer or the fourth conductive layer.
In an exemplary implementation, the peripheral region further includes a drive chip bonding region located at a side of the fan-out region away from the display region, the drive chip bonding region includes a control chip, and the display panel further includes at least one high-voltage connection line extending along the first direction and at least one low-voltage connection line extending along the first direction.
The high-voltage connection line is electrically connected with the high-voltage signal line and the control chip, respectively, and the low-voltage connection line is electrically connected with the low-voltage signal line and the control chip, respectively.
In an exemplary implementation, the high-voltage connection line is arranged on the same layer as the high-voltage signal line, and the low-voltage connection line is arranged on the same layer as the low-voltage signal line.
In second aspect, the present disclosure also provides a display apparatus including the display panel described above.
Other aspects of the present disclosure may be comprehended after the drawings and the detailed descriptions are read and understood.
Accompany drawings are used to provide further understanding of the technical solution of the present disclosure, and form a part of the description. The accompany drawings and embodiments of the present disclosure are adopted to explain the technical solution of the present disclosure, but do not form limitations on the technical solution of the present disclosure.
The embodiments of the present disclosure will be described below with reference to the drawings in detail. Implementation modes may be implemented in multiple different forms. Those of ordinary skills in the art may easily understand such a fact that modes and contents may be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be explained as being limited to the contents recorded in the following implementations only. The embodiments and features in the embodiments of the present disclosure may be randomly combined with each other if there is no conflict.
In the drawings, a size of one or more constituent elements, a thickness of a layer, or a region is sometimes exaggerated for clarity. Therefore, one mode of the present disclosure is not necessarily limited to the size, and a shape and a size of one or more components in the drawings do not reflect an actual scale. In addition, the accompanying drawings schematically illustrate ideal examples, and a mode of the present disclosure is not limited to shapes, numerical values, or the like shown in the drawings.
Ordinal numerals “first”, “second”, “third”, etc., in the specification are set not to form limits on numbers but only to avoid confusion between composition elements. In the present disclosure, “a plurality of” represents two or more than two.
In the specification, for convenience, expressions “central”, “above”, “below”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, etc., indicating directional or positional relationships are used to illustrate positional relationships between the composition elements, not to indicate or imply that involved devices or elements are needed to have specific orientations and be structured and operated with the specific orientations but only to easily and simply describe the present specification, and thus should not be understood as limitations on the present disclosure. The positional relationships between the constituent elements are changed as appropriate according to a direction with which the constituent elements are described. Therefore, appropriate replacements based on situations are allowed, which is not limited to the expressions in the specification.
In the specification, unless otherwise specified and defined, terms “mounting”, “mutual connection”, and “connection” should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or a connection; it may be a direct connection, an indirect connection through a middleware, or internal communication inside two elements. Those of ordinary skills in the art may understand meanings of the aforementioned terms in the present disclosure according to situations.
In the specification, “electrical connection” includes connection of composition elements through an element with some electrical effection. The “element having some electrical effection” is not particularly limited as long as electrical signals between the connected constituent elements may be transmitted. Examples of the “element having some electrical effection” not only include an electrode and a wiring, but also include a switching element such as a transistor, a resistor, an inductor, a capacitor, another element with multiple functions, etc.
In the specification, a transistor refers to an element which at least includes three terminals, i.e., a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and a current can flow through the drain, the channel region, and the source. In the specification, the channel region refers to a region through which a current mainly flows.
In the specification, a first electrode may be a drain and a second electrode may be a source, or, a first electrode may be a source and a second electrode may be a drain. In a case that transistors with opposite polarities are used, or in a case that a direction of a current is changed during operation of a circuit, or the like, functions of the “source” and the “drain” are sometimes interchangeable. Therefore, the “source” and the “drain” are interchangeable in the specification. In addition, the gate may also be referred to as a control electrode.
In the specification, “parallel” refers to a state in which an angle formed by two straight lines is above −10° and below 10°, and thus may include a state in which the angle is above −5° and below 5°. In addition, “perpendicular” refers to a state in which an angle formed by two straight lines is above 80° and below 100°, and thus may include a state in which the angle is above 85° and below 95°.
Triangle, rectangle, trapezoid, pentagon, hexagon, etc. in this specification are not strictly defined, and they may be approximate triangle, rectangle, trapezoid, pentagon, hexagon, etc. There may be some small deformations caused by tolerance, and there may be chamfer, arc edge, deformation, etc.
In the specification, “about” and “substantially” refer to that a boundary is not defined strictly and a case within a process and measurement error range is allowed. In the specification, “substantially the same” refers to a case where numerical values differ by less than 10%.
In an exemplary implementation, the timing controller may provide the data driver with a grayscale value and a control signal which are suitable for the specification of the data driver, provide the scan driver with a clock signal and a scan start signal and the like which are suitable for the specification of the scan driver, and provide the light emitting driver with a clock signal and an emission stop signal and the like which are suitable for the specification of the light emitting driver. The data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . , and Dn using the grayscale value and the control signal that are received from the timing controller. For example, the data driver may sample the gray scale value by using a clock signal, and apply a data voltage corresponding to the gray scale value to the data signal lines D1 to Dn by taking a pixel column as a unit. The scan driver may generate a scan signals to be provided to the scan signal lines S1, S2, S3, . . . , and Sm by receiving the clock signal and the scan start signal from the timing controller. For example, the scan driver may sequentially provide a scan signal with an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in a form of a shift register, and may generate a scan signal in a manner of sequentially transmitting a scan start signal provided in a form of an on-level pulse to a next-stage circuit under control of a clock signal. The light emitting driver may generate a light emitting control signal to be provided to the light emitting signal lines E1, E2, E3, . . . , and Eo by receiving the clock signal, the emission stop signal, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal with an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be constructed in a form of a shift register and generate a light emitting control signal in a manner of sequentially transmitting an emission stop signal provided in a form of an off-level pulse to a next-stage circuit under control of a clock signal.
In an exemplary implementation, a peripheral region 200 may include a fan-out region 220, a bending region 210, a driver chip region 240, and a bonding pin region that are arranged sequentially along a direction away from the display region 100. The fan-out region introduces signal lines of integrated circuits and bonding pads in the peripheral region into a wider display region in a fan-out (Fanout) trace manner. The fan-out region at least includes a data fan-out (Fanout) line, and a plurality of data fan-out lines are configured to be connected with data signal lines in a fan-out trace manner. The bending region may include a composite insulation layer provided with a groove, and is configured to enable the drive chip bonding region and the bonding pin region to be bent to a back of the display region 100. An Integrated Circuit (IC) may be arranged in the drive chip bonding region, and the integrated circuit may be configured to be connected with the plurality of data fan-out lines. The bonding pin region may include a bonding pad, and the bonding pad may be configured to be bonded and connected with an external Flexible Printed Circuit (FPC). In an exemplary implementation mode, the bezel region 300 may include a circuit region, a power supply line region, and a crack dam region, and a cutting region which are sequentially arranged along the direction away from the display region 100. The circuit region is connected to the display region 100 and may include at least a gate drive circuit, the gate drive circuit is connected with the scan signal line, the reset signal line, and the light emitting signal line that are connected with the pixel circuit in the display region 100. The power supply line region is connected to the circuit region and may at least include a bezel power supply lead line that extends along a direction parallel to an edge of the display region and is connected with a cathode in the display region 100. The crack dam region is connected to the power supply line region and may at least include a plurality of cracks arranged on the composite insulation layer. The cutting region is connected to the crack dam region and may at least include a cutting groove arranged on the composite insulation layer, and the cutting groove is configured such that a cutting device cuts along the cutting groove respectively after preparation of all film layers of the display panel are completed.
In an exemplary implementation mode, the fan-out region in the peripheral region 200 and the power supply line region in the bezel region 300 may be provided with a first isolation dam and a second isolation dam, the first isolation dam and the second isolation dam may extend along a direction parallel to the edge of the display region 100, thus forming an annular structure surrounding the display region 100. The edge of the display region is an edge of the display region 100 at a side close to the peripheral region 200 or the bezel region 300.
In an exemplary implementation, a light emitting device of the sub-pixel may have a shape of a rectangle, a rhombus, a pentagon, or a hexagon.
In an exemplary implementation, as shown in ”, etc., which is not limited here in the present disclosure.
”. In an exemplary implementation, as shown in
In an exemplary implementation, the base substrate 101 may be a flexible base substrate, or may be a rigid base substrate. The rigid base substrate may include, but is not limited to, one or more of glass and quartz. The flexible base substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylester, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary implementation, the flexible base substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer stacked on the glass carrier plate. Materials of the first flexible material layer and the second flexible material layer may be Polyimide (PI), Polyethylene Terephthalate (PET), or a surface-treated polymer soft film, etc., and materials of the first inorganic material layer and the second inorganic material layer may be Silicon Nitride (SiNx) or Silicon Oxide (SiOx), etc. to improve an anti-water-oxygen capability of the base substrate. The first inorganic material layer and the second inorganic material layer are called as barrier layers, and the semiconductor layer may be a polycrystalline Silicon (p-Si) layer. In an exemplary implementation, taking a laminated structure of PI1/Barrier1/p-Si/PI2/Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on the glass carrier plate, curing it into a film to form a first flexible (PI1) layer; then, depositing a layer of barrier thin film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon thin film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer, and forming a polysilicon layer through a process such as excimer laser annealing; after that, coating a layer of polyimide on the polysilicon layer, curing it into a film to form a second flexible (PI2) layer; then, depositing a layer of barrier thin film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing preparation of the base substrate.
In an exemplary implementation, the drive circuit layer 102 of each sub-pixel may include a plurality of transistors and a storage capacitor, which constitute a pixel drive circuit. In
In an exemplary implementation, the touch structure layer of each sub-pixel may include a first touch insulation layer arranged on the encapsulation structure layer, a first touch metal layer on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protective layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridge electrodes, the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes, and the first touch electrodes or the second touch electrodes may be connected with the bridge electrodes through a via.
In an exemplary implementation mode, the organic emitting layer may include an Emitting Layer (EM), and any one or more of following layers: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Block Layer (EBL), a Hole Block Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). In some examples, one or more layers of hole injection layers, hole transport layers, electron block layers, hole block layers, electron transport layers, and electron injection layers of all sub-pixels may be respectively connected together to be a common layer. Emitting layers of adjacent sub-pixels may be overlapped slightly, or may be mutually isolated.
In an exemplary implementation mode, as shown in
In an exemplary implementation, as shown in
In the example, the first node N1 is a connection point of the capacitor C, the first transistor T1, the third transistor T3, and the second transistor T2, the second node N2 is a connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3, the third node N3 is a connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6, and the fourth node N4 is a connection point of the sixth transistor T6, the seventh transistor T7, and the light emitting device L.
In an exemplary implementation mode, the seven transistors of the pixel circuit may be P-type transistors, or may be N-type transistors. Adopting a same type of transistors in the pixel circuit may simplify a process flow, reduce process difficulties of the display panel, and improve a yield of products. In some possible implementation modes, the seven transistors in the pixel circuit may include a P-type transistor and an N-type transistor.
In an exemplary implementation mode, for the seven transistors in the pixel circuit, a low temperature poly silicon thin film transistor may be adopted, or an oxide thin film transistor may be adopted, or a low temperature poly silicon thin film transistor and an oxide thin film transistor may be adopted. Low Temperature Poly-Silicon (LTPS for short) is used as an active layer of low temperature Poly-Silicon thin film transistor, and Indium Gallium Zinc Oxide (IGZO for short) is used as an active layer of oxide thin film transistor. The low temperature poly silicon thin film transistor has advantages such as a high migration rate and fast charging, and the oxide thin film transistor has advantages such as a low leakage current. The low temperature poly silicon thin film transistor and the oxide thin film transistor are integrated on one display panel, that is, an LTPS+IGZO (LTPO for short) display panel, so that advantages of both the low temperature poly silicon thin film transistor and the oxide thin film transistor may be utilized, low-frequency drive may be achieved, power consumption may be reduced, and display quality may be improved.
In an exemplary implementation, the high-voltage power supply line VDD may be configured to provide a constant first voltage signal to the pixel circuit, and the low-voltage power supply line VSS may be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal is greater than the second voltage signal. The scan signal line Gate may be configured to provide a scan signal to the pixel circuit, the data signal line Data may be configured to provide a data signal to the pixel circuit, and the light emitting signal line EM may be configured to provide a light emitting control signal to the pixel circuit. In some examples, in an n-th row of pixel circuits, the reset signal line Reset may be electrically connected with a scan signal line Gate of an (n−1)-th row of pixel circuits to be inputted with a scan signal. Herein, n is an integer greater than 0. In this way, signal lines of the display panel may be reduced, and a narrow bezel design of the display panel may be achieved. However, the embodiment is not limited thereto.
In an exemplary implementation mode, the first initial signal line INIL1 may be configured to provide a first initial signal to the pixel circuit, the second initial signal line INIL2 may be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between, for example, the first voltage signal provided by the high-voltage power supply line VDD and the second voltage signal provided by the low-voltage power supply line VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal may be the same and only the first initial signal line may be provided to provide the first initial signal.
In an exemplary implementation, the light emitting device L may be an OLED including a first electrode (anode), an organic emitting layer, and a second electrode (cathode) which are stacked, or may be a QLED including a first electrode (anode), a quantum dot emitting layer, and a second electrode (cathode) which are stacked. A second electrode of the light emitting device is connected with the low-voltage power supply line VSS, a signal of the low-voltage power supply line VSS is a low-level signal provided continuously, and a signal of the high-voltage power supply line VDD is a high-level signal provided continuously.
In an exemplary implementation mode,
The first stage A1 is referred to as a reset stage. A low-level signal provided by the reset signal line Reset enables the first transistor T1 to be turned on, and a first initial signal provided by the first initial signal line INIL1 is provided to the first node N1 to initialize the first node N1 and clear an original data voltage in the capacitor C. The scan signal line Gate provides a high-level signal and the light emitting signal line EM provides a high-level signal, so that the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. The light emitting device L does not emit light in this stage
A second stage A2 is referred to as a data writing stage or a threshold compensation stage. The scan signal line Gate provides a low-level signal, the Reset signal line Reset and the light emitting signal line EM both provide a high-level signal, and the data signal line DATA outputs a data signal Date. In this stage, since the first electrode plate of the capacitor C is at a low level, the third transistor T3 is turned on. The scan signal line Gate provides the low-level signal, so that the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on. The second transistor T2 and the fourth transistor T4 are turned on, so that a data voltage Vdata output by the data signal line Data is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the capacitor C is charged with a difference between the data voltage Vdata output by the data signal line Data and a threshold voltage of the third transistor T3. A voltage of the first electrode plate (i.e., the first node N1) of the capacitor C is Vdata−|Vth|, wherein Vdata is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that a second initial signal provided by the second initial signal line INIL2 is provided to the anode of the light emitting device L to initialize (reset) the anode of the light emitting device L and clear a pre-stored voltage therein, so as to complete initialization, thereby ensuring that the light emitting device L does not emit light. The reset signal line RESET provides a high-level signal, so that the first transistor T1 is turned off. The light emitting signal line EM provides a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
The third stage A3 is referred to as a light emitting stage. The light emitting signal line EM provides a low-level signal, and the scan signal line Gate and the Reset signal line Reset both provide a high-level signal. The light emitting signal line EM provides the low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and a first voltage signal output by the high-voltage power supply line VDD provides a drive voltage to the anode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 to drive the light emitting device L to emit light.
In a drive process of the pixel circuit, a drive current flowing through the third transistor T3 (i.e., the drive transistor) is determined by a voltage difference between the gate and the first electrode of the third transistor T3. Since the voltage of the first node N1 is Vdata−|Vth|, the drive current of the third transistor T3 is as follows.
Herein, I is the drive current flowing through the third transistor T3, that is, a drive current for driving the light emitting device L, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line DATA, and Vdd is the first voltage signal output by the high-voltage power supply line VDD.
It may be seen from the above formula that a current flowing through the light emitting device L is independent of the threshold voltage of the third transistor T3. The pixel circuit of the embodiment may better compensate the threshold voltage of the third transistor T3.
With development of OLED display technologies, consumers have higher requirements on a display effect of a display product. An extremely narrow bezel has become a new trend in development of display products. Therefore, bezel narrowing or even no-bezel design has attracted more and more attention in a design of an OLED display product. In a display panel, a peripheral region generally includes a fan-out region, a bending region, a drive chip bonding region, and a bonding pin region sequentially arranged along a direction away from a display region. Since the fan-out region is located at a side of the bending region close to the display region, the fan-out region cannot be bent after the peripheral region is bent, so that a width difference between the display region and the peripheral region is larger, which makes it difficult to narrow the lower bezel, and the lower bezel is always maintained at about 2.0 mm.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In the present disclosure, “A extends along a B direction” means that A may include a main portion and a secondary portion connected with the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the B direction, and a length of the main portion extending along the B direction is greater than a length of the secondary portion extending along another direction. In following description, “A extends along a B direction” means “a main body portion of A extends along a B direction”. In an exemplary implementation, the second direction Y may be a direction pointing from the display region to the peripheral region, and an opposite direction of the second direction Y may be a direction pointing from the peripheral region to the display region.
The display panel according to an embodiment of the present disclosure includes a display region and a peripheral region located at a side of the display region, wherein the peripheral region includes a bending region and a fan-out region; the fan-out region is located at a side of the bending region away from the display region; the display panel includes: a base substrate, circuit units arranged in an array and provided on the base substrate, a plurality of data signal lines extending along the first direction X, and a plurality of data fan-out lines located in the fan-out region; the data signal lines extend from the display region to at least the bending region, and are electrically connected with the circuit units and the data fan-out lines, respectively. According to present disclosure, the fan-out region is arranged at a side of the bending region away from the display region, so that the data fan-out line is arranged on the back side of the display panel after bending, thereby reducing a space occupied by the lower bezel of the display panel, and realizing the narrow bezel.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, paths, through which high-voltage signals flow, of the circuit units arranged in an array, are communicated with each other, wherein the high-voltage signals are signals provided by the high-voltage power supply line 60. The paths, through which the high-voltage signals flow, may refer to an electrode plate of a capacitor connected to the high-voltage power supply line and a first electrode of the fifth transistor in each circuit unit. The communication with each other among the paths, through which the high-voltage signals flow, of the circuit units arranged in an array, may be a connection with each other among electrode plates of the capacitors connected to the high-voltage power supply lines of the circuit units arranged in an array and/or a connection with each other among the first electrodes of the fifth transistors. The high-voltage power supply lines may be electrically connected to other columns of circuit units through a path, through which the high-voltage signals flow, of the connected circuit unit and other circuit units.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, the number of high-voltage power supply lines extending to the fan-out region and the number of low-voltage power supply lines extending to the fan-out region may be equal to the number of data signal lines, respectively, or the sum of the number of high-voltage power supply lines extending to the fan-out region and the number of low-voltage power supply lines extending to the fan-out region is equal to the number of data signal lines, or the sum of the number of high-voltage power supply lines extending to the fan-out region and the number of low-voltage power supply lines extending to the fan-out region is less than the number of data signal lines.
In an exemplary implementation, as shown in
In an exemplary implementation, the m-th high-voltage power supply line 60 extending to the fan-out region 220 is connected to the (2m−1)-th column of circuit units, the m-th high-voltage power supply line 60 extending to the fan-out region 220 is located between the (2m−1)-th data signal line 40 and the (2m)-th data signal line 40, the n-th low-voltage power supply line 70 is located between the (2n)-th data signal line 40 and the (2n+1)-th data signal line 40, or the m-th high-voltage power supply line 60 extending to the fan-out region 220 is connected to the (2m)-th column of circuit units, and the m-th high-voltage power supply line 60 extending to the fan-out region 220 is located between the (2m)-th data signal line 40 and the (2m+1)-th data signal line 40, the n-th low-voltage power supply line 70 is located between the (2n−1)-th data signal line 40 and the (2n)-th data signal line 40, wherein 1≤m≤N1, 1≤n≤N2, N1 is the number of high-voltage power supply lines extending to the fan-out region, and N2 is the number of low-voltage power supply lines. According to the present disclosure, the arrangement of the high-voltage power supply lines 60 and the low-voltage power supply lines 70 extending to the fan-out region 220 may make high-voltage signals or low-voltage signals interspersed between adjacent data signal lines, so the interference between adjacent data signal lines is small, which may effectively reduce image sticking, improving the display effect of the display pane.
In an exemplary implementation, a plurality of high-voltage power supply lines extending to the fan-out region 220 may be uniformly arranged or non-uniformly arranged and may be defined according to the structure of the display panel, which are not limited in the present disclosure. A plurality of low-voltage power supply lines extending to the fan-out region 220 may be uniformly arranged or non-uniformly arranged and may be defined according to the structure of the display panel, which are not limited in the present disclosure.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In the present disclosure, the high-voltage signal line 10 is arranged in the fan-out region at a side of the bending region away from the display region, which may reduce the space occupied by the bezel region of the display panel and achieve the narrow bezel of the display panel.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, tan orthographic projection of the low-voltage signal line 20 on the base substrate may not be overlapped with an orthographic projection of the high-voltage signal lines 10 on the base substrate.
In an exemplary implementation, in order to avoid mutual interference of signals between the low-voltage signal line 20 and the high-voltage signal line 10, the low-voltage signal line 20 and the high-voltage signal line 10 may be arranged in different layers, and the low-voltage signal line 20 is located at a side of the high-voltage signal line 10 away from the display region 100.
According to the present disclosure, since the arrangement of the high-voltage signal line and the low-voltage signal line makes the voltage drops of the high-voltage power supply line 60 and the low-voltage power supply line 70 reaching the circuit units of the display region substantially identical, the display uniformity of the display panel is better.
In an exemplary implementation as shown in
In an exemplary implementation, the drive circuit layer is provided with a circuit unit, a data signal line, a data fan-out line, a high-voltage power supply line, a low-voltage power supply line, a high-voltage signal line and a low-voltage signal line, the light emitting structure layer is provided with a light emitting device, and the drive circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially stacked on the base substrate.
In an exemplary implementation, the first conductive layer may include one electrode plate of the capacitor and gate electrodes of a plurality of transistors, the second conductive layer may include the other electrode plate of the capacitor, and the third conductive layer may include source electrodes and drain electrodes of the plurality of transistors.
In an exemplary implementation, the drive circuit layer may further include a semiconductor layer located at a side of the first conductive layer close to the base substrate. The semiconductor layer may include active layers of a plurality of transistors.
In an exemplary implementation, the drive circuit layer may further include a plurality of insulation layers and a planarization layer, wherein the plurality of insulation layers may include a first insulation layer arranged between the semiconductor layer and the first conductive layer, a second insulation layer arranged between the first conductive layer and the second conductive layer, a third insulation layer arranged between the second conductive layer and the third conductive layer, a fourth insulation layer arranged between the third conductive layer and the fourth conductive layer, and a fifth insulation layer arranged at a side of the fourth conductive layer away from the base substrate.
In an exemplary implementation, the semiconductor layer may be made of a material, such as an amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on the oxide technology, silicon technology or organic technology.
In an exemplary implementation, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of a metal material, such as any one or more of Argentum (Ag), Copper (Cu), Aluminum (Al), and Molybdenum (Mo), or an alloy material of the aforementioned metals, such as an Aluminum Neodymium alloy (AlNd) or a Molybdenum Niobium alloy (MoNb), and may be of a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo.
In an exemplary implementation, the first insulation layer, the second insulation layer, the third insulation layer, the fourth insulation layer and the fifth insulation layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be in a single layer, multiple layers, or in a composite layer. The first insulation layer may be referred to as a buffer layer, the second insulation layer may be referred to as a gate insulation (GI) layer, the fourth insulation layer may be referred to as an interlayer dielectric (ILD) layer, and the fifth insulation layer may be referred to as a passivation (PVX) layer.
In an exemplary implementation, an anode of the light emitting device may employ a transparent conductive layer, which may be made of Indium tin oxide ITO or indium zinc oxide IZO, or employ a multi-layer composite structure, such as ITO/Ag/ITO.
In an exemplary implementation, the planarization layer may be made of an organic material, such as resin.
In an exemplary implementation, as shown in
In an exemplary implementation, the first data signal line 41 is located in the third conductive layer and/or the fourth conductive layer, the second data signal line 42 is located in the first conductive layer or the second conductive layer, the third data signal line 43 is located in the third conductive layer or the fourth conductive layer, and the data fan-out line 50 is located in the first conductive layer or the second conductive layer.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, the first high-voltage power supply line 61 is located in the third conductive layer and/or the fourth conductive layer, the second high-voltage power supply line 62 is located in the first conductive layer or the second conductive layer, and the third high-voltage power supply line 63 is located in the third conductive layer or the fourth conductive layer.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, the first low-voltage power supply line 71 is located in the first conductive layer or the second conductive layer; the second low-voltage power supply line 72 is located in the third conductive layer or the fourth conductive layer.
In an exemplary implementation, as shown in
In an exemplary implementation, the first low-voltage power supply line 71 and the second high-voltage power supply line 62 may be arranged in the same layer or in different layers.
In an exemplary implementation, the second low-voltage power supply line is located in the fourth conductive layer when the third high-voltage power supply line 63 is located in the third conductive layer, or the second low-voltage power supply line is located in the third conductive layer when the third high-voltage power supply line 63 is located in the fourth conductive layer.
In an exemplary implementation, as shown in
In the exemplary implementation, as shown in
In an exemplary implementation, the high-voltage connection line 11 and the high-voltage signal line 10 may be arranged in the same layer, and the low-voltage connection line 21 and the low-voltage signal line 20 may be arranged in the same layer. The high-voltage connection line 11 and the high-voltage signal line 10 may be arranged in the same layer, and the low-voltage connection line 21 and the low-voltage signal line 20 may be arranged in the same layer, such that the manufacturing process of the display panel may be simplified.
In an exemplary implementation, the display panel of the present disclosure may be applied to a display apparatus with a pixel circuit, such as an OLED, a Quantum dot display (QLED), a Micro Light Emitting Diode display (Micro LED or Mini LED), or a Quantum Dot Light Emitting Diode display (QD-LED), which is not limited here in the present disclosure.
Through simulation, the uniformity of the current of the display panel according to an embodiment of the present disclosure in different items is greater than 75%. In the simulation, it is obtained by selecting 9 positions in the display panel, and analyzing the currents of high-voltage power supply lines and low-voltage power supply lines at these 9 positions. For a display panel with high resolution (for example, 2436*2752, and the pixel unit includes 4 sub-pixels), the uniformity of the current is up to 93% or more. Therefore, through simulation, the display uniformity of the display panel according to an embodiment of the present disclosure is high.
An embodiment of the present disclosure further provides a display apparatus which includes a display panel provided according to any one of the aforementioned embodiments.
In an exemplary implementation mode, the display apparatus may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, or a navigator, and the present disclosure is not limited thereto.
The accompanying drawings of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to usual designs.
For the sake of clarity, a thickness and size of a layer or a micro structure are enlarged in the accompanying drawings used for describing the embodiments of the present disclosure. It may be understood that when an element such as a layer, film, region, or substrate is described as being “on” or “under” another element, the element may be “directly” located “on” or “under” the another element, or there may be an intermediate element.
Although the implementations of the present disclosure are disclosed above, the contents are only implementations used for ease of understanding of the present disclosure, but not intended to limit the present disclosure. Any of those skilled in the art of the present disclosure can make any modifications and variations in the implementation mode and details without departing from the spirit and scope of the present disclosure. However, the protection scope of the present disclosure should be subject to the scope defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211064682.3 | Aug 2022 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/111467 | 8/7/2023 | WO |
