Patent Grant
11763772
This is a National Stage Application filed under 35 U.S.C. 371 based on International Patent Application No. PCT/CN2021/074032, filed on Jan. 28, 2021, which claims priority to Chinese Patent Application No. 202011503062.6 filed on Dec. 18, 2020, disclosures of both of which are incorporated herein by reference in their entireties.
The present disclosure relates to the field of display technologies, for example, a display panel and a display device.
With the development of display technologies, display panels are widely used in devices or scenarios that can integrate display functions, such as computers, mobile phones, wearable devices and vehicles. With the improvement of electronic device integration, pulse signals of the display panel can cause interference to other electronic products in the periphery. The interference can be referred to as Electromagnetic Interference (EMI). The electronic products subject to electromagnetic interference have a degraded performance, and even cannot work normally. Based on this, when the display panel is integrated in some devices or applied to some scenarios, for example, when the display panel is used as an onboard display screen and applied to an onboard display, the display panel generates electromagnetic interference to other onboard electronic products.
The present disclosure provides a display panel and a display device so that electromagnetic interference radiated to the periphery by the display panel can be reduced.
The display panel provided includes a gate drive circuit, a plurality of impedance regulation circuits and a control module.
The gate drive circuit includes a plurality of cascaded first shift registers. The plurality of cascaded first shift registers are electrically connected to a plurality of scanning lines in one to one correspondence.
The plurality of impedance regulation circuits are in one-to-one correspondence with the plurality of scanning lines, and each of the plurality of impedance regulation circuits is in series connection between a first shift register corresponding to the each of the plurality of impedance regulation circuits and a scanning line corresponding to the each of the plurality of impedance regulation circuits. The each of the plurality of impedance regulation circuits includes at least one transistor.
The control module is electrically connected to the plurality of impedance regulation circuits and configured to adjust impedance of the at least one transistor in the each of the plurality of impedance regulation circuits.
The display device provided includes the display panel described above.
The solutions of the present disclosure are described hereinafter through some embodiments in conjunction with the drawings in embodiments of the present disclosure.
The plurality of impedance regulation circuits 20 are in one-to-one correspondence with the plurality of scanning lines 40. The plurality of impedance regulation circuits 20 are in series connection between the plurality of cascaded first shift registers 11 and the plurality of scanning lines 40 which are in one-to-one correspondence with each other. Each impedance regulation circuit 20 includes at least one transistor. As shown in
In the gate drive circuit 10, because the scanning pulse signal is provided to multi-row scanning lines 40 row by row, the scanning pulse signal is a periodic rectangular wave. The periodic rectangular wave causes electromagnetic interference of discrete spectrum. The electromagnetic interference can spread outwards through a transmission line and a space electromagnetic field, to cause problems of conduction and radiation interference, which not only seriously pollutes the surrounding electromagnetic environment, but also causes electromagnetic interference to nearby electrical equipment. The steeper the rising edge and falling edge of the waveform of the scanning pulse signal provided by the gate drive circuit 10 are, the greater the electromagnetic interference caused by the scanning pulse signals is.
In this embodiment of the present disclosure, one impedance regulation circuit 20 is in series connection between each stage of first shift register 11 and a scanning line 40. The control module 30 adjusts the impedance of the transistor in the impedance regulation circuit 20 according to different EMI requirement standards to change the waveform of the scanning pulse signal, that is, the gradient of the rising edge and the falling edge of the scanning pulse signal waveform, and achieve optimal EMI performance for electronic products with different EMI requirement standards.
In an embodiment, on the basis of the above-described embodiment, the control module 30 according to this embodiment of the present disclosure may control the turn-on and turn-off of the transistor in the impedance regulation circuit 20 to adjust the impedance of the transistor in the impedance regulation circuit 20. The impedance regulation circuit 20 according to this embodiment of the present disclosure may include at least one transistor. If the impedance regulation circuit 20 includes a plurality of transistors, the plurality of transistors may be in series, in parallel, or partly in series and partly in parallel connection. The output terminal of the control module 30 may output different level signals to control the turn-on or turn-off of the transistor in the impedance regulation circuit 20. In the following, the transistor in the impedance regulation circuit 20 is an N-type transistor as an example. For example, if the output terminal of the control module 30 is a high level, the transistor is turned on; and if the output terminal of the control module 30 is a low level, the transistor is turned off. When multiple transistors in the impedance regulation circuit 20 achieve different combinations of turn-on and turn-off, different impedance mountings of the plurality of scanning lines 40 can be obtained, so that the scanning pulse signal waveform is actively adjusted according to the EMI requirements of products, and the optimal EMI performance is achieved. In this embodiment of the present disclosure, the at least one transistor in the each of the plurality of impedance regulation circuits 20 may be an N-type transistor or a P-type transistor, which is not limited by this embodiment of the present disclosure. For example, if the transistor in the impedance regulation circuit 20 is an P-type transistor and the output terminal of the control module 30 is a low level, the transistor is turned on; and if the output terminal of the control module 30 is a high level, the transistor is turned off.
In an embodiment, the control module 30 may also adjust a gate voltage value of the transistor in the impedance regulation circuit 20 to adjust the impedance of the transistor in the impedance regulation circuit 20. The output terminal of the control module 30 may output adjustable voltage signal for controlling the switching degree of the transistor in the impedance regulation circuit 20, to achieve the adjustment of the impedance of the transistor in the impedance regulation circuit 20. For example, if the transistor in the impedance regulation circuit 20 is an N-type transistor, the voltage signal value output by the control module 30 may be increased when the rising edge and falling edge of the scanning pulse signal waveform are required to be relatively steep; and the voltage signal value output by the control module 30 may be reduced when the rising edge and falling edge of the scanning pulse signal waveform are required to be relatively slow. If the transistor in the impedance regulation circuit 20 is a P-type transistor, the voltage signal value output by the control module may be reduced when the rising edge and falling edge of the scanning pulse signal waveform are required to be steeper; and the voltage signal value output by the control module may be increased when the rising edge and falling edge of the scanning pulse signal waveform are required to be slow. In this embodiment of the present disclosure, a transistor having a relatively large linear region may be selected as the transistor in the impedance regulation circuit 20 to increase the adjustment range of the impedance of the transistor in the impedance regulation circuit 20, and ensure that the adjustment of the mounting impedance of the scanning line 40 is sufficiently flexible to achieve better EMI adjustment performance.
According to the IV characteristic formula
of the transistor in linear region, the smaller the slope of the IV curve is, the larger the linear region of the transistor is, and the larger the impedance adjustment range of the impedance regulation circuit 20 is. The slope of the transistor IV curve
is denotes a transconductance parameter,
denotes the channel width-to-length ratio of the transistor, Vgs denotes the voltage difference between the gate and the source, Vth denotes the threshold voltage of the transistor, Vds denotes the voltage difference between the drain and the source, and Id denotes the drain current of the transistor.
In an embodiment, on the basis of the above-described embodiment, each impedance regulation circuit 20 includes a first impedance regulation subcircuit. The first impedance regulation subcircuit includes N transistors connected in series. A gate of an i-th transistor of the N transistors in the first impedance regulation subcircuit of the impedance regulation circuit 20 are electrically connected to a same output terminal of the control module 30, where N is a positive integer greater than 1, and i is a positive integer less than or equal to N.
In the solution where a plurality of transistors in the first impedance regulation subcircuit are in series connection, the transistors may correspond to traverses when turned on, and impedances of the transistors are approximately 0. When turned off, the transistors may correspond to resistors. This embodiment of the present disclosure may use the off-impedances of multiple transistors in the first impedance regulation subcircuit to achieve the adjustment of the impedances of the impedance regulation circuit 20. The output terminal of the control module 30 may output different level signals to control the turn-on or turn-off of the transistors in the first impedance regulation subcircuit. For example, a transistor having a relatively large channel width-to-length ratio may be selected so that the impedance of the transistor is approximately 0 when the transistor is turned on, and the transistor may have a leakage current equivalent to a resistor when the transistor is turned off. It is also possible to use a case where the p-n junction of the field-effect transistor or the bipolar junction transistor (BJT) is a Schottky junction. That is, when the transistor is turned off, the channel of the transistor is not completely off.
As shown in
Since a gate of an i-th transistor of the N transistors in the first impedance regulation subcircuits 21 of the each of the plurality of impedance regulation circuits 20 is electrically connected to a same output terminal of the control module, the control module 30 can simultaneously control the turn-on and turn-off of the i-th transistor in each of a plurality of first impedance regulation subcircuits 21 through the i-th output terminal. In this manner, a number of output terminals in the control module 30 can be reduced, to reduce the cost.
The off-impedances of the plurality of transistors in the first impedance regulation subcircuit 21 may be the same or may be different. For example, transistors having different off-impedances can be obtained by providing the communication width-to-length ratio of the transistors to be different.
Referring to
Table 1 is an impedance regulation table of an impedance regulation circuit of the display panel shown in
Table 1 only provides an example of the impedance adjustment of an impedance regulation circuit in conjunction with
In order to achieve that the impedances of the impedance regulation circuit 20 can be varied at equal intervals, the off-impedances of N transistors in the first impedance regulation subcircuit 21 may be set to be in a geometric sequence. As shown in Table 1, for example, an off-impedance of the first transistor of N transistors in the first impedance regulation subcircuit 21 is 1 kΩ, an off-impedance of the second transistor of N transistors in the first impedance regulation subcircuit 21 is 2 kΩ, an off-impedance of the third transistor of N transistors in the first impedance regulation subcircuit 21 is 4 kΩ, and an off-impedance of the fourth transistor of N transistors in the first impedance regulation subcircuit 21 is 8 kΩ, which can achieve that the impedances of the impedance regulation circuit 20 are adjusted from 0 kΩ to 15 kΩ at equal intervals.
In an embodiment, the control module 30 may be provided to simultaneously control gate potentials of the i-th transistors in the first impedance regulation subcircuits 21 through the i-th output terminals to control the switching degree of the i-th transistors in the first impedance regulation subcircuit 21. As shown in
If the control module 30 outputs the voltage signal to gates of transistors in each impedance regulation circuit 20 to control the switching degree of the transistors, the number of transistors in the impedance regulation circuit 20 can be provided according to the situation. For example, each first impedance regulation subcircuit 21 may include only one transistor, as shown in
In an embodiment, the control module 30 may further include N cascaded first shift latch modules. Each stage of first shift latch module receives and latches a shift signal output from a previous-stage first shift latch module. The gate of the i-th transistor in each first impedance regulation subcircuit 21 is electrically connected to an i-th-stage first shift latch module.
As shown in
In an embodiment, a first-stage first shift latch module includes a first enable signal terminal STV1, and a k-th-stage first shift latch module includes a first shift signal enable terminal. Each stage of first shift latch module includes a first clock signal terminal CKV1 and an output terminal. A first shift signal enable terminal of the k-th-stage first shift latch module is connected to an output terminal of a (k−1)-th-stage first shift latch module. K is a positive integer greater than 1 and less than or equal to N. An output terminal of each stage of first shift latch module outputs a high level or a low level to a transistor gate to control the turn-on and turn-off of a transistor. In addition, an output terminal of the first shift latch module is connected to a first shift signal enable terminal of a next-stage first shift latch module for transmitting a shift signal to the first shift signal enable terminal of the next-stage first shift latch module. The control module 30 controls the impedance of each impedance regulation circuit 20 according to an input signal of the first enable signal terminal STV1 and an input signal of the first clock signal terminal CKV1.
The control module 30 is provided with N cascaded first shift latch modules to control the turn-on or turn-off of transistors in the first impedance regulation subcircuits 21. The input signal of the first enable signal terminal STV1 and the input signal of the first clock signal terminal CKV1 can control the signal state latched by each first shift latch module, and can be output to control the turn-on or turn-off of the transistors in the first impedance regulation subcircuits 21.
For example, in a frame of image period, the input signal of the first enable signal terminal STV1 remain a high level, and latch states of multi-stage first shift latch module of the control module 30 are 1, 1, 1, 1 in order. That is, all first shift latch modules from the first stage to the fourth stage output high levels to the transistors in the first impedance regulation subcircuits 21, and the transistors are controlled in a turn-on state. In this case, the impedances of the impedance regulation circuits 20 are minimum, the rising edge and falling edge of the scanning pulse signal are the steepest, and the electromagnetic interference is the strongest.
In a frame of image period, if the input signal of the first enable signal terminal STV1 remains a low level, the latch states of the multi-stage first shift latch module of the control module 30 are 0, 0, 0, 0 in order. That is, all first shift latch modules from the first stage to the fourth stage output low levels to the transistors in the first impedance regulation subcircuits 21, and the transistors are controlled in a turn-off state. In this case, the impedances of the plurality of impedance regulation circuits 20 are maximum, the rising edge and falling edge of the scanning pulse signal are the slowest, and the electromagnetic interference is the smallest.
Therefore, in this embodiment of the present disclosure, by selecting the waveform of the input signal of the first enable signal terminal STV1, the combination of turn-on and turn-off of the transistors in the plurality of first impedance regulation subcircuits 21 can be achieved under the control of the input signal of the first clock signal terminal CKV1, to adjust the waveform of the scanning pulse signal according to the EMI requirements of different products. For example,
The larger the impedances of the impedance regulation circuits 20 are, the slower the rising edge and falling edge of the scanning pulse signal are, and the smaller the electromagnetic interference is, but the longer the delay of the scanning pulse signal is. The delay of the scanning pulse signal is too long, which easily affects the display effect of the display panel. Therefore, in the practical application process, the electromagnetic interference and the delay of the scanning pulse signal need to be simultaneously considered according to the actual requirements of products.
This embodiment of the present disclosure does not limit the circuit structure of the first shift latch module as long as the latch function described in above embodiments can be achieved. In an embodiment, this embodiment of the present disclosure provides a circuit structure of a first shift latch module. The first shift latch module may consist of a corresponding active device or passive device. As shown in
An input terminal of the first inverter, a gate of the transistor M16 and a gate of the transistor M17 are each electrically connected to the first clock signal terminal CKV1, and a gate of the transistor M13 and a gate of the transistor M110 are each electrically connected to the output terminal of the first inverter. A first electrode of the transistor M11, a first electrode of the transistor M13, a first electrode of the transistor M17, and a first electrode of the transistor M111 are each electrically connected to a first level signal input terminal VGH, and a first electrode of the transistor M12, a first electrode of the transistor M16, a first electrode of the transistor M110, and a first electrode of the transistor M112 are each electrically connected to a second level signal input terminal VGL. A second electrode of the transistor M13 is electrically connected to a first electrode of the transistor M14, a second electrode of the transistor M14 and a second electrode of the transistor M15 are each electrically connected to a first node N1, and a gate of the transistor M14 and a gate of the transistor M15 are each electrically connected to the first enable signal terminal STV1 (or the first shift signal enable terminal). A first electrode of the transistor M15 is electrically connected to a second electrode of the transistor M16. A second electrode of the transistor M17 is electrically connected to a first electrode of the transistor M18. A second electrode of the transistor M18 and a second electrode of the transistor M19 are each electrically connected to the first node N1, and a gate of the transistor M18, a gate of the transistor M19, and the output terminals of the second inverter are each electrically connected to a second node N2. A first electrode of the transistor M19 is electrically connected to a second electrode of the transistor M110. An input terminal of the second inverter is electrically connected to the first node N1. The second node N2 is connected to an output terminal Next of the first shift latch module.
In the following, the transistors M11, M13, M14, M17, M18 and M111 are P-type transistors, and M12, M15, M16, M19, M110, and M112 are N-type transistors as examples, and the driving process of the first shift latch module is described as follows. The first clock signal input terminal CKV1 receives a first clock control signal CKV1 of the high level controlling the transistor M16 to be turned on. The first enable signal terminal STV1 (or the first shift signal enable terminal) receives the high level controlling the transistor M15 to be turned on. A second level signal of the low level received by the second level signal input terminal VGL is written into the first node N1 sequentially through the transistors M15 and M16 which are turned on, so that the input terminal of the second inverter electrically connected to the first node N1 inputs the second level signal of the low level. In this case, the output terminal of the second inverter outputs the first level signal of the high level received by the first level signal input terminal VGH to the second node N2. The output terminal Next of the first shift latch module electrically connected to the second node N2 outputs a shift signal Next of the high level.
In an embodiment, each impedance regulation circuit 20 may further include a second impedance regulation subcircuit. The second impedance regulation subcircuit includes M transistors connected in parallel. The Gate of a j-th transistor of the M transistors in the second impedance regulation subcircuit of each impedance regulation circuit 20 is electrically connected to a same output terminal of the control module 30. M is a positive integer greater than 1, and j is a positive integer less than or equal to M.
In the solution where multiple transistors in the second impedance regulation subcircuit are connected in parallel, the transistors may correspond to a resistor having an impedance when turned on. The resistor is infinite when the transistors are turned off. This embodiment of the present disclosure may use on-impedances of the transistors in the second impedance regulation subcircuit to achieve the adjustment of the impedances of the impedance regulation circuits 20. The output terminal of the control module 30 may output different level signals to control the turn-on or turn-off of the plurality of transistors in the second impedance regulation subcircuit. For example, a transistor having a relatively small channel width-to-length ratio may be selected so that the channel is completely pinched off and the resistor is infinite when the transistor is turned off, and the transistor is equivalent to a resistor when the transistor is turned on.
On-impedances of M transistors connected in parallel may be the same or different. For example, transistors having different on-impedances can be obtained by providing the communication width-to-length ratio of the transistors to be different.
Table 2 is an impedance regulation table of an impedance regulation circuit of the display panel shown in
As can be seen from the data in Table 2, compared with the transistors connected in series in the plurality of first impedance regulation subcircuit 21, the impedance regulation circuit 20 of the second impedance regulation subcircuit 22 in which the transistors connected in parallel has a smaller impedance adjustment range but high precision, which is more suitable for the EMI performance fine adjustment scenario. The transistors connected in series in the plurality of first impedance regulation subcircuit 21 are suitable for the EMI performance coarse adjustment scenario.
Table 2 only provides an example of the impedance adjustment of an impedance regulation circuit in conjunction with
In an embodiment, the control module 30 may be provided to simultaneously control gate potentials of the j-th transistors of M transistors in multiple second impedance regulation subcircuits 22 through the j-th output terminals to control the switching degree of the j-th transistors in the multiple second impedance regulation subcircuits 22. As shown in
In an embodiment, in this embodiment of the present disclosure, the control module 30 may further include M cascaded second shift latch modules. Each stage of second shift latch module receives and latches a shift signal output from a previous-stage second shift latch module. The gate of the j-th transistor in each second impedance regulation subcircuit 22 is electrically connected to a j-th-stage second shift latch module.
As shown in
Optionally, a first-stage second shift latch module includes a second enable signal terminal STV2, and a x-th-stage second shift latch module includes a second shift signal enable terminal. Each stage of second shift latch module of the four cascaded second shift latch modules includes a second clock signal terminal CKV2 and an output terminal. The second shift signal enable terminal of an x-th-stage second shift latch module is connected to an output terminal of a x−1-th-stage second shift latch module. x is a positive integer greater than 1 and less than or equal to M. An output terminal of each stage of second shift latch module of the four cascaded second shift latch modules outputs a high level or a low level to the transistor gate to control the turn-on and turn-off of the transistor. In addition, an output terminal of the second shift latch module is connected to a second shift signal enable terminal of a next-stage second shift latch module for transmitting a shift signal to the second shift signal enable terminal of the next-stage second shift latch module. The control module 30 controls the impedance of each impedance regulation circuit 20 according to an input signal of the second enable signal terminal STV2 and an input signal of the second clock signal terminal CKV2.
The control module 30 is provided with M cascaded second shift latch modules to control the turn-on or turn-off of the transistors in the second impedance regulation subcircuits 22. The input signal of the second enable signal terminal STV2 and the input signal of the second clock signal terminal CKV2 can control the signal state latched by each second shift latch module, and can be output to control the turn-on or turn-off of the transistors in the second impedance regulation subcircuits 22.
The latch output working principle of M cascaded second shift latch modules is similar to the latch output working principle of N cascaded first shift latch modules. The second shift latch module may also refer to the circuit structure shown in
In an embodiment, the impedance regulation circuits 20 in this embodiment of the present disclosure may employ a solution in which transistors are connected in parallel and a solution in which transistors are connected in series at the same time. As shown in
In an embodiment, as shown in
In other embodiments, this embodiment of the present disclosure may also provide the control module 30 in a non-display region of the display panel. As shown in
For convenience of description, a signal terminal and a signal transmitted by the signal terminal are denoted by the same reference numeral. For example, the first enable signal terminal and the first enable signal are each denoted by STV1, and the first clock signal terminal and the first clock signal each are denoted by CKV1.
This embodiment of the present disclosure further provides a display device. The display device includes the display panel described in any embodiment of the present disclosure. Therefore, the display device according to this embodiment of the present disclosure has corresponding effects of the display panel according to this embodiment of the present disclosure, which is not repeated here. In an embodiment, the display device may be a mobile phone, a computer, a smart wearable device (for example, a smart watch), an onboard display device, and other electronic devices, which is not limited in this embodiment of the present disclosure. In an embodiment,
In the display panel and the display device according to this embodiment of the present disclosure, the plurality of impedance regulation circuits 20 are in series connection with the each stage of first shift register 11 in the gate drive circuit, and the impedances of the plurality of transistors in the plurality of impedance regulation circuits 20 are adjusted by the control module 30. The output waveform of the gate drive circuit is adjusted according to different EMI requirement standards of the electronic products integrated with the display panel to configure optimal EMI performance for the electronic products with different EMI requirement standards.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202011503062.6 | Dec 2020 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/074032 | 1/28/2021 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2022/126835 | 6/23/2022 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 10620676 | Tejada et al. | Apr 2020 | B1 |
| 20100214206 | Yokoyama et al. | Aug 2010 | A1 |
| 20100277458 | Liu et al. | Nov 2010 | A1 |
| 20180122322 | Ji et al. | May 2018 | A1 |
| 20190340969 | Hu et al. | Nov 2019 | A1 |
| 20190362685 | Tsai et al. | Nov 2019 | A1 |
| 20210074219 | Hung | Mar 2021 | A1 |
| Number | Date | Country |
|---|---|---|
| 1790473 | Jun 2006 | CN |
| 100377196 | Mar 2008 | CN |
| 100399386 | Jul 2008 | CN |
| 101308705 | Nov 2008 | CN |
| 101847375 | Sep 2010 | CN |
| 103177681 | Jun 2013 | CN |
| 109416902 | Mar 2019 | CN |
| 110969999 | Apr 2020 | CN |
| 110992863 | Apr 2020 | CN |
| Number | Date | Country | |
|---|---|---|---|
| 20220398992 A1 | Dec 2022 | US |
