The present invention relates to a display panel, and more particularly to a technique for suppressing the occurrence of flicker in a display panel having no light-shielding layer in a picture-frame region.
Meanwhile, in recent years, there has been a case in which a liquid crystal panel that requires UV (Ultra Violet Ray) irradiation, such as a panel using PNLC (Polymer Network Liquid Crystal element), is adopted in a display device. In such a liquid crystal panel requiring UV irradiation, if a black matrix is provided in a picture-frame region, then sufficient UV irradiation is not performed in a boundary portion between a display region and the picture-frame region, causing degradation in display quality (e.g., peripheral nonuniformity). Hence, as shown in
Note that, in connection with the invention of the present application, Japanese Patent No. 2959123 discloses an invention of a liquid crystal display device 903 that prevents application of a direct-current voltage to a liquid crystal layer by providing an electrode (peripheral electrode) 910 around a display region 905 as shown in
However, in a liquid crystal panel requiring UV irradiation, i.e., a liquid crystal panel having no black matrix in a picture-frame region, flicker may be visually recognized in the picture-frame region. This will be described below.
Here, when taking a look at a given electrical wiring line 934, if the electrical wiring line 934 is a power supply wiring line, then, for example, a potential of 0 V is continuously provided to the electrical wiring line 934. On the other hand, to a counter electrode 942 on the color filter substrate 940 are alternately provided, for example, a potential of 0 V and a potential of 5 V every horizontal scanning period. At this time, in the picture-frame region, a voltage of 0 V and a voltage of 5 V are alternately applied between the counter electrode 942 and the electrical wiring lines 934 (see reference numeral 96 in
In the liquid crystal display device 903 disclosed in the above-described Japanese Patent No. 2959123, as shown in
Furthermore, in the liquid crystal panel 901 having the black matrix 944 (see
An object of the present invention is therefore to suppress the occurrence of flicker in a picture-frame region of a display panel having no black matrix in the picture-frame region. Another object of the present invention is to provide a display panel with excellent designability in a picture-frame region.
A first aspect of the present invention is directed to a display panel that comprises a display region for displaying an image and a picture-frame region which is a peripheral region of the display region, and that has at least one substrate, a display element, a first electrode provided in the display region on the substrate to display an image, and a second electrode disposed to face the first electrode with the display element interposed therebetween, to apply a voltage according to an image to be displayed between the first electrode and the second electrode, the display panel comprising:
a peripheral electrode formed in the picture-frame region on the substrate in such a way as to cover at least a part of an electrical wiring line arranged in the picture-frame region on the substrate, the electrical wiring line being arranged in such a way as to face the second electrode with the display element interposed therebetween, the peripheral electrode being formed to face the electrical wiring line with an insulating film interposed between; and
a peripheral-electrode-giving-potential generating circuit that provides a potential to the peripheral electrode, the potential being determined according to a control signal provided from an external source, wherein
a light-shielding layer is not provided in the picture-frame region.
According to a second aspect of the present invention, in the first aspect of the present invention,
the peripheral electrode is formed in the picture-frame region on the substrate in such a way as to surround the display region.
According to a third aspect of the present invention, in the first aspect of the present invention,
the peripheral electrode is formed in such a way as to cover all of the electrical wiring line.
According to a fourth aspect of the present invention, in the first aspect of the present invention,
the control signal is a binary signal, and
the peripheral-electrode-giving-potential generating circuit provides a potential having a predetermined potential difference from a potential provided to the second electrode, or a potential equal to the potential provided to the second electrode, to the peripheral electrode according to a value of the control signal.
According to a fifth aspect of the present invention, in the fourth aspect of the present invention,
a first potential and a second potential are alternately provided to the second electrode every predetermined period, the first potential being a predetermined high-level potential and the second potential being a predetermined low-level potential, and
the peripheral-electrode-giving-potential generating circuit:
According to a sixth aspect of the present invention, in the first aspect of the present invention,
the first electrode is a pixel electrode to which a potential according to the image to be displayed is provided, the second electrode is a counter electrode provided to apply a voltage between the pixel electrode and the second electrode, and the display element is a liquid crystal element.
According to a seventh aspect of the present invention, in the first aspect of the present invention,
the first electrode is an anode electrode, the second electrode is a cathode electrode, and the display element is an organic electroluminescence element.
An eighth aspect of the present invention is directed to a display device comprising a display panel according to any one of the first through the seventh aspects of the present invention.
According to the first aspect of the present invention, a peripheral electrode is formed in a picture-frame region on a substrate composing a display panel, in such a way as to cover an electrical wiring line. In addition, peripheral-electrode-giving-potential generating circuit that provides a predetermined potential to the peripheral electrode is provided in the display panel. A potential provided to the peripheral electrode is determined according to a control signal provided to the peripheral-electrode-giving-potential generating circuit from an external source. Hence, for example, a potential can be provided to the peripheral electrode such that the voltage between a second electrode and the peripheral electrode is constant. By this, in a region of the picture-frame region where the peripheral electrode is formed, a constant voltage is applied to a display element during the operation of the display panel. As a result, the occurrence of flicker in the picture-frame region caused by variations in applied voltage to the display element is suppressed.
According to the second aspect of the present invention, since the peripheral electrode is formed in such a way as to surround a display region, while the outer area of the display region is allowed to have the same color (uniform color), the occurrence of flicker in the picture-frame region can be suppressed.
According to the third aspect of the present invention, since the peripheral electrode is formed in such a way as to cover all of the electrical wiring line, the occurrence of, flicker in the picture-frame region caused by variations in applied voltage to the display element can be reliably prevented.
According to the fourth aspect of the present invention, a potential having a predetermined potential difference from a potential of the second electrode, or a potential equal to the potential of the second electrode is provided to the peripheral electrode according to the value of the control signal provided to the peripheral-electrode-giving-potential generating circuit. Hence, by changing the value of the control signal, the magnitude of a voltage applied between the second electrode and the peripheral electrode can be changed. In other words, the color of the picture-frame region can be set to different colors as necessary. By this, a display panel is implemented that is superior in designability to conventional ones, while suppressing the occurrence of flicker in the picture-frame region.
According to the fifth aspect of the present invention, a potential for black display or a potential for white display is provided to the peripheral electrode according to the value of the control signal provided to the peripheral-electrode-giving-potential generating circuit. Hence, the color of the picture-frame region can be appropriately set to black or white. By this, as with the fourth aspect of the present invention, a display panel is implemented that is superior in designability to conventional ones, while suppressing the occurrence of flicker in the picture-frame region.
According to the sixth aspect of the present invention, a liquid crystal panel that provides the same effect as that obtained in the first aspect of the present invention is implemented.
According to the seventh aspect of the present invention, an organic EL panel that provides the same effect as that obtained in the first aspect of the present invention is implemented.
According to the eighth aspect of the present invention, a display device including a display panel that provides the same effect as that obtained in any of the first to seventh aspects of the present invention is implemented.
An embodiment of the present invention will be described below with reference to the accompanying drawings.
<1. Configuration of a Liquid Crystal Panel>
Meanwhile, in the present embodiment, as a display element, the above-described PNLC (Polymer Network Liquid Crystal element) is adopted. Hence, a black matrix serving as a light-shielding layer is not provided in the liquid crystal panel 100 according to the present embodiment. On the other hand, in the picture-frame region on the TFT array substrate 130 is formed the above-described peripheral electrode 110 in such a way as to cover the electrical wiring lines 134. Note that an insulating film 136 is provided between the peripheral electrode 110 and the electrical wiring lines 134 to provide an electrically nonconducting state therebetween.
Note that the voltage generating circuit 180 may be provided on the inner side than the sealing material 120 or may be provided on the outer side than the sealing material 120. Note, however, that in the case of a configuration in which the voltage generating circuit 180 is provided on the inner side than the sealing material 120, it is preferable that the peripheral electrode 110 be formed in such a way as to cover not only the electrical wiring lines 134 but also the voltage generating circuit 180.
In a configuration such as that described above, in the display region 105, voltages corresponding to potential differences between the potentials of the pixel electrodes 132 and the potential of the counter electrode 142 are applied to the liquid crystal layer 150, whereby display according to the voltages is performed. On the other hand, in the picture-frame region, a voltage corresponding to a potential difference between the potential of the peripheral electrode 110 and the potential of the counter electrode 142 is applied to the liquid crystal layer 150, whereby display according to the voltage is performed.
Note that, in the present embodiment, a first electrode is implemented by the pixel electrode 132, a second electrode is implemented by the counter electrode 142, and a peripheral-electrode-giving-potential generating circuit is implemented by the voltage generating circuit 180.
<2. Configuration and Operation of the Voltage Generating Circuit>
Connection relationships between the components in the voltage generating circuit 180 are as follows. As for the inverter 181, the input terminal is connected to the third input terminal 193, and has the output terminal is connected to the input terminal of the inverter 182, the gate terminal of the P-type TFT of the CMOS switch 183, and the gate terminal of the N-type TFT of the CMOS switch 184. As for the inverter 182, the input terminal is connected to the output terminal of the inverter 181, the gate terminal of the P-type TFT of the CMOS switch 183, and the gate terminal of the N-type TFT of the CMOS switch 184, and the output terminal is connected to the gate terminal of the N-type TFT of the CMOS switch 183 and the gate terminal of the P-type TFT of the CMOS switch 184.
As for the CMOS switch 183, the input terminal is connected to the first input terminal 191, the output terminal is connected to the input terminal of the inverter 185 and the output terminal of the CMOS switch 184, the gate terminal of the N-type TFT is connected to the output terminal of the inverter 182 and the gate terminal of the P-type TFT of the CMOS switch 184, and the gate terminal of the P-type TFT is connected to the output terminal of the inverter 181, the input terminal of the inverter 182, and the gate terminal of the N-type TFT of the CMOS switch 184. As for the CMOS switch 184, the input terminal is connected to the second input terminal 192, the output terminal is connected to the input terminal of the inverter 185 and the output terminal of the CMOS switch 183, the gate terminal of the N-type TFT is connected to the output terminal of the inverter 181, the input terminal of the inverter 182, and the gate terminal of the P-type TFT of the CMOS switch 183, and the gate terminal of the P-type TFT is connected to the output terminal of the inverter 182 and the gate terminal of the N-type TFT of the CMOS switch 183.
As for the inverter 185, the input terminal is connected to the output terminal of the CMOS switch 183 and the output terminal of the CMOS switch 184, and the output terminal is connected to the input terminal of the inverter 186. As for the inverter 186, the input terminal is connected to the output terminal of the inverter 185, and the output terminal is connected to the first output terminal 194. Note that the first output terminal 194 is connected to the peripheral electrode 110.
In a configuration such as that described above, signals VA and VB of potentials to be provided to the peripheral electrode 110 are provided to the first input terminal 191 and the second input terminal 192. Note that in the following the signal VA provided to the first input terminal 191 is referred to as the “first peripheral electrode potential setting signal” and the signal VB provided to the second input terminal 192 is referred to as the “second peripheral electrode potential setting signal”. To the third input terminal 193 is provided a control signal DMYCTL for controlling a potential provided to the peripheral electrode 110. A signal of a potential provided to the peripheral electrode 110 is outputted from the first output terminal 194 as an output signal DMYOUTZ.
Next, the operation of the voltage generating circuit 180 will be described.
Here, when the logic level of the control signal DMYCTL provided to the voltage generating circuit 180 is set to a high level, a low-level signal is outputted from the output terminal of the inverter 181 and a high-level signal is outputted from the output terminal of the inverter 182. By this, the CMOS switch 183 is placed in an on state and the CMOS switch 184 is placed in an off state. As a result, the first peripheral electrode potential setting signal VA is provided to the input terminal of the inverter 185. The signal provided to the input terminal of the inverter 185 is inverted by the inverter 185 and is further inverted by the inverter 186. Accordingly, the potential of an output signal DMYOUTZ becomes the potential of the first peripheral electrode potential setting signal VA. In other words, the potential of the first peripheral electrode potential setting signal VA is provided to the peripheral electrode 110. By this, as understood from
On the other hand, when the logic level of the control signal DMYCTL provided to the voltage generating circuit 180 is set to a low level, a high-level signal is outputted from the output terminal of the inverter 181 and a low-level signal is outputted from the output terminal of the inverter 182. By this, the CMOS switch 183 is placed in an off state and the CMOS switch 184 is placed in an on state. As a result, the second peripheral electrode potential setting signal VB is provided to the input terminal of the inverter 185. The signal provided to the input terminal of the inverter 185 is inverted by the inverter 185 and is further inverted by the inverter 186. Accordingly, the potential of an output signal DMYOUTZ becomes the potential of the second peripheral electrode potential setting signal VB. In other words, the potential of the second peripheral electrode potential setting signal VB is provided to the peripheral electrode 110. By this, as understood from
<3. Effects>
According to the present embodiment, the peripheral electrode 110 is formed in the picture-frame region on the TFT array substrate 130 composing the liquid crystal panel 100, in such a way as to cover the electrical wiring lines 134. In addition, the voltage generating circuit 180 for providing a predetermined potential to the peripheral electrode 110 is provided in the liquid crystal panel 100. To the peripheral electrode 110 is provided a potential equal to a counter potential or a potential reverse to the counter potential, according to a control signal DMYCTL provided to the voltage generating circuit 180 from an external source. Note that the “potential reverse to the counter potential” refers to a potential which has a polarity reverse to that of the counter potential with respect to a predetermined reference potential (2.5 V in an example shown in
Note that, in the case in which the display mode of the liquid crystal panel 100 is a normally black mode, when the logic level of a control signal DMYCTL provided to the voltage generating circuit 180 is set to a high level, white display is performed in the picture-frame region, and when the logic level of the control signal DMYCTL is set to a low level, black display is performed in the picture-frame region.
According to the present, embodiment, by changing the logic level of a control signal DMYCTL provided to the voltage generating circuit 180, the color of the picture-frame region can be set to black or can be set to white. As such, the liquid crystal panel 100 which is also superior in terms of design to conventional ones is implemented. Note that, in the voltage generating circuit 180 shown in
<4. Variant>
Although, in the above-described embodiment, description is made using a liquid crystal panel as an example of a display panel, the present invention is not limited thereto and the present invention can also be applied to an organic EL panel using an organic electroluminescence element, which will be described with reference to
<5. Others>
Although in the above-described embodiment the peripheral electrode 110 is formed in such away as to surround the display region 105, the present invention is not limited thereto. For example, when electrical wiring lines 134 are formed only in picture-frame regions of two sides among picture-frame regions of four sides surrounding the display region 105, the configuration may be such that a peripheral electrode 110 is provided only in the picture-frame regions of two sides where the electrical wiring lines 134 are formed. In addition, the peripheral electrode 110 does not necessarily need to be formed in such a way as to coverall of the electrical wiring lines 134. For example, the peripheral electrode 110 does not need to be formed on those electrical wiring lines 134 formed at a location where flicker is not visually recognized even if a viewer views the liquid crystal panel 100 in oblique directions as shown in
Number | Date | Country | Kind |
---|---|---|---|
2009-118470 | May 2009 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/JP2010/052023 | 2/12/2010 | WO | 00 | 6/9/2011 |