Patent Application
20250095570
The present disclosure relates to the field of display technologies, in particular, relates to a display panel and a display device.
Organic light emitting diode (OLED) display panels are commonly used in various display devices due to their advantages such as spontaneous emission, rapid response, and wide viewing angles.
A display panel and a display device are provided. The technical solutions are as follows:
According to some embodiments, a display panel is provided. The display panel includes:
In some embodiments, the drive circuit includes a drive transistor, and the regulating circuit includes at least one regulation capacitor and a storage capacitor,
In some embodiments, the display panel further includes:
In some embodiments, the regulating circuit includes two regulation capacitors, wherein an overlapping portion between the first active layer and the second capacitor plate is configured to form one regulation capacitor connected in series between the drive power line and the initial power line, and an adjacent portion of the first active layer and the first capacitor plate is configured to form another regulation capacitor connected in series between the initial power line and the control node.
In some embodiments, the first active layer includes a first active portion and a second active portion connected in a first direction, wherein an orthographic projection of the second active portion onto the substrate is overlapped with the orthographic projection of the second capacitor plate onto the substrate, and an orthographic projection of the first active portion onto the substrate is not overlapped with the orthographic projection of the second capacitor plate onto the substrate;
In some embodiments, an area of the orthographic projection of the first active portion onto the substrate is smaller than an area of the orthographic projection of the second active portion onto the substrate.
In some embodiments, the metal portion includes a first metal segment extending along the first direction.
In some embodiments, the metal portion includes a second metal segment extending along a second direction, wherein the second direction intersects with the first direction.
In some embodiments, in the first direction, the first active layer and the second active layer are arranged in a staggered manner, and in the second direction that intersects with the first direction, the first active layer and the second active layer are arranged at intervals;
In some embodiments, the control circuit includes:
In some embodiments, the compensation control line and the gate line are independent of each other; within a refresh cycle, a period for the compensation control line providing a compensation control signal of an active potential is overlapped with a period for the first reset control line providing a first reset control signal of an active potential, and a number of times that the compensation control line provides the compensation control signal of the active potential and a number of times that the first reset control line provides the first reset control signal of the active potential are both greater than or equal to 3,
In some embodiments, the light-emitting control line includes a first light-emitting control line and a second light-emitting control line, wherein
In some embodiments, the compensation control line is shared with the gate line; the control circuit further includes:
In some embodiments, during a frame refresh period of the display panel, the initial power line is configured to provide an initial power signal of a first potential,
According to some embodiments, a display device is provided. The display device includes a power supply assembly and the display panel according to any of the above embodiments,
To describe the technical solutions in the embodiments of the present disclosure more clearly, the following briefly describes the accompanying drawings required for describing the embodiments. Apparently, the accompanying drawings in the following description show merely some embodiments of the present disclosure, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.
For clearer descriptions of the objectives, technical solutions, and advantages of the present disclosure, embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings.
The transistors employed in all the embodiments disclosed herein can all be field-effect transistors or devices with similar characteristics. The transistors employed in the embodiments disclosed herein are primarily switch transistors based on their function in the circuit. Since the switch transistors employed herein have a symmetrical source and drain, the source and drain are interchangeable. In the embodiments disclosed herein, the source is referred to as the first electrode, and the drain is referred to as the second electrode. Alternatively, the drain is referred to as the first electrode, and the source terminal is referred to as the second electrode. As depicted in the accompanying drawings, the middle terminal of the transistor is designated as the gate, the signal input terminal as the source, and the signal output terminal as the drain. In addition, the switch transistors employed in the embodiments disclosed herein include either a P-type switch transistor or an N-type switch transistor. Specifically, the P-type switch transistor conducts when the gate is at a low level and cuts off when the gate is at a high level, while the N-type switch transistor conducts when the gate is at a high level and cuts off when the gate is at a low level. In addition, in each of the disclosed embodiments, multiple signals correspond to active and inactive potentials. The active and inactive potentials merely indicate that the potentials of the signals include two state quantities, and do not indicate that the active or inactive potentials throughout the entire text have specific numerical values.
The OLED display panel typically includes a substrate and a plurality of pixels disposed on one side of the substrate. Each pixel comprises a pixel circuit and a current-driven OLED light-emitting element. The pixel circuit is configured to transmit the drive current to the OLED light-emitting element, thereby driving the OLED light-emitting element to emit light. Currently, the transistors in the pixel circuit are made of a material known as low-temperature polycrystalline (LTPS), which possesses high electron mobility. Accordingly, these display panels are also referred to as LTPS-type OLED display panels.
In some practices, in display panels made of LTPS material such as OLED display panels, the Ioff of transistors within the pixel circuits (e.g., drive transistors for driving light-emitting elements) typically ranges around E−13, signifying a certain level of current leakage. This tendency leads to potential occurrences of screen flickering, as described in the background. Moreover, this flickering becomes more apparent during low-frequency displays. The reason behind this is that as the frequency decreases, the duration required to display a frame of an image increases correspondingly, and the duration of leakage also increases consequently. When the accumulated current leakage within a frame reaches a certain level, it results in changes in the display brightness of the display panel, easily perceivable by the human eye, manifesting as screen flickering.
To address the aforementioned screen flickering, it is necessary to stabilize the gate potential of the drive transistors, ensuring reduced current leakage within a frame during low-frequency displays. Extensive experimental research has revealed that if the current leakage within a frame can be maintained below 5%, the flickering phenomenon can be mitigated, even rendering it imperceptible to the human eye. Consequently, current efforts involve attempts to improve low-frequency display performance by incorporating transistors made of materials such as indium gallium zinc oxide (IGZO) around the gate of the drive transistors to block leakage paths. However, this arrangement necessitates the introduction of the IGZO process, leading to an increased number of masks required for manufacturing display panels. This impacts production capacity negatively, hampering the mass production of display panels.
Based on this, a display panel is provided according to the embodiments disclosed herein that effectively alleviates screen flickering while being conducive to mass production of the display panel.
Based on
The control circuit 0211 is coupled (i.e., electrically connected) respectively to the gate line Gate1, the data line Data, and the control node N1. The control circuit 0211 is configured to control the potential of the control node N1 based on the gate drive signal provided by the gate line Gate1 and the data signal provided by the data line Data.
The control terminal of the drive circuit 0212 is coupled to the control node N1, the input terminal of the drive circuit 0212 is coupled to the drive power line VDD, and the output terminal of the drive circuit 0212 is coupled to the light-emitting element 022. The drive circuit 0212 is configured to transmit a drive signal (e.g., a drive current) to the light-emitting element 022 based on the potential of the control node N1 and the drive power signal provided by the drive power line VDD, thereby driving the light-emitting element 022 to emit light. Accordingly, the drive circuit 0212 here includes the drive transistors as described in the aforementioned embodiments. Moreover, in the embodiments disclosed herein, the material for the drive transistors is LTPS, which exhibits a certain level of Ioff.
In some embodiments, referring to
The regulating circuit 0213 is coupled respectively to the drive power line VDD, the control node N1, and the initial power line Vinit0. The regulating circuit 0213 is configured to regulate the potential of the control node N1 through the coupling effect based on the initial power signal provided by the initial power line Vinit0 and the drive power signal provided by the drive power line VDD.
The flexible adjustment of the initial power signal increases, to some extent, the capacitance value at the control node N1, and reduces the impact of the cutoff current (Ioff) of the drive transistor in the drive circuit 0212 on the potential at the control node N1, resulting in better stability of the potential at the control node N1. Moreover, the channel electric field strength of the drive transistors can also be altered, and the electric field influences the distribution of defect particles at the channel interface, thereby adjusting the hysteresis state of the drive transistors. Combining the above two aspects improves the retention rate of the potential at the control node N1 within a frame, reducing the current leakage of the drive transistors. This improvement effectively alleviates screen flickering in the display panel, ensuring better display performance. The improvement is particularly noticeable during low-frequency displays (e.g., 40 Hz, 30 Hz, or even 24 Hz) of the display panel. In addition, since the regulating circuit 0213 adjusts the potential at the control node N1 through the coupling effect, the regulating circuit 0213 described in the embodiments disclosed herein is a non-transistor device such as a capacitor. Thus, compared with current transistors made of IGZO material, the manufacturing process for the display panel according to the embodiments disclosed herein is simpler and requires fewer masks, making it more suitable for mass production.
In summary, a display panel is provided according to the embodiments disclosed herein. The pixel circuit in the display panel includes a control circuit, a drive circuit, and a regulating circuit. The control circuit controls the potential of the coupled control node based on the gate drive signal provided by the gate line and the data signal provided by the data line. The drive circuit drives the light-emitting element to emit light based on the potential of the control node and the drive power signal provided by the drive power line. The regulating circuit adjusts the potential of the control node through the coupling effect based on the drive power signal and the initial power signal provided by the initial power line. The flexible adjustment of the initial power signal enhances the stability of the potential at the control node, and reduces the current leakage of the drive transistor within the drive circuit, thereby alleviating screen flickering in the display panel, and ensuring a better display performance of the display panel.
In some embodiments,
The data writing module 02111 is coupled respectively to the gate line Gate1, the data line Data, and the input terminal of the drive circuit 0212 (identified as node N2 in the figure). The data writing module 02111 is configured to control the connection and disconnection between the data line Data and the input terminal of the drive circuit 0212 based on the gate drive signal.
For example, the data writing module 02111, in the case that the potential of the gate drive signal is the first potential, enables the connection between the data line Data and the input terminal of the drive circuit 0212. At this point, the data signal provided by the data line Data is transmitted to the input terminal of the drive circuit 0212 to charge the input terminal of the drive circuit 0212. Moreover, the data writing module 02111, in the case that the potential of the gate drive signal is the second potential, decouples the data line Data from the input terminal of the drive circuit 0212.
In some embodiments disclosed herein, the first potential is the active potential, the second potential is the inactive potential, and the first potential is a lower potential relative to the second potential. Additionally, in some other embodiments, the first potential is a higher potential relative to the second potential.
The light-emitting control module 02112 is coupled respectively to the light-emitting control line EM, the drive power line VDD, the input terminal of the drive circuit 0212, the output terminal of the drive circuit 0212 (identified as node N3 in the figure), and the light-emitting element 022 (identified as node N4 in the figure). The light-emitting control module 02112 is configured to, based on the light-emitting control signal provided by the light-emitting control line EM, control the connection and disconnection between the drive power line VDD and the input terminal of the drive circuit 0212 and to control the connection and disconnection between the output terminal of the drive circuit 0212 and the light-emitting element 022.
For example, the light-emitting control module 02112, in the case that the potential of the light-emitting control signal is the first potential, enables the connection between the drive power line VDD and the input terminal of the drive circuit 0212 as well as the connection between the output terminal of the drive circuit 0212 and the light-emitting element 022. At this point, the drive power signal provided by the drive power line VDD is transmitted to the input terminal of the drive circuit 0212, and the potential at the output terminal of the drive circuit 0212 is further transmitted to the light-emitting element 022. Moreover, the light-emitting control module 02112, in the case that the potential of the light-emitting control signal is the second potential, decouples the drive power line VDD from the input terminal of the drive circuit 0212 and decouples the output terminal of the drive circuit 0212 from the light-emitting element 022. In other words, the drive circuit 0212 is indirectly coupled to the drive power line VDD and the light-emitting element 022 via this light-emitting control module 02112.
The compensation module 02113 is coupled respectively to the compensation control line V1, the output terminal of the drive circuit 0212 (i.e., node N3), and the control node N1. The compensation module 02113 is configured to control the connection and disconnection between the output terminal of the drive circuit 0212 and the control node N1 based on the compensation control signal provided by the compensation control line V1.
For example, the compensation module 02113, in the case that the potential of the compensation control signal is the first potential, enables the connection between the output terminal of the drive circuit 0212 and the control node N1. Moreover, the compensation module 02113, in the case that the potential of the compensation control signal is the second potential, decouples the output terminal of the drive circuit 0212 from the control node N1.
The first reset module 02114 is coupled respectively to the first reset control line Reset1, the first reset power line Vinit1, and the control node N1. The first reset module 02114 is configured to control the connection and disconnection between the first reset power line Vinit1 and the control node N1 based on the first reset control signal provided by the first reset control line Reset1.
For example, the first reset module 02114, in the case that the potential of the first reset control signal is the first potential, enables the connection between the first reset power line Vinit1 and the control node N1. At this point, the first reset power signal provided by the first reset power line Vinit1 is transmitted to the control node N1, achieving a reset of the control node N1. Moreover, the first reset module 02114, in the case that the potential of the first reset control signal is the second potential, decouples the first reset power line Vinit1 from the control node N1.
In some embodiments, as still another pixel circuit illustrated in
Based on this, within a refresh cycle, the period for the compensation control line V1 providing the compensation control signal of the active potential (i.e., the first potential) is overlapped with the period for the first reset control line Reset1 providing the first reset control signal of the active potential (i.e., the first potential). Additionally, the number of times that the compensation control line V1 provides the compensation control signal of the active potential and the number of times that the first reset control line Reset1 provides the first reset control signal of the active potential are both greater than or equal to 3.
As described in the aforementioned embodiments, the compensation control signal of the active potential is configured to enable the connection between the output terminal of the drive circuit 0212 and the control node N1, and the first reset control signal of the active potential is configured to enable the connection between the first reset power line and the control node N1. Accordingly, the period for the compensation control line V1 providing the compensation control signal of the active potential is also referred to as the turn-on period of the compensation control line V1. Similarly, the period for the first reset control line Reset1 providing the first reset control signal of the active potential is also referred to as the turn-on period of the first reset control line Reset1. The turn-on periods of both are overlapped, and the number of turn-on times for each is greater than or equal to 3.
In some embodiments, referring to
Additionally, in
In some embodiments, the period for the N−7-th second light-emitting control line EM2_N−7 providing the signal of the active potential (i.e., the turn-on period of the second light-emitting control line EM2_N−7) is overlapped with the period for the N-th second light-emitting control line EM2_N providing the signal of the active potential (i.e., the turn-on period of the second light-emitting control line EM2_N). Additionally, the period for the N-th second light-emitting control line EM2_N providing the signal of the active potential is overlapped with the period for the gate line Gate1 providing the gate drive signal of the active potential. The gate drive signal of active potential is configured to enable the connection between the data line Data and the input terminal of the drive circuit 0212. Accordingly, the period for the gate line Gate1 providing the gate drive signal of active potential is referred to as the turn-on period of the gate line Gate1.
Alternatively, in
In some embodiments, as yet still another pixel circuit illustrated in
The second reset module 02115 is coupled respectively to the second reset control line Reset2, the second reset power line Vinit2, and the input terminal (i.e., node N2) of the drive circuit 0212. The second reset module 02115 is configured to control the connection and disconnection between the second reset power line Vinit2 and the input terminal of the drive circuit 0212 based on the second reset control signal provided by the second reset control line Reset2.
For example, the second reset module 02115, in the case that the potential of the second reset control signal is the first potential, enables the connection between the second reset power line Vinit2 and the input terminal of the drive circuit 0212. At this point, the second reset power signal provided by the second reset power line Vinit2 is transmitted to the input terminal of the drive circuit 0212, achieving a reset of the input terminal of the drive circuit 0212. Moreover, the second reset module 02115, in the case that the potential of the second reset control signal is the second potential, decouples the second reset power line Vinit2 from the input terminal of the drive circuit 0212.
In some embodiments, referring to
For example, the third reset module 02116, in the case that the potential of the third reset control signal is the first potential, enables the connection between the third reset power line Vinit3 and the light-emitting element 022. At this point, the third reset power signal provided by the third reset power line Vinit3 is transmitted to the light-emitting element 022, achieving a reset of the light-emitting element 022. Moreover, the third reset module 02116, in the case that the potential of the third reset control signal is the second potential, decouples the third reset power line Vinit3 from the light-emitting element 022.
It should be noted that with respect to the structure illustrated in
In some embodiments, based on
Referring to
The gate of the drive transistor T1 is coupled to the control node N1, the first electrode of the drive transistor T1 is coupled to the drive power line VDD, and the second electrode of the drive transistor T1 is coupled to the light-emitting element 022. For example, the second electrode of the drive transistor T1 is coupled to the anode of the light-emitting element 022.
The at least one regulation capacitor C1 is connected in series between the drive power line VDD and the control node N1, and the at least one regulation capacitor C1 is also coupled to the initial power line Vinit0.
The storage capacitor Cst is connected in series between the drive power line VDD and the control node N1.
Exemplarily, each regulating circuit 0213 illustrated in
That is, the embodiments disclosed herein stabilize the potential of the control node N1 by arranging the regulation capacitors C1 coupled to the initial power line Vinit0, thereby reducing the current leakage of the drive transistor T1 and alleviating screen flickering in the display panel.
In some embodiments, referring to
In the structures illustrated in
In the structures illustrated in
In the structures illustrated in
In the structure illustrated in
In the structure illustrated in
In the structure illustrated in
Moreover, in the structure illustrated in
In some embodiments, referring to
In some embodiments disclosed herein, referring to
It should be noted that apart from the regulation capacitor C1, the pixel circuit structures illustrated in
Taking the circuit structure illustrated in
The semiconductor layer L0 is configured to form a first active layer Ac1 of the at least one regulation capacitor C1 and a second active layer Ac2 of the drive transistor T1. The first metal layer L1 and the second metal layer L2 are respectively configured to form a first capacitor plate Cst1 and a second capacitor plate Cst2 of the storage capacitor Cst. With reference to
In addition, the orthographic projection of the first active layer Ac1 onto the substrate 01 and the orthographic projection of the second active layer Ac2 onto the substrate 01 are both overlapped with the orthographic projection of the second capacitor plate Cst2 onto the substrate 01.
In some embodiments, taking the pixel circuits illustrated in
In some embodiments, referring to
In addition, the display panel further includes an insulating layer J1 and a third metal layer L3 disposed on one side of the second metal layer L2 distal to the substrate 01. The third metal layer L3 is configured to form a metal portion L31 coupled to the initial power line Vinit0. In addition, the metal portion L31 is overlapped with the first active portion Ac12 through a via hole K1 penetrating the insulating layer J1, allowing the initial power line Vinit0 to be coupled to at least one regulation capacitor C1.
That is, the orthographic projection of the portion where the metal portion L31 is overlapped with the first active layer Ac1 onto the substrate 01 is not overlapped with the orthographic projection of the second capacitor plate Cst2 onto substrate 01.
In some embodiments, the metal portion L31 includes a first metal segment extending along a first direction X1. And/or, the metal portion L31 includes a second metal segment extending along a second direction X2.
The second direction X2 intersects with the first direction X1. For example, as illustrated in
That is, in the embodiments disclosed herein, the initial power line Vinit is not limited to a specific connection path to the regulation capacitor C1. The initial power line may vertically (e.g., along the first direction X1, i.e., the pixel row direction) penetrate through the substrate 01 to connect to each pixel 02, or horizontally (e.g., along the second direction X2, i.e., the pixel column direction) penetrate through the substrate 01 to connect to each pixel 02. Moreover, within spatial constraints, the initial power line may penetrate through the substrate 01 in both horizontal and vertical directions in a mesh-like manner to connect to each pixel 02. The mesh-like layout reduces the loading.
In some embodiments, referring to
In some embodiments, referring to
In some embodiments, referring to
It should be noted that
Taking the structures illustrated in
Firstly, the operation principle of the structure illustrated in
During stage t1, the potential of the light-emitting control signal provided by the second light-emitting control line EM2_N−7 is a low potential, and the potentials of the light-emitting control signal provided by the first light-emitting control line EM1, the gate drive signal provided by the gate line Gate1, and the light-emitting control signal provided by the second light-emitting control line EM2_N are all high potentials. Accordingly, the first reset transistor T6 is turned on, while the data writing transistor T2, the first light-emitting control transistor T3, the second light-emitting control transistor T4, the compensation transistor T5, and the third reset transistor T8 are all turned off. At this point, the first reset power signal provided by the first reset power line Vinit1 is transmitted to the control node N1 through the turned-on compensation transistor T5, thereby achieving the reset of the control node N1.
During stage t2, the potentials of the light-emitting control signal provided by the second light-emitting control line EM2_N−7 and the light-emitting control signal provided by the second light-emitting control line EM2_N are both low potentials, and the potentials of the light-emitting control signal provided by the first light-emitting control line EM1 and the gate drive signal provided by the gate line Gate1 are both high potentials. Accordingly, the first reset transistor T6 and the compensation transistor T5 are both turned on, while the data writing transistor T2, the first light-emitting control transistor T3, the second light-emitting control transistor T4, and the third reset transistor T8 are all turned off. In addition, based on the reset of the control node N1 during stage t1, the drive transistor T1 is turned on. At this point, the first reset power signal provided by the first reset power line Vinit1 is transmitted to the control node N1 through the turned-on compensation transistor T5, to the node N3 through the turned-on compensation transistor T5, and to the node N2 through the turned-on drive transistor T1, thereby achieving the reset of the node N2 and the node N3.
During stage t3, the potentials of the light-emitting control signal provided by the second light-emitting control line EM2_N and the gate drive signal provided by the gate line Gate1 are both low potentials, and the potential of the light-emitting control signal provided by the second light-emitting control line EM2_N−7 and the potential of the light-emitting control signal provided by the first light-emitting control line EM1 are both high potentials. Accordingly, the data writing transistor T2, the third reset transistor T8, and the compensation transistor T5 are all turned on, while the first reset transistor T6, the first light-emitting control transistor T3, and the second light-emitting control transistor T4 are all turned off. In addition, based on the reset of the control node N1 during stage t1, the drive transistor T1 is turned on. At this point, the data signal provided by data line Data is transmitted to the node N2 through the turned-on data writing transistor T2 and is also transmitted to the node N3 and the control node N1 through the turned-on drive transistor T1 and compensation transistor T5, thereby achieving the charging of the control node N1. Moreover, the third reset power signal provided by the third reset power line Vinit3 is transmitted to the node N4 through the turned-on third reset transistor T8, thereby achieving the reset of the node N4.
After stage t3, in the case that the potential of the light-emitting control signal provided by the first light-emitting control line EM1 transitions to a low potential, causing both the first light-emitting control transistor T3 and the second light-emitting control transistor T4 to turn on, a path is established between the drive power line VDD and the pull-down power line VSS, thereby driving the light-emitting element 022 to emit light.
Secondly, the operation principle of the structure illustrated in
During stage t1, the potential of the first reset control signal provided by the first reset control line Reset1 is a low potential, and the potentials of the light-emitting control signal provided by the first light-emitting control line EM1, the light-emitting control signal provided by the second light-emitting control line EM2, and the gate drive signal provided by the gate line Gate1 are all high potentials. Accordingly, the first reset transistor T6 is turned on, while the data writing transistor T2, the first light-emitting control transistor T3, the second light-emitting control transistor T4, the compensation transistor T5, and the third reset transistor T8 are all turned off. At this point, the first reset power signal provided by the first reset power line Vinit1 is transmitted to the control node N1 through the turned-on compensation transistor T5, thereby achieving the reset of the control node N1.
During stage t2, the potentials of the first reset control signal provided by the first reset control line Reset1 and the gate drive signal provided by the gate line Gate1 transition between low and high potentials, and the potentials of both the light-emitting control signal provided by the first light-emitting control line EM1 and the light-emitting control signal provided by the second light-emitting control line EM2 remain high potentials. Accordingly, the first reset transistor T6 and the compensation transistor T5 are continuously turned on and turned off, while the data writing transistor T2, the first light-emitting control transistor T3, the second light-emitting control transistor T4, and the third reset transistor T8 all remain in the turned-off state. This allows for multiple times of refreshes and resets of the potential at the control node N1.
During stage t3, the potentials of the gate drive signal provided by the gate line Gate1 and the light-emitting control signal provided by the second light-emitting control line EM2 are both low potentials, and the potentials of the first reset control signal provided by the first reset control line Reset1 and the light-emitting control signal provided by the second light-emitting control line EM2 are both high potentials. Accordingly, the data writing transistor T2, the compensation transistor T5, and the third reset transistor T8 are all turned on, while the first light-emitting control transistor T3, the second light-emitting control transistor T4, and the first reset transistor T6 are all turned off. In addition, based on the reset of the control node N1 during stage t1, the drive transistor T1 is turned on. At this point, the data signal provided by data line Data is transmitted to the node N2 through the turned-on data writing transistor T2 and is also transmitted to the node N3 and the control node N1 through the turned-on drive transistor T1 and compensation transistor T5, thereby achieving the charging of the control node N1. Moreover, the third reset power signal provided by the third reset power line Vinit3 is transmitted to the node N4 through the turned-on third reset transistor T8, thereby achieving the reset of the node N4.
During stage t4, the potential of the light-emitting control signal provided by the second light-emitting control line EM2 is a low potential, and the potentials of the gate drive signal provided by the gate line Gate1, the first reset control signal provided by the first reset control line Reset1, and the light-emitting control signal provided by the second light-emitting control line EM2 are all high potentials. Accordingly, the data writing transistor T2 and the third reset transistor T8 are both turned on, while the first light-emitting control transistor T3, the second light-emitting control transistor T4, the compensation transistor T5, and the first reset transistor T6 are all turned off. At this point, the data signal provided by data line Data continues to be transmitted to the node N2 through the turned-on data writing transistor T2 to refresh the potential at the node N2. Moreover, the third reset power signal provided by the third reset power line Vinit3 is transmitted to the node N4 through the turned-on third reset transistor T8, thereby achieving the reset of the node N4.
After stage t4, in the case that the potential of the light-emitting control signal provided by the first light-emitting control line EM1 transitions to a low potential, causing both the first light-emitting control transistor T3 and the second light-emitting control transistor T4 to turn on, a path is established between the drive power line VDD and the pull-down power line VSS, thereby driving the light-emitting element 022 to emit light.
In addition, with reference to
During stage t5, the data writing transistor T2 and the third reset transistor T8 are both turned on, while the rest of the transistors are all turned off. At this point, the data signal provided by data line Data is transmitted to the node N2 through the turned-on data writing transistor T2, and the third reset power signal provided by the third reset power line Vinit3 is transmitted to the node N4 through the turned-on third reset transistor T8, achieving the refresh and reset for the node N2 and the node N4. In the case that the potential of the light-emitting control signal provided by the first light-emitting control line EM1 transitions to a low potential, causing the establishment of a path between the drive power line VDD and the pull-down power line VSS, the light-emitting element 022 continues emitting light within the frame hold period.
Moreover, referring to
In some embodiments,
Comparing the brightness waveform before and after improvement in
In summary, a display panel is provided according to the embodiments disclosed herein. The pixel circuit in the display panel includes a control circuit, a drive circuit, and a regulating circuit. The control circuit controls the potential of the coupled control node based on the gate drive signal provided by the gate line and the data signal provided by the data line. The drive circuit drives the light-emitting element to emit light based on the potential of the control node and the drive power signal provided by the drive power line. The regulating circuit adjusts the potential of the control node through the coupling effect based on the drive power signal and the initial power signal provided by the initial power line. The flexible adjustment of the initial power signal enhances the stability of the potential at the control node, and reduces the current leakage of the drive transistor within the drive circuit, thereby alleviating screen flickering in the display panel, and ensuring a better display performance of the display panel.
The power supply assembly J1 is coupled to the display panel 00 and is configured to supply power to the display panel 00.
In some embodiments, the display device is any product or component with display functionality such as an OLED device, a mobile phone, a tablet, a television, or a monitor.
It should be noted that in the accompanying drawings, the sizes of the layers and regions may be exaggerated for clarity of illustration. Also, it should be understood that in the case that an element or layer is referred to as being “on” another element or layer, it may be directly on the other element, or an intermediate layer may be present. In addition, it should be understood that in the case that an element or layer is referred to as being “under” another element or layer, it may be directly under the other element, or one or more intermediate layers or elements may be present. In addition, it should also be understood that in the case that a layer or element is referred to as being “between” two layers or elements, it may be the only layer between the two layers or elements, or one or more intermediate layers or elements may also be present. Like reference numerals refer to like elements throughout the present disclosure.
Moreover, terms used in detailed description of the present disclosure are defined to merely explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in detailed description of the present disclosure should have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure belongs.
For example, in the embodiments disclosed herein, the terms “first” and “second” are used solely for descriptive purposes and should not be construed as indicating or implying relative importance. The term “a plurality of” refers to two or more, unless otherwise explicitly defined.
Likewise, “a”, “an” or similar words do not denote a quantity limitation, but indicate the presence of at least one.
“Include”, “comprise” or similar words imply that the elements or items preceding the word “include” or “comprise” cover the elements or items listed after the word “include” or “comprise” as well as their equivalents, without excluding other elements or items.
“Up”, “down”, “left”, “right” or the like is only defined to indicate relative position relationship. In the case that the absolute position of the described object is changed, the relative position relationship may be changed accordingly. “Connected” or “coupled” refers to an electrical connection.
“And/or” indicates that three relationships may be present. For example, A and/or B may indicate that only A is present, both A and B are present, and only B is present. The symbol “/” generally indicates an “or” relationship between the associated objects.
Described above are merely optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalents, improvements, and the like, made within the spirit and principle of the present disclosure, should be included in the protection scope of the present disclosure.
The present disclosure is a U.S. national stage of international application No. PCT/CN2023/084434, filed on Mar. 28, 2023, the disclosure of which is herein incorporated by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/084434 | 3/28/2023 | WO |
