Patent Application
20240177672
This application claims priority to Chinese Patent Application No. 202310099990.8 filed Feb. 6, 2023, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technologies and in particular, to a display panel and a display device.
Since the self-luminous display panel is usually provided with a light-emitting element, no backlight module that is used for providing light sources needs to be set. As a result, the self-luminous display panel has the characteristics of being light, thin and simple in structure and has become a research focus in the current display field.
The luminescence of the light-emitting element in the display panel needs to be driven by a corresponding drive transistor. Generally, a data signal is provided for the gate of the drive transistor, and then the drive transistor converts the data signal into a drive current and supplies the drive current to the light-emitting element to drive the light-emitting element to emit light.
However, when the light-emitting element emits light, the drive transistor is in a bias state, and especially in the low-frequency display mode, the drive transistor is in the bias state for a long time. In this manner, the threshold voltage of the drive transistor is drifted, and hysteresis occurs in the drive transistor, thereby causing the display smear and affecting the display effect of the display panel.
The present disclosure provides a display panel and a display device to improve the display smear and improve the display effect of the display panel.
According to an aspect of the present disclosure, a display panel is provided. The display panel includes a display area; the display area includes a plurality of pixel circuits arranged in an array; each of the plurality of pixel circuits includes a drive transistor and a reset module.
The reset module is electrically connected to the gate of the drive transistor at a first node.
The reset module includes a first reset transistor and a second reset transistor; the first reset transistor and the second reset transistor are connected in series between a reset signal terminal and the first node; the gate of the first reset transistor is electrically connected to a first scan terminal, and the gate of the second reset transistor is electrically connected to a second scan terminal.
The channel type of the first reset transistor is different from the channel type of the second reset transistor; the duration of an effective pulse of a first scan signal of the first scan terminal is overlapped with durations of at least two effective pulses of a second scan signal of the second scan terminal.
According to another aspect of the present disclosure, a display device is provided. The display device includes the display panel described above.
It is to be understood that the contents described in this part are not intended to identify key or important features of the embodiments of the present disclosure and are not intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily apparent from the description hereinafter.
To illustrate solutions in embodiments of the present disclosure more clearly, the drawings used in the description of the embodiments will be briefly described below. Apparently, the drawings described below illustrate part of embodiments of the present disclosure, and those of ordinary skill in the art may obtain other drawings based on the drawings described below without any creative effort.
The solutions in embodiments of the present disclosure will be described clearly and completely in conjunction with the drawings in the embodiments of the present disclosure from which the solutions will be better understood by those skilled in the art. Apparently, the embodiments described below are part, not all, of the embodiments of the present disclosure. Based on the embodiments described herein, all other embodiments obtained by those of ordinary skill in the art without any creative effort are within the scope of the present disclosure.
It is to be noted that the terms “first”, “second” and the like in the description, claims and drawings of the present disclosure are used to distinguish between similar objects and are not necessarily used to describe a particular order or sequence. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the present disclosure described herein are capable of operation in sequences other than those illustrated or otherwise described herein. In addition, the terms “comprise”, “include” or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that contains a list of steps or units is not necessarily limited to those structures or units expressly listed herein but may include other structures or units not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background, when the drive transistor in the pixel circuit is kept in the bias state for a long time, the hysteresis effect occurs in the drive transistor. In this manner, when the screen is switched, the data signal of the screen that is to be switched to cannot be accurately written to the gate of the drive transistor, and the drive transistor cannot generate an accurate drive current, thereby causing the smear on the displayed screen and affecting the display effect of the display panel.
To solve the preceding problems, an embodiment of the present disclosure provides a display panel. The display panel includes a display area. The display area includes a plurality of pixel circuits arranged in an array. Each pixel circuit includes a drive transistor and a reset module, and the reset module is electrically connected to the gate of the drive transistor at a first node. The reset module includes a first reset transistor and a second reset transistor, and the first reset transistor and the second reset transistor are connected in series between a reset signal terminal and the first node. The gate of the first reset transistor is electrically connected to a first scan terminal, and the gate of the second reset transistor is electrically connected to a second scan terminal. The channel type of the first reset transistor is different from the channel type of the second reset transistor. The duration of the effective pulse of the first scan signal of the first scan terminal is overlapped with durations of at least two effective pulses of the second scan signal of the second scan terminal.
In the preceding technical solution, when the first reset transistor and the second reset transistor that are different in channel type are set to be connected in series between the reset signal terminal and the first node, when the first reset transistor and the second reset transistor are simultaneously on, a reset signal of the reset signal terminal is controlled to be written to the first node to reset the gate of the drive transistor electrically connected to the first node. Further, when the duration of the effective pulse of the first scan signal received by the gate of the first reset transistor is set to be overlapped with durations of at least two effective pulses of the second scan signal received by the gate of the second reset transistor, the reset signal of the reset signal terminal resets the gate of the drive transistor at least twice within the overlapping duration of effective pulses of the first scan signal and the second scan signal. In this manner, the drive transistor is in a stable reset state, the data signal in the current drive cycle can be written to the gate of the drive transistor accurately, and the drive transistor can provide an accurate drive current according to the accurate data signal and drive the light-emitting element to emit light accurately, thereby improving the display smear and improving the display effect of the display panel.
The preceding is the core idea of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative effort are within the scope of the present disclosure. The technical solutions in the embodiments of the present disclosure are described clearly and completely hereinafter in conjunction with the drawings in the embodiments of the present disclosure.
The setting that the first reset transistor M11 and the second reset transistor M12 are connected in series between the reset signal terminal VREF and the first node N1 may be understood as follows: as shown in
With continued reference to
The setting that the channel type of the first reset transistor M11 is different from the channel type of the second reset transistor M12 may specifically be as follows: when the first reset transistor M11 is an N-channel transistor, the second reset transistor M12 may be a P-channel transistor; at this point, when the first scan signal s1 of the first scan terminal S1 is at a high level, the first reset transistor M11 is on, and when the first scan signal s1 of the first scan terminal S1 is at a low level, the first reset transistor M11 is off; accordingly, when the second scan signal s2 of the second scan terminal S2 is at a high level, the second reset transistor M12 is off, and when the second scan signal s2 of the second scan terminal S2 is at a low level, the second reset transistor M12 is on. In this manner, the duration of the effective pulse of the first scan signal s1 is the duration in which the first scan signal s1 is at a high level, and the duration of the effective pulse of the second scan signal s2 is the duration in which the second scan signal s2 is at a low level.
In other optional embodiments, the first reset transistor may also be a P-channel transistor, and the second reset transistor also be an N-channel transistor; at this point, when the first scan signal of the first scan terminal is at a low level, the first reset transistor is on, and when the first scan signal of the first scan terminal is at a high level, the first reset transistor is off; similarly, when the second scan signal of the second scan terminal is at a high level, the second reset transistor is on, and when the second scan signal of the second scan terminal is at a low level, the second reset transistor is off. In this manner, the duration of the effective pulse of the first scan signal is the duration in which the first scan signal is at a low level, and the duration of the effective pulse of the second scan signal is the duration in which the second scan signal is at a high level.
It is to be understood that both the high level and the low level are relative level signals and do not represent the polarity of the signals, and the embodiments of the present disclosure do not limit the polarity and specific values of the high level and the low level as long as the core invention point of the embodiments of the present disclosure can be achieved.
For ease of description, unless otherwise specified, the technical solutions in the embodiments of the present disclosure are illustrated through the example in which the first reset transistor M11 is an N-channel transistor and the second reset transistor M12 is a P-channel transistor.
The material of the active layer of the N-type transistor may include, but is not limited to, an oxide semiconductor material such as indium gallium zinc oxide (IGZO), and the material of the active layer of the P-type transistor may include, but is not limited to, a low-temperature polysilicon (LTPS) material. In this manner, the P-channel transistor has relatively high mobility and the N-channel transistor has a relatively low off-leakage current. In this manner, as shown in
For example,
Further, when the duration of the effective pulse of the first scan signal s1 of the first scan terminal S1 is overlapped with the durations of at least two effective pulses of the second scan signal s2 of the second scan terminal S2, the gate of the drive transistor T can be reset once within the duration in which the effective pulse of the first scan signal s1 is overlapped with each effective pulse of the second scan signal s2, and then the gate of the drive transistor T can be reset at least twice within the duration in which the first scan signal s1 is the effective pulse. In this manner, the data signal contained in the gate potential of the drive transistor T can be thoroughly cleared when the reset of the gate of the drive transistor T is finished, and the drive transistor T can be in a stable reset state, thereby facilitating the subsequent accurate writing of the data signal.
In the preceding embodiments of the present disclosure, the first reset transistor and the second reset transistor that are different in channel type are connected in series between the reset signal terminal and the first node so that when the first reset transistor and the second reset transistor are simultaneously on, a reset signal of the reset signal terminal is controlled to be written to the first node to reset the gate of the drive transistor electrically connected to the first node. Further, the duration of the effective pulse of the first scan signal received by the gate of the first reset transistor is overlapped with durations of at least two effective pulses of the second scan signal received by the gate of the second reset transistor so that within the overlapping duration of effective pulses of the first scan signal and the second scan signal, the reset signal of the reset signal terminal resets the gate of the drive transistor at least twice. In this manner, the drive transistor is in a stable reset state, the data signal in the current drive cycle can be written to the gate of the drive transistor accurately, and the drive transistor can provide an accurate drive current according to the accurate data signal and drive the light-emitting element to emit light accurately, thereby improving the display smear and improving the display effect of the display panel.
It is to be noted that in
Optionally, with continued reference to
It is to be understood that the duration in which the display panel displays one frame of a screen is equal to one drive cycle of one pixel circuit P. Within one drive cycle of the pixel circuit P, the first scan signal s1 of the first scan terminal S1 may include one effective pulse; the start time t2 of the effective pulse of the first scan signal s1 is the time when the first scan signal s1 changes from a low level to a high level, and the end time t4 of the effective pulse of the first scan signal s1 is the time when the first scan signal s1 changes from a high level to a low level. Similarly, within one drive cycle of the pixel circuit P, the second scan signal s2 of the second scan terminal S2 may include at least two effective pulses; the start time t2 of the first one effective pulse of the second scan signal s2 is the time when the second scan signal s2 jumps from a high level to a low level for the first time, and the end time t3 of the first one effective pulse of the second scan signal s2 is the time when the second scan signal s2 jumps from a low level to a high level for the first time; the start time t2′ of the last one effective pulse of the second scan signal s2 is the time when the second scan signal s2 jumps from a high level to a low level for the last time, and the end time t3′ of the last one effective pulse of the second scan signal s2 is the time when the second scan signal s2 jumps from a low level to a high level for the last time.
In the same pixel circuit P, when the start time t1 of the effective pulse of the first scan signal s1 is set to be before the start time t2 of the first one effective pulse of the second scan signal s2, the turn-on time of the first reset transistor M11 controlled by the first scan signal s1 can be before the first turn-on time of the second reset transistor M12 controlled by the second scan signal s2; when the end time t4 of the effective pulse of the first scan signal s1 is set to be after the end time t3 of the last one effective pulse of the second scan signal s2, the turn-off time of the first reset transistor M11 controlled by the first scan signal s1 can be after the turn-off time of the second reset transistor M12 controlled by the second scan signal s2. In this manner, the first reset transistor M11 is in the on state within the duration in which the second reset transistor M12 is on, the reset signal Vref of the reset signal terminal VREF can be written to the first node N1 through the first reset transistor M11 and the second reset transistor M12, and the duration in which the reset signal Vref is written to the first node N1 can be controlled by the duration of the effective pulse of the second scan signal s2 so that when the first scan signal s1 is the effective pulse the reset signal Vref can be provided for the first node N1 at least twice to reset the gate of the drive transistor T at least twice.
It is to be understood that since the width and number of the effective pulse of the first scan signal s1 are different from the width and number of the effective pulse of the second scan signal s2, different scan circuits need to be set to provide the first scan signal s1 and the second scan signal s2 for pixel circuits P, respectively.
Optionally,
The first scan terminals S1 of at least part of pixel circuits P in the same row are electrically connected to the same first scan line 141, that is, the first scan terminals S1 of part or all of the pixel circuits P in the same row are electrically connected to the same first scan line 141. Accordingly, the second scan terminals S2 of at least part of pixel circuits P in the same row are electrically connected to the same second scan line 142, that is, the second scan terminals S2 of part or all of the pixel circuits P in the same row are electrically connected to the same second scan line 142. The embodiments of the present disclosure do not specifically limit the case where the pixel circuits P in the same row share the first scan line 141 and the second scan line 142 as long as the core invention point of the embodiments of the present disclosure can be achieved. For ease of description, unless otherwise specified, the technical solutions in the embodiments of the present disclosure are illustrated through the example in which all of the pixel circuits P in the same row are electrically connected to the same first scan line and the second scan line 142, respectively.
With reference to
It is to be understood that each first scan unit 111 may include a signal input terminal and a signal output terminal. At this point, the signal input terminal of the first stage of first scan unit 111 receives a start pulse signal, and for the remaining stages of first scan units 111, the signal input terminal of each stage of first scan unit 111 is electrically connected to the signal output terminal of the previous stage of first scan unit 111. For example, the signal input terminal of the second stage of first scan unit 111 is electrically connected to the signal output terminal of the first stage of first scan unit 111, and the signal input terminal of the third stage of first scan unit 111 is electrically connected to the signal output terminal of the second stage of first scan unit 111. Similarly, each second scan unit 121 may include a signal input terminal and a signal output terminal. At this point, the signal input terminal of the first stage of second scan unit 121 receives a start pulse signal, and for the remaining stages of second scan units 121, the signal input terminal of each stage of second scan unit 121 is electrically connected to the signal output terminal of the previous stage of second scan unit 121. For example, the signal input terminal of the second stage of second scan unit 121 is electrically connected to the signal input terminal of the first stage of second scan unit 121, and the signal input terminal of the third stage of second scan unit 121 is electrically connected to the signal input terminal of the second stage of second scan unit 121. The signal output terminal of each stage of first scan unit 111 is used for outputting the first scan signal s1, and the signal output terminal of second scan unit 121 is used for outputting the second scan signal s2.
Each stage of first scan unit 111 is electrically connected to the adjacent N first scan lines 141 so that the pixel circuits P electrically connected to these adjacent N first scan lines 141 share the same first scan unit 111. In this manner, no first scan unit 111 needs to be set for each pixel circuit P electrically connected to each first scan line 141, thereby reducing the number of first scan circuits 111 set in the first scan circuit 110. Since the first scan circuit 110 is set in the non-display area NA of the display panel 100, the structure of the display panel 100 can be simplified when the number of first scan units 111 set in the first scan circuit 110 is small, thereby reducing the size of the non-display area NA and achieving the narrow bezel of the display panel 100. Further, the effective pulse of the first scan signal s1 outputted by each stage of first scan unit 111 is sequentially shifted, and the shift amount of the effective pulse of the first scan signal s1 outputted by each stage of first scan unit 111 is less than the width of the effective pulse of the first scan signal s1, that is, durations of effective pulses of the first scan signals s1 outputted by adjacent two or more cascaded first scan units 111 are overlapped. Compared with the case where durations of effective pulses of the first scan signals s1 outputted by adjacent two or more cascaded first scan units 111 are not overlapped, the preceding setting can effectively shorten the duration between the start time of the effective pulse of the first scan signal s1 outputted by the first stage of first scan unit 111 and the end time of the effective pulse of the first scan signal s1 outputted by the last stage of first scan unit 111, the duration for resetting the drive transistor T in each pixel circuit P is shortened, and the reset duration of each drive transistor T when the drive cycle of the pixel circuit P is fixed is shortened, thereby extending the duration of the light emission phase of each pixel circuit P. Since the display brightness of the display panel 100 is related to the integration of time by the human eye, that is, the longer the time, the larger the integration value and the stronger the display brightness of the display panel 100 perceived by the human eye, when the duration of the light emission phase is extended, the display brightness of the display panel 100 is improved, thereby improving the display effect of the display panel.
It is to be noted that in
Further, each stage of second scan unit 121 is electrically connected to one second scan line 142 so that pixel circuit Ps which are electrically connected to the same second scan line 121 and are located in the same row share the same second scan unit 121. The effective pulse of the second scan signal s2 outputted by each stage of the second scan unit 121 is sequentially shifted, and the shift amount of the effective pulse of the second scan signal s2 outputted by each stage of second scan unit 121 is greater than or equal to the width of the effective pulse of the second scan signal s2. At this point, durations of the effective pulses of the second scan signals s2 outputted by any adjacent N stages of second scan units 121 may not be overlapped each other so that the second reset transistors M12 in pixel circuits P that each are electrically connected to a respective one of successive N stages of second scan units 21 and are located in different rows are not simultaneously on. In this manner, although the first scan signal s1 outputted by each stage of first scan unit 111 can control the first reset transistors M11 in pixel circuits P that are electrically connected to N first scan lines 142 to be simultaneously on, since the reset signal Vref of the reset signal terminal VREF is written to the first node N1 only when both the first reset transistor M11 and the second reset transistor M12 are simultaneously on, the drive transistors T in pixel circuits P in different rows can be reset at different times when the second reset transistors M12 of the pixel circuits P in different rows are not simultaneously on.
It is to be noted that in
In an optional embodiment,
For example, the following is described using an example in which N is equal to 2, that is, one first scan unit 111 is electrically connected to the first scan terminals S1 of adjacent two rows of pixel circuits P through adjacent two first scan lines 141, and the second scan terminals S2 of these two rows of pixel circuits P are electrically connected to two second scan units 121 through two second scan lines 142, respectively. For example, the first scan terminal S1 of each of pixel circuits P in the first and second rows is electrically connected to the first stage of first scan unit 111 through two first scan lines 141, respectively, and the first scan terminal S1 of each of pixel circuits P in the third and fourth rows is electrically connected to the second stage of first scan unit 111 through two other first scan lines 141, respectively. The second scan terminal S2 of each of pixel circuits P in the first row is electrically connected to the first stage of second scan unit 121 through one second scan line 142, and the second scan terminal S2 of each of pixel circuits P in the second row is electrically connected to the second stage of second scan unit 121 through another second scan line 142. At this point, the effective pulse of the first scan signal s11 outputted by the first stage of first scan unit 111 is shifted by a certain shift amount from the effective pulse of the first scan signal s12 outputted by the second stage of first scan unit 111, and the shift amount is the first duration t11. In this manner, when the duration in which the first stage of first scan unit 111 outputs the effective pulse of the first scan signal s11 reaches t11, the second stage of first scan unit 111 starts to output the effective pulse of the first scan signal s12. The second scan unit 121 outputs each effective pulse of the second scan signal s2 at a duration t20. At this point, the sum of the duration t20 in which the first stage of second scan unit 121 outputs the first one effective pulse of the second scan signal s21 and the duration t20 in which the second stage of second scan unit 121 outputs the first one effective pulse of the second scan signal s22 is the second duration 2*t12. Since the first duration t11 is greater than or equal to the duration time 2*t20, before the second stage of first scan unit 111 starts to output the effective pulse of the first scan signal s12, the drive transistor T of each of pixel circuits P electrically connected to the first stage of first scan unit 111 can be reset at least once so that pixel circuits P electrically connected to different first scan units 111 can be reset at different time periods. Further, since in successive N stages of second scan units 121, the effective pulse of the second scan signal s2 outputted by each stage of second scan unit 121 is sequentially shifted and the duration in which each stage of second scan unit 121 outputs the effective pulse of the second scan signal s2 is not overlapped, the drive transistors T of pixel circuits P in different rows can be reset at different time periods. Therefore, the drive transistors T of pixel circuits P in different rows can be prevented from being reset simultaneously, and the normal working process of the display panel cannot be affected, thereby ensuring that the display panel normally displays and emits light.
Optionally, with continued reference to
The channel type of the data write transistor M2 may be the same as or different from the channel type of the first compensation transistor M31 and the embodiments of the present disclosure do not specifically limit the channel type of both. In an optional embodiment, the channel type of the data write transistor M2 may be different from the channel type of the first compensation transistor M31; that is, when the data write transistor M2 is a P-channel transistor, the first compensation transistor M31 is an N-channel transistor, or when the data write transistor M2 is an N-channel transistor, the first compensation transistor M31 is a P-channel transistor.
It is to be understood that if the first compensation transistor M31 is an N-channel transistor, when the third scan signal s3 of the third scan terminal S3 is at a low level, the first compensation transistor M31 is off, and when the third scan signal s3 of the third scan terminal S3 is at a high level, the first compensation transistor M31 is on. At this point, the duration in which the third scan signal s3 is at a high level is the duration of the effective pulse of the third scan signal s3. If the first compensation transistor M31 is a P-channel transistor, the first compensation transistor M31 is on under the control of the low level of the third scan signal s3, and the first compensation transistor M31 is off under the control of the high level of the third scan signal s3. At this point, the duration in which the third scan signal s3 is at a low level is the duration of the effective pulse of the third scan signal s3.
Accordingly, if the data write transistor M2 is a P-channel transistor, when the fourth scan signal s4 of the fourth scan terminal S4 is at a high level, the data write transistor M2 is off, and when the fourth scan signal s4 of the fourth scan terminal S4 is at a low level, the data write transistor M2 is on. At this point, the duration in which the fourth scan signal s4 is at a low level is the duration of the effective pulse of the fourth scan signal s4. If the data write transistor M2 is an N-channel transistor, the data write transistor M2 is on under the control of the high level of the fourth scan signal s4, and the data write transistor M2 is off under the control of the low level of the fourth scan signal s4. At this point, the duration in which the fourth scan signal s4 is at a high level is the duration of the effective pulse of the fourth scan signal s4.
The duration of the effective pulse of the third scan signal s3 of the third scan terminal S3 is overlapped with the duration of the effective pulse of the fourth scan signal s4 of the fourth scan terminal S4 so that the data write transistor M2 and the first compensation transistor M31 can be in the on state simultaneously within the overlapping duration, and at this point, the data signal Vdata of the data signal terminal DATA can be transmitted to the second node N2 through the data write transistor M2 that is on. If the drive transistor T is also in the on state at this point, the drive transistor T can transmit the data signal Vdata to the third node N3 and then to the gate of the drive transistor T through the first compensation transistor M31 that is on.
It is to be understood that since the drive transistor T needs to be in the on state when the data signal Vdata of the data signal terminal DATA is written to the gate of the drive transistor T, the gate of the drive transistor T may be reset through the reset signal Vref of the reset signal terminal VREF before the data signal is written to the gate of the drive transistor T. In this manner, when the data signal Vdata is written to the gate of the drive transistor T, the difference between the gate potential of the drive transistor T and the first electrode potential of the drive transistor T enables the drive transistor T to be in the on state. Therefore, the reset phase in which the gate of the drive transistor T is reset using the reset signal Vref of the reset signal terminal VREF is before the write phase in which the data signal is written to the gate of the drive transistor T. At this point, the duration of at least one effective pulse of the second scan signal s2 for controlling the on or off of the second reset transistor M12 is before the overlapping duration of the effective pulse of the third scan signal s3 and the effective pulse of the fourth scan signal s4. In an optional embodiment, durations of at least two effective pulses of the second scan signal s2 are before the overlapping duration of the effective pulse of the third scan signal s3 and the effective pulse of the fourth scan signal s4 so that the data signal Vdata can be written after the gate of the drive transistor Tis reset at least twice. In this manner, the gate potential of the drive transistor T can maintain the drive transistor T in the on state in the write phase of the data signal Vdata, thereby ensuring the accurate writing of the data signal Vdata of the data signal terminal DATA.
Further, the gate potential of the drive transistor T is consistent with the reset signal Vref of the reset signal terminal VREF before the data signal Vdata is written to the gate of the drive transistor T and after the gate of the drive transistor T is reset. As the data signal Vdata is written, the gate potential of the drive transistor T gradually changes until the potential between the gate potential of the drive transistor T and the first electrode potential of the drive transistor T is equal to a threshold voltage Vth of the drive transistor T, and the critical turn-on condition of the drive transistor T is reached. At this point, the gate potential of the drive transistor T is Vdata+Vth at the end of the write phase of the data signal Vdata. In this manner, after the write phase of the data signal Vdata is finished, the drive current provided by the drive transistor T according to its gate potential may be independent of its threshold voltage.
In an optional embodiment, with continued reference to
In an example embodiment, the light emission control transistor 40 may include a first light emission control transistor M41 and a second light emission control transistor M42. In the same pixel circuit P, when the channel types of the first light emission control transistor M41 and the second light emission control transistor M42 are the same, the gates of the first light emission control transistor M41 and the second light emission control transistor M41 can both be electrically connected to the same light emitting control terminal EM. The first electrode of the first light emission control transistor M41 is electrically connected to the positive power supply terminal PVDD, and the second electrode of the first light emission control transistor M41 is electrically connected to the first electrode of the drive transistor T at the second node N2. The second light emission control transistor M42 is electrically connected to the second electrode of the drive transistor T at the third node N3, the second light emission control transistor M42 is electrically connected to the anode of the light-emitting element D, and the cathode of the light-emitting element D is electrically connected to the negative power supply terminal PVEE. The duration of the effective pulse of the light emission control signal Em of the light emission control terminal EM is not overlapped with the duration of the effective pulse of the first scan signal s1, the duration of the effective pulse of the second scan signal s2, the duration of the effective pulse of the third scan signal s2 and the duration of the effective pulse of the fourth scan signal s4.
It is to be understood that the channel types of the first light emission control transistor M41 and the second light emission control transistor M42 are the same, that is, the first light emission control transistor M41 and the second light emission control transistor M42 are both N-channel transistors or P-channel transistors. If the first light emission control transistor M41 and the second light emission control transistor M42 are both N-channel transistors, when the light emission control signal Em of the light emission control terminal EM is at a high level, the first light emission control transistor M41 and the second light emission control transistor M42 are simultaneously on, and when the light emission control signal Em of the light emission control terminal EM is at a low level, the first light emission control transistor M41 and the second light emission control transistor M42 are simultaneously off. At this point, the duration of the effective pulse of the light emission control signal Em is the duration in which the light emission control signal Em is at a high level. If the first light emission control transistor M41 and the second light emission control transistor M42 are both P-channel transistors, when the light emission control signal Em of the light emission control terminal EM is at a low level, the first light emission control transistor M41 and the second light emission control transistor M42 are simultaneously on, and when the light emission control signal Em of the light emission control terminal Em is at a high level, the first light emission control transistor M41 and the second light emission control transistor M42 are simultaneously off. At this point, the duration of the effective pulse of the light emission control signal Em is the duration in which the light emission control signal Em is at a low level. The embodiments of the present disclosure do not specifically limit the channel types of the first light emission control transistor M41 and the second light emission control transistor M42 as long as the core invention point of the embodiments of the present disclosure can be achieved.
For example, the following is described using an example in which the first reset transistor M11 and the first compensation transistor M31 are N-channel transistors and the second reset transistor M12, the data write transistor M2, the first light emission control transistor M41, the second light emission control transistor M42 and the drive transistor T are all P-channel transistors.
In the first reset phase t21 of the current drive cycle, the first scan signal s1 is a high-level effective pulse, the second scan signal s2 is a low-level effective pulse, and the first reset transistor M11 and the second reset transistor M12 are simultaneously on. The reset signal of the reset signal terminal VREF is transmitted to the first node N1 through the first reset transistor M11 and the second reset transistor M12 that are on to reset the gate of the drive transistor T electrically connected to the first node N1 for the first time. After the first reset phase t21 of the pixel circuit P is finished, the first scan signal s1 of the pixel circuit P remains as a high-level effective pulse, and the second scan signal s2 jumps to a high level so that the second reset transistor M12 of the pixel circuit P is off.
In the second reset phase t22, the first scan signal s1 remains as a high-level effective pulse, the second scan signal s2 jumps again to a low-level effective pulse, and the first reset transistor M11 and the second reset transistor M12 are simultaneously on to reset the gate of the drive transistor T again. The reset signal Vref is provided for the gate of the drive transistor T again, and the drive transistor T is restored to the reset state to prevent the drive transistor T from not being restored to the reset state from the bias state of the previous drive cycle after the first reset. After the gate of the drive transistor T is reset twice, the potential of the first node N1 is consistent with the reset signal Vref so that the potential difference between the gate potential of the drive transistor T and the potential of the data signal corresponding to any display brightness can satisfy the condition under which the drive transistor T is accurately on.
In the write phase t30, the first scan signal s1 is at a low level, the second scan signal s2 is at a high level, and the first reset transistor M11 and the second reset transistor M12 are off. The third scan signal s3 is a high-level effective pulse, the fourth scan signal s4 is a low-level effective pulse, and the data write transistor M2 and the first compensation transistor M31 are on. The data signal Vdata of the data signal terminal DATA is transmitted to the second node N2 through the data write transistor M2 that is on to enable the first electrode potential of the drive transistor T to be equivalent to the voltage of the data signal Vdata. Since after the second reset phase t22, the gate potential of the drive transistor T is equivalent to the voltage of the reset signal Vref so that the potential difference between the gate of the drive transistor T and its first electrode is Vdata-Vref, and the drive transistor T is in the on state. The data signal Vdata continues to be transmitted to the third node N3 through the drive transistor T that is on and then transmitted to the gate of the drive transistor T through the first compensation transistor M31 electrically connected between the third node N3 and the first node N1 until the gate potential of the drive transistor T becomes Vdata+Vth. The potential difference between the gate of the drive transistor and its first electrode becomes Vth, the critical turn-on condition of the drive transistor T is reached, and the gate potential of the drive transistor T no longer changes.
In the light emission phase t40 after the write phase t30 is finished, the third scan signal s3 jumps to a low level, the fourth scan signal s4 jumps to a high level, and the data write transistor M2 and the first compensation transistor M31 are both off. The light emission control signal Em jumps to a low-level effective pulse, and the first light emission control transistor M41 and the second light emission control transistor M42 are on. Since the first light emission control transistor M41 is on, the positive power supply signal Pvdd of the positive power supply terminal PVDD is transmitted to the first electrode of the drive transistor T. At this point, the potential difference between the gate of the drive transistor T and its first electrode is Vdata+Vth−Pvdd so that the drive current generated by the drive transistor T is Id=K*(Vdata−Pvdd)2, where K is a coefficient related to the size and material of the drive transistor T. In this manner, the drive current generated by the drive transistor T is independent of its threshold voltage Vth, and the drive current is transmitted to the anode of the light-emitting element D through the second light emission control transistor M42 that is on so that the light-emitting element D emits light.
Further, with continued reference to
Accordingly, with continued reference to
The initialization transistor M5 may be an N-channel transistor or a P-channel transistor. If the initialization transistor M6 is an N-channel transistor, when the initialization control signal Se of the initialization control terminal SE is at a high level, the initialization transistor M5 is on, and when the initialization control signal Se of the initialization control terminal SE is at a low level, the initialization transistor M5 is off. If the initialization transistor M5 is a P-channel transistor, when the initialization control signal Se of the initialization control terminal SE is at a low level, the initialization transistor M5 is on, and when the initialization control signal Se of the initialization control terminal SE is at a high level, the initialization transistor M5 is off. The embodiments of the present disclosure do not specifically limit the type of the initialization transistor M5.
In an optional embodiment, the channel type of the initialization transistor M5 may be the same as the channel type of the data write transistor M2. At this point, since the data write transistor M2 controls the writing of the data signal Vdata before the light-emitting element D emits light, the initialization transistor M5 also initializes the anode of the light-emitting element D before the light-emitting element 20 emits light. In this manner, the fourth scan terminal S4 can be reused as the initialization control terminal SE so that the initialization transistor M5 and the data write transistor M2 can be on or off simultaneously.
In other optional embodiments, the channel type of the initialization transistor M5 may be the same as the channel type of the second reset transistor M12, and at this point, the second scan terminal S2 may be reused as the initialization control terminal SE so that the initialization transistor M5 and the second reset transistor M12 can be on or off simultaneously.
It is to be understood that the type of each transistor in the pixel circuit P and the corresponding drive processes have been illustrated through examples. In the embodiments of the present disclosure, when the type of each transistor in the pixel circuit P changes, the drive processes may be similar to the drive processes described above by changing the signal received by the gate of each transistor. The details are not repeated here.
In an optional embodiment,
The first scan terminals S1 of at least part of pixel circuits P in the same row are electrically connected to the same first scan line 141, that is, the first scan terminals S1 of part or all of the pixel circuits P in the same row are electrically connected to the same first scan line 141. Accordingly, the third scan terminals S3 of at least part of pixel circuits P in the same row are electrically connected to the same third scan line 143, that is, the third scan terminals S3 of part or all of the pixel circuits P in the same row are electrically connected to the same third scan line 143. For ease of description, unless otherwise specified, the technical solutions in the embodiments of the present disclosure are illustrated through the example in which all of the pixel circuits P in the same row are electrically connected to the same first scan line 141 and the same third scan line 143, respectively.
As shown in
Specifically, when the first scan line 141 and the third scan line 143 electrically connected to the same pixel circuit P are electrically connected to adjacent two first scan units 111, the first scan circuit 110 providing the first scan signal s1 for the pixel circuit P may be reused as the scan circuit providing the third scan signal s3 for the pixel circuit P, thereby reducing the number of scan circuits set in the non-display area NA, reducing the space occupied by the scan circuits in the non-display area NA and achieving the narrow bezel of the display panel 100. Further, the first stage of first scan unit 111 is electrically connected to N first scan lines 141 so that N rows of pixel circuits P electrically connected to the N first scan lines 141 share the same first scan unit 111. The last stage of first scan unit 111 is electrically connected to N third scan lines 143 so that N rows of pixel circuits P electrically connected to the N third scan lines 143 share the same first scan unit 111. Each stage of first scan unit 111 between the first stage of first scan unit 111 and the last stage of first scan unit 111 is electrically connected to N first scan lines 141 and N third scan lines 143, respectively so that N rows of pixel circuits P electrically connected to the N first scan lines 141 and N rows of pixel circuits P electrically connected to the N third scan lines 143 share the same first scan unit 111. Therefore, the number of first scan units set in the first scan circuit 110 can be reduced, and the size occupied by the first scan circuit 110 can be further reduced.
Further, since for the first scan line 141 and the third scan line 143 electrically connected to the same pixel circuit P, the first scan line 141 is electrically connected to the first scan unit 111 at the previous stage, the third scan line 143 is electrically connected to the first scan unit 111 at the subsequent stage and the first scan signal s1 outputted by each stage of first scan unit 111 is sequentially shifted, the time when the first reset transistor M11 starts to be turned on is before the time when the first compensation transistor M31 starts to be turned on. In this manner, at least part of the duration in which the gate of the drive transistor T is reset is before the duration in which the data signal Vdata is provided for the gate of the drive transistor T so that the data signal Vdata can be written after the gate of the drive transistor T is reset, thereby ensuring the accurate writing of the data signal Vdata to the gate of the drive transistor T.
In an optional embodiment,
The gate of the drive transistor T of each pixel circuit P in the first row can be reset only when the first reset transistor M11 and the second reset transistor M12 are simultaneously on, for example, only when the first scan signal s11 and the second scan signal s21 provided for each pixel circuit P in the first row are both effective pulses. The data signal Vdata can be transmitted to the gate of the drive transistor T of each pixel circuit P in the first row only when the data write transistor M2 and the first compensation transistor M13 are simultaneously on, for example, only when the third scan signal s31 and the fourth scan signal s41 provided for each pixel circuit P in the first row are both effective pulse. Therefore, in each pixel circuit P electrically connected to the same first scan unit 111, the end time (t5 and t5′) of the first one effective pulse of the second scan signal s2 is set before the start time (t7 and t7′) of the effective pulse of the fourth scan signal s4. For example, in the pixel circuit P in the first row and the pixel circuit P in the second row that both are electrically connected to the first stage of first scan unit 111, the end time of the first one effective pulse of the second scan signal s21 received by each pixel circuit P in the first row is t5, and the end time of the first one effective pulse of the second scan signal s22 received by each pixel circuit P in the second row is t5′. The start time of the effective pulse of the fourth scan signal s41 received by each pixel circuit P in the first row is t7, and the start time of the effective pulse of the fourth scan signal s41 received by each pixel circuit P in the second row is t7′. At this point, both t5 and t5′ are before t7 and t7′. In this manner, after the gate of the drive transistor T is reset at least once, the drive transistor T can be in the on state in the write phase of the data signal Vdata, ensuring that the data signal Vdata can be written to the gate of the drive transistor T in each pixel circuit P.
In an optional embodiment, with continued reference to
Specifically, the first reset transistor M11 is in the on state within the duration in which the first scan signal s1 is an effective pulse. At this point, the state of the second reset transistor M12 is controlled by the second scan signal s2, and then the transmission path of the reset signal Vref of the reset signal terminal VREF to the first node N1 can be controlled. Since the second scan signal s2 includes at least two effective pulses within the duration in which the first scan signal s1 is an effective pulse, the gate of the drive transistor T is reset at least twice after the end time t6 of the effective pulse of the first scan signal s1 so that the gate potential of the drive transistor T is sufficient to support the subsequent writing process of the data signal Vdata. In this manner, when the start time (t7 and t7′) of the effective pulse of the fourth scan signal s4 is set after the end time t6 of the effective pulse of the first scan signal s1, the data write transistor M2 is controlled to be on after the gate of the drive transistor T is reset at least twice, and the display cycle enters the write phase. Therefore, the data signal Vdata can be accurately written to the gate of the drive transistor T in the write phase so that the drive transistor T generates an accurate drive current according to the gate of the drive transistor T in the light emission phase to accurately drive the light-emitting element D to emit light.
It is to be understood that illustratively, pixel circuits P in different rows are electrically connected to different second scan lines 142, respectively, and different second scan lines 142 are electrically connected to different second scan units 121 so that the drive transistors of the pixel circuits P in different rows are reset at different times. In the embodiments of the present disclosure, the connection mode between the second scan lines 142 and the second scan units 121 is not limited thereto.
Optionally,
Each stage of second scan unit 121 is electrically connected to adjacent N second scan lines 142, that is, when the pixel circuits P in the same row share one second scan line 142, each stage of second scan unit 121 provides the second scan signal for the adjacent N rows of pixel circuits P so that the second reset transistors M12 in the N rows of pixel circuits P are simultaneously on or off. The effective pulse of the second scan signal s2 outputted by each second scan unit 121 is sequentially shifted, and the shift amount of the second scan signal s2 is greater than or equal to the width of the effective pulse of the second scan signal. For example, the end time of the effective pulse of the second scan signal s21 outputted by the first stage of second scan unit 121 is after the start time of the effective pulse of the second scan signal s22 outputted by the second stage of second scan unit 121 so that the effective pulses of the second scan signals s22 outputted by these two stages of second scan units 121 are not overlapped each other. In this manner, the second scan terminals s2 of the adjacent N rows of pixel circuits P receive the same second scan signal s2 so that the adjacent N rows of pixel circuits P can be reset simultaneously, thereby shortening the reset duration of each pixel circuit P in the display panel 100, relatively prolonging the light emission duration of the light-emitting element D and improving the display effect of the display panel 100. Further, since the reset signal Vref provided for each row of pixel circuits P is usually the same, even if N rows of pixel circuits P are reset simultaneously, the reset accuracy of each pixel circuit P will not be affected.
Accordingly, each stage of third scan unit 131 is electrically connected to a respective one fourth scan line 144. For example, each stage of third scan unit 131 is electrically connected to one fourth scan line 144. When each pixel circuit P in the same row shares one fourth scan line 144, each stage of third scan unit 131 provides the third scan signal for each pixel circuit P in the same row, and different stages of third scan units 131 provide the third scan signal to pixel circuits P in different rows. For example, the first stage of third scan unit 131 provides the fourth scan signal s41 for the data write transistors M2 of the pixel circuits P in the first row, and the second stage of third scan unit 131 provides the fourth scan signal S42 to the data write transistors M2 of the pixel circuits P in the second row. The effective pulse of the fourth scan signal s4 outputted by each third scan unit 131 is sequentially shifted, and the shift amount of the effective pulse of the fourth scan signal s4 is greater than or equal to the width of the effective pulse of the fourth scan signal s4. For example, the end time of the effective pulse of the fourth scan signal s41 outputted by the first stage of third scan unit 131 is before the start time of the fourth scan signal s42 outputted by the second stage of third scan unit 131 so that the data signal is written to pixel circuits P in different rows at different times to prevent crosstalk between data signals written to the pixel circuits P in different rows due to the fact that the data signal is simultaneously written to the pixel circuits P in different rows, thereby improving the accuracy of the data signals written to the pixel circuits P.
In an optional embodiment, with continued reference to
Specifically, since each stage of second scan unit 121 is electrically connected to N second scan lines 142, the gates of the drive transistors T of N rows of pixel circuits P electrically connected to the N second scan lines 142 can be reset simultaneously. After the drive transistors T of N rows of pixel circuits P are reset, the data signal Vdata needs to be provided for the pixel circuits P in each row, respectively. At this point, the data signal Vdata needs to be controlled to be written to the pixel circuits P in each row at different times. Therefore, when the width t20 of the effective pulse of the second scan signal s2 is set to be greater than or equal to N times the width t30 of the effective pulse of the fourth scan signal s4, the data signal Vdata can be written to N rows of pixel circuits P within the duration of one effective pulse of the second scan signal s2, thereby shortening the writing duration of the data signal Vdata and ensuring that the data signal Vdata can be accurately written to pixel circuits P in each row. Further, when the duration of the effective pulse of the second scan signal s2 is set not to be overlapped with the duration of the effective pulse of the fourth scan signal s4 in the same pixel circuit P, the reset phase and the write phase of the same pixel circuit P can be performed at different times to prevent the writing of the data signal Vdata from affecting the reset of the gate of the drive transistor T and prevent the reset signal Vref from affecting the writing of the data signal Vdata, thereby improving the accuracy of the reset of the gate of the drive transistor T and ensuring that the data signal Vdata can be accurately written to the gate of the drive transistor T.
In an optional embodiment,
It is to be understood that the bias adjustment transistor M6 may be an N-channel transistor or a P-channel transistor. If the bias adjustment transistor M6 is an N-channel transistor, when the fifth scan signal s5 of the fifth scan terminal S5 is at a high level, the bias adjustment transistor M6 is on, and when the fifth scan signal s5 is at a low level, the bias adjustment transistor M6 is off. At this point, the duration in which the fifth scan signal s5 is at a high level is the duration of the effective pulse of the fifth scan signal s5. If the bias adjustment transistor M6 is a P-channel transistor, when the fifth scan signal s5 is at a low level, the bias adjustment transistor M6 is on, and when the fifth scan signal s5 is at a high level, the bias adjustment transistor M6 is off. At this point, the duration in which the fifth scan signal s5 is at a low level is the duration of the effective pulse of the fifth scan signal s5.
When the drive transistor T is in the on state, a certain potential difference exists between the gate and the first electrode of the drive transistor T. In this manner, the drive transistor T is in a bias state, the I-V curve of the drive transistor is shifted, the threshold voltage of the drive transistor T is drifted, and the drive current cannot be accurately provided for the light-emitting element D, affecting the display effect. When the bias adjustment transistor M6 is set in the pixel circuit P, when the bias adjustment transistor M6 is on, the bias adjustment signal Vpark of the bias adjustment terminal DVH can be written to the first electrode of the drive transistor T through the bias adjustment transistor M6 that is on. In this manner, the first electrode potential of the drive transistor T is consistent with the bias adjustment signal Vpark, the potential difference between the gate and the first electrode of the drive transistor T is improved, the bias adjustment of the drive transistor T is achieved, and the shift of the I-V curve of the drive transistor T is balanced, and the threshold voltage drift of the drive transistor T is improved, thereby ensuring the display uniformity of the display panel.
For example, the following is described using an example in which the bias adjustment transistor M6 is a P-channel transistor.
In another optional embodiment, with reference to
In yet another embodiment, with reference to
It is to be understood that the duration in which the bias adjustment transistor M6 is on is illustrated above, and the embodiments of the present disclosure do not specifically limit the duration in which the bias adjustment transistor M6 is on as long as the bias adjustment of the drive transistor T can be achieved.
It is to be noted that in
Optionally,
Specifically, within the durations (t21 and t22) in which the second scan signal s2 is an effective pulse, the reset signal Vref can be written to the first node N1 to reset the drive transistor T so that the data signal written to the gate of the drive transistor T in the previous drive cycle can be cleared and the drive transistor T can be in the on state. When the duration t51 of the first effective pulse of the fifth scan signal s5 is set between the duration (t21 and t22) of the effective pulse of adjacent two second scan signals s2, after the gate of the drive transistor T is reset at least once, the bias adjustment is performed on the drive transistor T so that the bias adjustment signal Vpark can be transmitted to the first electrode of the drive transistor T through the bias adjustment transistor M6 and then to the second electrode of the drive transistor T through the drive transistor T, thereby keeping the first electrode potential of the drive transistor T consistent with the second electrode potential of the drive transistor T. Further, in the same pixel circuit P, the duration t51 of the first effective pulse of the fifth scan signal s5 is set to be overlapped with the duration t30′ of the effective pulse of the third scan signal s3, and the bias transistor M6 and the first compensation transistor M31 are simultaneously on within the overlapping duration so that the bias adjustment signal Vpark is transmitted to the gate of the drive transistor T through the bias adjustment transistor M6, the drive transistor T and the first compensation transistor M31 sequentially, thereby keeping the potentials of the first electrode, the second electrode and the gate of the drive transistor T all consistent with each other, balancing the I-V curve shift of the drive transistor T, improving the threshold drift of the drive transistor T and further improving the display uniformity of the display panel.
In an optional embodiment, with continued reference to
It is to be understood that with continued reference to
Optionally,
With continued reference to
Optionally, with continued reference to
For example,
In this manner, when the second scan terminals S2 of the adjacent N rows of pixel circuits P are set to electrically connected to the same second scan unit 121 and the fifth scan terminals S5 of the adjacent N rows of pixel circuits P are set to electrically connected to the same second scan unit 121, the number of the second scan units 121 set in the non-display area NA of the display panel 100 can be reduced, thereby simplifying the circuit structure of the non-display area NA of the display panel 100, reducing the size of the non-display area NA and achieving the narrow bezel of the display panel 100.
It is to be understood that illustratively, each second scan unit 121 is electrically connected to two second scan lines 142 and/or two fifth scan lines 145, respectively, that is, N is equal to 2. In the embodiments of the present disclosure, the value of N may be set according to requirements, and the embodiments of the present disclosure do not specifically limit the value of N.
In an optional embodiment,
It is to be understood that illustratively, each drive cycle of the pixel circuit P includes two bias adjustment phases for bias adjustment of the drive transistor T. In the embodiments of the present disclosure, the bias adjustment of the drive transistor T may also be achieved in other manners.
Optionally,
The effective pulse of the third scan signal s3 can control the first compensation transistor M31 to be on so that the first compensation transistor M31 is kept in the on state within the duration t30′ of the effective pulse of the third scan signal s3, and the effective pulse of the fourth scan signal s4 can control the data write transistor M2 to be on. In this manner, within the overlapping duration (t41 and t42) of the effective pulses of the third scan signal s3 and the fourth scan signal s4, the data write transistor M2 and the first compensation transistor M31 are simultaneously in the on state so that the data signal Vdata of the DATA signal terminal DATA can be transmitted to the gate of the drive transistor T, and in the transmission process of the data signal Vdata, the data signal Vdata passes through the first electrode and the second electrode of the drive transistor T sequentially and then reaches the gate of the drive transistor T so that the potentials of the first electrode, the second electrode and the gate of the drive transistor T can be kept consistent. Further, since the duration t30′ of the effective pulse of the third scan signal s3 is overlapped with the durations (t41 and t42) of at least two effective pulses of the fourth scan signal s4, for example, the duration t30′ of the effective pulse of the third scan signal s3 is overlapped with the durations (t41 and t42) of the two effective pulses of the fourth scan signal s4, within the first one overlapping duration between the third scan signal s3 and the fourth scan signal s4, the data signal Vdata is transmitted to the gate of the drive transistor T through the data write transistor M2, the drive transistor T and the first compensation transistor M31 sequentially so that the potentials of the first electrode, the second electrode and the gate of the drive transistor T are kept consistent, thereby achieving the bias adjustment of the drive transistor T, balancing the I-V curve shift of the drive transistor T and improving the threshold drift of the drive transistor T; within the next effective pulse overlapping duration between the third scan signal s3 and the fourth scan signal s4, due to the bias adjustment effect on the drive transistor T within the previous effective pulse overlapping duration, that drive transistor T approaches to the non-bias state, and at this point, the data signal Vdata is written to the gate of the drive transistor T again to ensure the accurate writing of the data signal Vdata so that the light-emitting element D can be driven to accurately emit light when the drive transistor T provides a drive current for the light-emitting element D according to the gate potential of the drive transistor T, thereby improving the display uniformity of the display panel.
It is to be noted that illustratively, the duration of the effective pulse of the third scan signal s3 is overlapped with durations of two effective pulses of the fourth scan signal s4. In the embodiments of the present disclosure, the duration of the effective pulse of the third scan signal s3 may also be overlapped with durations of more than two (for example, three, four or five) effective pulses of the fourth scan signal s4 in the same pixel circuit, and the embodiments of the present disclosure do not specifically limit the number of the preceding effective pulses of the fourth scan signal s4 as long as the core invention point of the embodiments of the present disclosure can be achieved. For ease of description, unless otherwise specified, the technical solutions in the embodiments of the present disclosure are illustrated through the example in which the duration of the effective pulse of the third scan signal is overlapped with durations of two effective pulses of the fourth scan signal in the same pixel circuit.
Optionally, with continued reference to
The setting that durations of part of the effective pulses of the fourth scan signal s4 are between durations of adjacent two effective pulses of the second scan signal s2 may be understood as follows: durations of part of the effective pulses of the fourth scan signal s4 are between durations of adjacent two effective pulses of the second scan signal s2 and durations of part of the effective pulses of the fourth scan signal s4 are not between durations of adjacent two effective pulses of the second scan signal s2. In an optional embodiment, durations of part of the effective pulses of the fourth scan signal s4 may also be after the durations of the effective pulses of the second scan signal s2 or the duration of the effective pulse of the first scan signal s1.
For example, the following is described using an example in which in each drive cycle of the pixel circuit P, the second scan signal s2 and the fourth scan signal s4 each have two effective pulses, the duration (t21 and t22) of each effective pulse of the second scan signal s2 is overlapped with the duration t10 of the effective pulse of the first scan signal s1, and the duration (t41 and t42) of each effective pulse of the fourth scan signal s4 is overlapped with the duration t30′ of the effective pulse of the third scan signal s3. At this point, the duration t41 of the first one effective pulse of the fourth scan signal s4 is between the durations t21 and t22 of the two effective pulses of the second scan signal s2. The gate of the drive transistor T may be reset within the duration t21 of the first one effective pulse of the second scan signal s2 so that the drive transistor T is on to ensure that the data signal Vdata is transmitted to the first electrode, the second electrode and the gate of the drive transistor T sequentially within the duration t41 of the first one effective pulse of the fourth scan signal s4 and keep the potentials of the first electrode, the second electrode and the gate of the drive transistor T consistent, thereby achieving the bias adjustment of the drive transistor T. After the duration t41 of the first one effective pulse of the fourth scan signal s4, within the duration t22 of the second one effective pulse of the second scan signal s2, the gate of the drive transistor T can be reset again so that the gate potential of the drive transistor T is cleared to ensure that the data signal Vdata can be accurately transmitted to the gate of the drive transistor T within the duration t42 of the second one effective pulse of the fourth scan signal s4 and enable the drive transistor T to accurately drive the light-emitting element D to emit light according to the gate potential of the drive transistor T in the subsequent light emission phase t40.
Optionally,
Each stage of first scan unit 111 is electrically connected to adjacent N first scan lines 141, where N is a positive integer greater than or equal to 2. In this manner, the number of the first scan units 111 can be reduced, thereby achieving the narrow bezel of the display panel 100. Each stage of first scan unit 111 is used for providing the first scan signal s1 for each first scan line 141. The effective pulse of the first scan signal s1 outputted by each stage of first scan unit 111 is sequentially shifted, and the shift amount of the effective pulse of the first scan signal s1 is less than the width of the effective pulse of the first scan signal s1. In this manner, the scan duration in which the first scan circuit 110 scans each pixel circuit P can be shortened while the progressive scanning of each pixel circuit P can be achieved.
In an optional embodiment, the display area AA of the display panel 100 may further include a plurality of third scan lines 143, and the third scan terminals S3 of at least part of pixel circuits P in the same row are electrically connected to the same third scan line 143. The first scan unit 111 may also be electrically connected to adjacent N third scan lines 143, and the first scan terminal S1 and the third scan terminal S3 of the same pixel circuit P are electrically connected to adjacent two stages of first scan units 111 respectively so that the first scan unit 111 can also provide the third scan signal s3 for each pixel circuit P. At this point, the first scan circuit 110 which provides the first scan signal s1 for the pixel circuit P can be reused as the scan circuit which provides the third scan signal s3 for the pixel circuit P, thereby reducing the number of scan circuits set in the non-display area NA and achieving the narrow bezel of the display panel 100.
With continued reference to
For example,
The following is described using an example of the drive progress of pixel circuits P in the first and second rows. Within the overlapping duration t211 between the effective pulse of the first scan signal s11 outputted by the first stage of first scan unit 111 and the first one effective pulse of the second scan signal s21 outputted by the first stage of second scan unit 121, the first reset transistor M11 and the second reset transistor M12 of each pixel circuit P in the first row are simultaneously on so that the drive transistor T of each pixel circuit P in the first row can be reset. Within the overlapping duration t212 between the effective pulse of the first scan signal s11 outputted by the first stage of first scan unit 111 and the first one effective pulse of the second scan signal s22 outputted by the second stage of second scan unit 121, the first reset transistor M11 and the second reset transistor M12 of each pixel circuit P in the second row are simultaneously on so that the drive transistor T of each pixel circuit P in the second row can be reset. Within the overlapping duration t411 between the effective pulse of the third scan signal s31 outputted by the second stage of first scan unit 111 and the first one effective pulse of the fourth scan signal s41 outputted by the third stage of second scan unit 121, the data write transistor M2 and the first reset compensation transistor M31 of each pixel circuit P in the first row are simultaneously on so that the data signal Vdata can be provided for the first electrode, the second electrode and the gate of the drive transistor T of each pixel circuit P in the first row to achieve the bias adjustment of the drive transistor T. Within the overlapping duration t412 between the effective pulse of the third scan signal s31 outputted by the second stage of first scan unit 111 and the first one effective pulse of the fourth scan signal s42 outputted by the fourth stage of second scan unit 121, the data write transistor M2 and the first reset compensation transistor M31 of each pixel circuit P in the second row are simultaneously on so that the data signal Vdata can be provided for the first electrode, the second electrode and the gate of the drive transistor T of each pixel circuit P in the second row to achieve the bias adjustment of the drive transistor T. Within the overlapping duration t221 between the effective pulse of the first scan signal s11 outputted by the first stage of first scan unit 111 and the second one effective pulse of the second scan signal s21 outputted by the first stage of second scan unit 121, the first reset transistor M11 and the second reset transistor M12 of each pixel circuit P in the first row are on again so that the drive transistor T of each pixel circuit P in the first row can be reset again. Within the overlapping duration t222 between the effective pulse of the first scan signal s11 outputted by the first stage of first scan unit 111 and the second one effective pulse of the second scan signal s22 outputted by the second stage of second scan unit 121, the first reset transistor M11 and the second reset transistor M12 of each pixel circuit P in the second row are on again so that the drive transistor T of each pixel circuit P in the second row can be reset again. Within the overlapping duration t421 between the effective pulse of the third scan signal s31 outputted by the second stage of first scan unit 111 and the second one effective pulse of the fourth scan signal s41 outputted by the third stage of second scan unit 121, the data write transistor M2 and the first reset compensation transistor M31 of each pixel circuit P in the first row are on again so that the data signal Vdata corresponding to each pixel circuit P in the first row can be accurately written to the gate of the drive transistor T of each pixel circuit P. Within the overlapping duration t422 between the effective pulse of the third scan signal s31 outputted by the second stage of first scan unit 111 and the second one effective pulse of the fourth scan signal s42 outputted by the fourth stage of second scan unit 121, the data write transistor M2 and the first reset compensation transistor M31 of each pixel circuit P in the second row are on again so that the data signal Vdata corresponding to each pixel circuit P in the second row can be accurately written to the gate of the drive transistor T of each pixel circuit P. After each pixel circuit in the first and second rows is reset twice and the data signal Vdata is written to each pixel circuit in the first and second rows twice, the light emission phases t40 of the pixel circuits P in the two rows can simultaneously start, and the light-emitting elements D of the pixel circuits P in the two rows are driven to emit light.
In this manner, the reset phase and the write phase of each row of pixel circuits P can be performed at different times without affecting each other, thereby achieving the accurate writing of the data signal to each pixel circuit P, reducing the number of scan circuits and scan units set in the display panel 100 and achieving the narrow bezel of the display panel 100.
Optionally,
Since the second compensation transistor M32 is electrically connected between the first compensation transistor M31 and the gate of the drive transistor T, the signal at the third node N3 can be transmitted to the gate of the drive transistor T only when the second compensation transistor M32 and the first compensation transistor M31 are simultaneously in the on state. In this manner, in the writ phase of the data signal Vdata, the data write transistor M2, the first compensation transistor M31 and the second compensation transistor M32 can be controlled to be simultaneously on so that the data signal Vdata of the DATA signal terminal DATA can be transmitted to the gate of the drive transistor T through the data write transistor M2, the drive transistor T, the first compensation transistor M31 and the second compensation transistor M32 that are all on.
In an optional embodiment,
It is to be understood that the setting that the second compensation transistor M32 is electrically connected between the drive transistor T and the first compensation transistor M31 may be: the first electrode of the first compensation transistor M31 is electrically connected to the second electrode of the drive transistor T at the third node N3, the second electrode of the first compensation transistor M31 is electrically connected to the first electrode of the second compensation transistor M32, and the second electrode of the second compensation transistor M32 is electrically connected to the gate of the drive transistor T. In this manner, the first compensation transistor M31 and the second compensation transistor M32 can be connected in series.
In other optional embodiments, as shown in
It is to be noted that the connection manners shown in
It is to be understood that the channel types of the first compensation transistor M31 and the second compensation transistor M32 may be the same or different. When the channel types of the first compensation transistor M31 and the second compensation transistor M32 are the same, for example, the first compensation transistor M31 and the second compensation transistor M32 are both N-channel transistors or both P-channel transistors. When the channel type of the first compensation transistor M31 is different from the channel type of the second compensation transistor M32, the first compensation transistor M31 is an N-channel transistor and the second compensation transistor M32 is a P-channel transistor, or the first compensation transistor M31 is a P-channel transistor and the second compensation transistor M32 is an N-channel transistor.
For example, the following is described using an example in which the first compensation transistor M31 is an N-channel transistor and the second compensation transistor M32 is a P-channel transistor. When the third scan signal s3 is at a high level and the sixth scan signal s6 is at a low level, the first compensation transistor M31 and the second compensation transistor M32 are simultaneously on. Conversely, when the third scan signal s3 is at a low level, the first compensation transistor M31 is off, and when the sixth scan signal s6 is at a high level, the second compensation transistor M32 is off. Therefore, the duration in which the third scan signal s3 is at a high level is the duration of the effective pulse of the third scan signal, and the duration in which the sixth scan signal s6 is at a low level is the duration of the effective pulse of the sixth scan signal s6.
In an optional embodiment, with reference to
Specifically, when the fourth scan terminal S4 is reused as the sixth scan terminal S6, the fourth scan signal s4 provided for the fourth scan terminal S4 can control the data write transistor M2 and the second compensation transistor M32 to be on or off simultaneously to provide a path for writing the data signal Vdata when the data write transistor M2 and the second compensation transistor M32 are simultaneously on. Therefore, when the fourth scan terminal S4 is set to be reused as the sixth scan terminal S6, the number of scan terminals set in the pixel circuit P can be reduced, the structure of the pixel circuit P can be simplified, and the size occupied by the pixel circuit P and its corresponding scan lines in the display area can be reduced, thereby improving the resolution of the display panel. Further, when the fourth scan terminal S4 is set to be reused as the sixth scan terminal S6, the data write transistor M2 and the second compensation transistor M32 in the pixel circuit P can be controlled without the need of providing the fourth scan signal s4 and the sixth scan signal s6 for the pixel circuit P respectively, thereby reducing the number of scan signals provided for the pixel circuit P, reducing the number of scan circuits set in the non-display area and achieving the narrow bezel of the display panel.
In an optional embodiment,
For example,
It is to be understood that illustratively, the bias adjustment phase t50 is before the light emission phase t40 and after the write phase t42 of the last data signal Vdata. The embodiments of the present disclosure do not limit the specific duration of the bias adjustment phase t50 without affecting the core invention point of the embodiments of the present disclosure.
Based on the same inventive concept, an embodiment of the present disclosure further provides a display device. The display device includes the display panel provided in the embodiments of the present disclosure. Therefore, the display device has the technical features of the display panel provided in the embodiments of the present disclosure and the drive method thereof and can achieve the beneficial effects of the display panel provided in the embodiments of the present disclosure. For similarities between the display device and the display panel, reference may be made to the description of the display panel provided in the embodiments of the present disclosure, and the details are not repeated here.
For example,
It is to be understood that various forms of the working processes of the pixel circuit shown above may be used with phases re-ordered, added, or removed. For example, the phases in the working processes of the pixel circuit described in the present disclosure may be performed in parallel, sequentially or in different orders, as long as the desirable results of the technical solutions of the present disclosure can be achieved, and no limitation is imposed herein.
The preceding embodiments do not limit the scope of the present disclosure. It is to be understood by those skilled in the art that various modifications, combinations, sub-combinations, and substitutions may be performed according to design requirements and other factors. Any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present disclosure are within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310099990.8 | Feb 2023 | CN | national |
