Patent Application
20230031812
The present application is related to the field of display technology, and specifically, to a display panel and a display device.
Gate driver on array (GOA) technology is a technology that directly forms gate driver circuits on array substrates to replace driver chips made of external silicon chips. A GOA circuit is formed on a substrate around a display region, which simplifies manufacturing processes of a display panel and eliminates a bonding process in a direction of horizontal scan lines. This increases production capacity, reduces product costs, and improves integration of the display panel to make it more suitable for making narrow border or borderless products to satisfy a visual pursuit of modern people.
Currently, large-sized, high-resolution, and super-narrow border (SNB) designs of display screens have become a development trend. Moreover, requirements for designing narrow borders of spliced display screens are even more inevitable. Technology of GOA produced in a display region (GOA in AA) is increasingly favored.
However, with resolutions become higher and sizes of pixels become smaller, a layout space of the GOA becomes larger. Designing the GOA in the AA region leads to a decrease in an aperture ratio and a serious lack of transmittance. Therefore, a problem of increasing the transmittance needs to be solved to achieve the narrow border.
The present application provides a display panel and a display device, which can increase transmittance of a display panel by reducing a total number of signal transmission lines and increasing an aperture ratio of the display panel.
In a first aspect, the display panel provided by the present application includes a plurality of rows of pixel units. Every two rows of pixel units in the plurality of rows of the pixel units compose a pixel unit group. Each of the pixel unit group includes a first row of pixel units and a second row of pixel units, which are adjacently disposed.
The display panel further includes a first gate driver on array (GOA) circuit unit disposed between the first row of pixel units and the second row of pixel units and a second GOA circuit unit disposed between the first GOA circuit unit and the second row of pixel units. The first GOA circuit unit is electrically connected to the first row of pixel units. The second GOA circuit unit is electrically connected to the second row of pixel units.
The first GOA circuit unit and the second GOA circuit unit share at least one signal transmission line. Each of the signal transmission line is respectively electrically connected to the first GOA circuit unit and the second GOA circuit unit.
In the display panel provided by the present application, the at least one signal transmission line includes at least one of a first low-frequency clock signal transmission line or a second low-frequency clock signal transmission line.
In the display panel provided by the present application, the at least one signal transmission line further includes a reset signal transmission line.
In the display panel provided by the present application, the at least one signal transmission line further includes a power signal transmission line.
In the display panel provided by the present application, the at least one signal transmission line is disposed between the first GOA circuit unit and the second GOA circuit unit. The first GOA circuit unit is electrically connected to the at least one signal transmission line in one-to-one correspondence through at least one first bridge line. The second GOA circuit unit is electrically connected to the at least one signal transmission line in one-to-one correspondence through at least one second bridge line.
In the display panel provided by the present application, the first GOA circuit unit includes two first sub-GOA circuit units disposed in parallel;
the second GOA circuit unit includes two second sub-GOA circuit units disposed in parallel; the two second sub-GOA circuit units one-to-one correspond to the two first sub-GOA circuit units; and
the first sub-GOA circuit unit and the second sub-GOA circuit unit arranged in a same column share the at least one signal transmission line.
In the display panel provided by the present application, the display panel further includes a GOA bus unit. The GOA bus unit is disposed at a periphery of the plurality of rows of pixel units.
The GOA bus unit includes at least one signal transmission bus extending in a column direction.
The at least one signal transmission line is electrically connected to the at least one signal transmission bus in one-to-one correspondence.
In the display panel provided by the present application, the at least one signal transmission bus includes at least one of a first low-frequency clock signal transmission bus, a second low-frequency clock signal transmission bus, a reset signal transmission bus, or a power signal transmission bus.
In the display panel provided by the present application, the display panel further includes a display region and a frame region at a periphery of the display region. The GOA bus unit is disposed in the frame region. The plurality of rows of pixel units, the first GOA circuit unit, and the second GOA circuit unit are disposed in the display region.
In the display panel provided by the present application, the display panel further includes:
a first gate line disposed between the first row of pixel units and the first GOA circuit unit and corresponding to the first row of pixel units, wherein the first GOA circuit unit is electrically connected to the first row of pixel units through the first gate line; and
a second gate line disposed between the second row of pixel units and the second GOA circuit unit and corresponding to the second row of pixel units, wherein the second GOA circuit unit is electrically connected to the second row of pixel units through the second gate line.
In the display panel provided by the present application, each of the pixel units includes any one of a red pixel unit, a green pixel unit, or a blue pixel unit.
In a second aspect, the present application further provides the display device including the display panel and a circuit board. The display panel includes a plurality of rows of pixel units. Every two rows of pixel units in the plurality of rows of the pixel units compose a pixel unit group. Each of the pixel unit group includes a first row of pixel units and a second row of pixel units, which are adjacently disposed.
The display panel further includes a first gate driver on array (GOA) circuit unit disposed between the first row of pixel units and the second row of pixel units and a second GOA circuit unit disposed between the first GOA circuit unit and the second row of pixel units. The first GOA circuit unit is electrically connected to the first row of pixel units. The second GOA circuit unit is electrically connected to the second row of pixel units.
The first GOA circuit unit and the second GOA circuit unit share at least one signal transmission line. Each of the signal transmission line is respectively electrically connected to the first GOA circuit unit and the second GOA circuit unit.
The circuit board is electrically connected to the first GOA circuit unit and the second GOA circuit unit.
In the display device provided by the present application, the at least one signal transmission line includes at least one of a first low-frequency clock signal transmission line or a second low-frequency clock signal transmission line.
In the display device provided by the present application, the at least one signal transmission line further includes a reset signal transmission line.
In the display device provided by the present application, the at least one signal transmission line further includes a power signal transmission line.
In the display device provided by the present application, the at least one signal transmission line is disposed between the first GOA circuit unit and the second GOA circuit unit. The first GOA circuit unit is electrically connected to the at least one signal transmission line in one-to-one correspondence through at least one first bridge line. The second GOA circuit unit is electrically connected to the at least one signal transmission line in one-to-one correspondence through at least one second bridge line.
In the display device provided by the present application, the first GOA circuit unit includes two first sub-GOA circuit units disposed in parallel.
The second GOA circuit unit includes two second sub-GOA circuit units disposed in parallel. The two second sub-GOA circuit units one-to-one correspond to the two first sub-GOA circuit units.
The first sub-GOA circuit unit and the second sub-GOA circuit unit arranged in a same column share the at least one signal transmission line.
In the display device provided by the present application, the display panel further includes a GOA bus unit. The GOA bus unit is disposed at a periphery of the plurality of rows of pixel units.
The GOA bus unit includes at least one signal transmission bus extending in a column direction.
The at least one signal transmission line is electrically connected to the at least one signal transmission bus in one-to-one correspondence.
In the display device provided by the present application, the at least one signal transmission bus includes at least one of a first low-frequency clock signal transmission bus, a second low-frequency clock signal transmission bus, a reset signal transmission bus, or a power signal transmission bus.
In the display device provided by the present application, the display panel further includes:
a first gate line disposed between the first row of pixel units and the first GOA circuit unit and corresponding to the first row of pixel units, wherein the first GOA circuit unit is electrically connected to the first row of pixel units through the first gate line; and
a second gate line disposed between the second row of pixel units and the second GOA circuit unit and corresponding to the second row of pixel units, wherein the second GOA circuit unit is electrically connected to the second row of pixel units through the second gate line.
Compared with the prior art, the display panel and the display device provided by the present application dispose two stages of the GOA circuit units (the first GOA circuit unit and the second GOA circuit unit) between two adjacent rows of the pixel units (the first row of pixel units and the second row of pixel units). The two stages of the GOA circuit units respectively provide gate signals to the two rows of the pixel units, and they share at least one signal transmission line, so as to use every signal transmission line to transmit a same signal to the two stages of the GOA circuit units. This reduces a total number of the signal transmission lines, thereby reducing an area occupied by the signal transmission lines in the display region, and the saved area can be used to increase an aperture ratio of the pixel units, thereby increasing transmittance of the display panel.
The following describes specific embodiments of the present application in detail with reference to the accompanying drawings, which will make technical solutions and other beneficial effects of the present application obvious.
To further explain the technical means and effects of the present application, the following refers to embodiments and drawings for detailed description. Obviously, the described embodiments are only for some embodiments of the present application, instead of all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall into a protection scope of the present application.
Generally, a gate driver on array (GOA) type display panel adopts a GOA circuit to drive the display panel for normal display. The GOA circuit includes a GOA bus unit and a GOA circuit unit. After drive signals such as a high-frequency clock signal CK, a low-frequency clock signal LC, a reset signal RST, and a power signal VSS are input from a circuit board to an array substrate of the display panel, they need to pass through the GOA bus unit to reach a gate drive circuit which is the GOA circuit unit, so as to realize precise control for every gate line (scan line).
For a GOA in AA type display panel, with a gradual increase of sizes and resolutions of the display panel, a resistance-capacitance (RC) load of the GOA bus unit becomes heavy, and it is not suitable to be place into a display region. The GOA bus unit is generally disposed in a border region of the display panel, and the GOA circuit unit in the GOA circuit is disposed in the display region, so as to achieve a narrow border. In an exemplary GOA in AA type display panel, a plurality of rows of pixel units and a plurality of stages of the GOA circuit unit are alternately arranged in sequence in the display region, so that each stage of the GOA circuit unit corresponds to a row of the pixel units. Because the GOA bus unit includes a plurality of signal transmission buses which are used to respectively transmit different driving signals, each stage of the GOA circuit unit needs to be electrically connected to each of the plurality of signal transmission buses through a plurality of signal transmission lines in one-to-one correspondence. For example, the GOA bus unit includes a first low-frequency clock signal (LC1) transmission bus, a second low-frequency clock signal (LC2) transmission bus, a reset signal (RST) transmission bus, a power signal (VSS) transmission bus, and a multi-stage high-frequency clock signal (CK) transmission bus. Then, a first low-frequency clock signal transmission line, a second low-frequency clock signal transmission line, a reset signal transmission line, a power signal transmission line, and a multi-stage high-frequency clock signal transmission line are disposed between each stage of the GOA circuit unit and the GOA bus unit.
With the increase in resolution of the display panel, a number of the GOA circuit units is also increased. Because every GOA circuit unit requires the plurality of signal transmission lines to achieve signal transmission, a number of the signal transmission lines is greatly increased, which means that an area of the display region occupied by the signal transmission lines is greatly increased. The increase in the number of the GOA circuit units reduces an aperture area of the pixel units in the display region, thereby affecting transmittance of the display panel. In order to solve the above problems, embodiments of the present application provide a display panel and a display device.
As shown in
Specifically, as shown in
Specifically, as shown in
Specifically, the display panel 1 further includes a display region 13 and a frame region 14 at a periphery of the display region 13. The GOA bus unit 11 is disposed in the frame region 14 of the display panel 1. The plurality of rows of pixel units 2, the first GOA circuit unit 6, and the second GOA circuit unit 7 are disposed in the display region 13. The signal transmission line is used to transmit the electrical signals on the signal transmission bus to the first GOA circuit unit 6 and the second GOA circuit unit 7. Each signal transmission line is partially located in the display region 13, and another portion is located in the frame region 14.
In an embodiment, as shown in
In an embodiment, as shown in
In an embodiment, as shown in
In an embodiment, as shown in
Specifically, as shown in
Specifically, each of the pixel units 2 includes any one of a red pixel unit (R), a green pixel unit (G), or a blue pixel unit (B).
In this embodiment, two stages of the GOA circuit units (the first GOA circuit unit 6 and the second GOA circuit unit 7) are disposed between two adjacent rows of the pixel units (the first row of pixel units 4 and the second row of pixel units 5). The two stages of the GOA circuit units respectively provide gate signals to the two rows of the pixel units, and they share at least one signal transmission line, so as to use every signal transmission line to transmit a same signal to the two stages of the GOA circuit units. This reduces a total number of the signal transmission lines, thereby reducing an area occupied by the signal transmission lines in the display region 13, and the saved area can be used to increase an aperture ratio of the pixel units 2, thereby increasing transmittance of the display panel 1.
As shown in
Specifically, in each pixel unit group 3, the first GOA circuit unit 6 includes two first sub-GOA circuit units 25 arranged side by side in a row direction; the second GOA circuit unit 7 includes two second sub-GOA circuit units 26 arranged in parallel in the row direction; the two second sub-GOA circuit units 26 one-to-one correspond to the two first sub-GOA circuit units 25; and the first sub-GOA circuit unit 25 and the second sub-GOA circuit unit 26 share the at least one signal transmission line. In other words, if the first sub-GOA circuit unit 25 and the second sub-GOA circuit unit 26 arranged in a same column are used as a group, two groups of the signal transmission lines are required to correspond to the two groups of the first sub-GOA circuit unit 25 and the second sub-GOA circuit unit 26. Each group of the signal transmission lines includes the at least one signal transmission line.
Specifically, the two first sub-GOA circuit units 25 are electrically connected to the first gate line 9 and input the gate signals to the first gate line 9. The two second sub-GOA circuit units 26 are electrically connected to the second gate line 10 and input the gate signals to the second gate line 10. By inputting the gate signals to the same gate line through the two sub-GOA circuit units at a same time, a driving capability can be enhanced, which is beneficial to increase response speed and a display effect of the display panel 1′.
Specifically, the frame region 14 of the display panel 1′ is respectively located on opposite two sides of the display region 13. The GOA bus unit 11 includes two sub-GOA bus units 27, which are respectively located in the frame region 14 on two sides of the display region 13. The first sub-GOA circuit unit 25 and the second sub-GOA circuit unit 26 arranged in the same column are electrically connected to the adjacent (closer in distance) sub-GOA bus unit 27.
Specifically, as shown in
In an embodiment, two groups of the signal transmission lines are same. This embodiment of the present application only uses a positional relationship between one group of the signal transmission lines and the corresponding first sub-GOA circuit unit 25 and second sub-GOA circuit unit 26 arranged in a same column for description. As shown in
Specifically, as shown in
In this embodiment, in an aspect, each gate line inputs the gate signals through two sub-GOA circuit units, which is a dual-drive structure, which can effectively enhance the driving capability. Therefore, transmission efficiency of the driving signals is effectively increased, and attenuation of the driving signals is reduced, thereby increasing the response speed and the display effect of the display panel 1. In another aspect, the display panel 1′ of the dual-drive structure requires more GOA circuit units, which means more signal transmission lines. In this embodiment, each group of first sub-GOA circuit units 25 and second sub-GOA circuit units 26 disposed in the same column share four signal transmission line. This reduces the total number of the signal transmission lines, thereby reducing the area occupied by the signal transmission lines in the display region 13, and the saved area can be used to increase the aperture ratio of the pixel units, thereby increasing the transmittance of the display panel 1.
As shown in
Specifically, the circuit board 31 is electrically connected to the first GOA circuit unit and the second GOA circuit unit through the GOA bus unit and is used to provide a driving signal to control the display panel 1′ to display normally.
In this embodiment, two stages of the GOA circuit units (the first GOA circuit unit and the second GOA circuit unit) are disposed between two adjacent rows of the pixel units (the first row of pixel units and the second row of pixel units). The two stages of the GOA circuit units respectively provide gate signals to the two rows of the pixel units, and they share at least one signal transmission line, so as to use every signal transmission line to transmit a same signal to the two stages of the GOA circuit units. This reduces a total number of the signal transmission lines, thereby reducing an area occupied by the signal transmission lines in the display region 13, and the saved area can be used to increase an aperture ratio of the pixel units, thereby increasing transmittance of the display device 30.
In the above embodiments, the descriptions of the various embodiments are different in emphases, for contents not described in detail, please refer to related description of other embodiments.
The display panel and the display device provided by embodiments of the present application are described in detail above, and the description of embodiments above is only for helping to understand technical solutions of the present application and its core idea. Understandably, for a person of ordinary skill in the art can make various modifications of the technical solutions of the embodiments of the present application above. However, it does not depart from the scope of the technical solutions of the embodiments of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202010285575.8 | Apr 2020 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2020/086010 | 4/22/2020 | WO |
