Patent Application
20240040832
The present application relates to the field of display technology, and in particular to a display panel and a display device.
With the development of display technology, in order to maximize an active area in a limited space, a narrow-frame display technique has been proposed.
Usually, as limited by a layout of a driving circuit in a frame area, and the flexible screen may also be limited by bending process, the frame size of the display screen cannot be further reduced. As a result, a technique that places part of the driving circuit in the active area in order to reduce the frame size has appeared on the market. However, this induces change of pixel circuits in the active area, which thereby affects the display stability of the screen.
In view of this, there is a need to provide a display panel and display device.
According to an aspect of the present application, a display panel is provided, including a substrate, a plurality of light-emitting units arranged in array alignment, a plurality of first pixel circuit units, and a plurality of second pixel circuit units. The substrate includes an active area and a frame area at least partially surrounding the active area. The plurality of light-emitting units are located in the active area. Each light-emitting unit includes a first electrode. The plurality of first pixel circuit units are arranged in array alignment and located in the active area. Each first pixel circuit unit includes a plurality of first pixel circuits. The plurality of first pixel circuits are arranged in array alignment, and at least one first pixel circuit is electrically connected to the first electrode of a corresponding light-emitting unit. The plurality of second pixel circuit units are located in the active area. Each second pixel circuit unit includes a plurality of second pixel circuits. The plurality of second pixel circuits are arranged in array alignment, and at least one second pixel circuit is electrically connected to the first electrode of a corresponding light-emitting unit. A first arrangement gap is defined between any two adjacent first pixel circuit units.
According to another aspect of the present application, a display device is provided, including the above-described display panel.
In the above-described display device, a plurality of first pixel circuits are arranged to form a regular layout of a plurality of first pixel circuit units, so that a distance between two adjacent first pixel circuits in each first pixel circuit unit decreases, and a distance between any two adjacent first pixel circuit units increases correspondingly. Thus, the increased distance can meet the requirement for placing other materials, thereby improving the display stability of the display panel.
In order to facilitate understanding of the present application, the present application will be described more thoroughly hereinafter with reference to the accompanying drawings. Embodiments of the present application are given in the accompanying drawings. However, the present application may be implemented in various different forms and is not limited to the embodiments described herein. The purpose of providing these embodiments is to provide a more thorough and complete understanding of the present application.
In the present application, a direction perpendicular to a display surface of a display panel is defined as a third direction, and two intersecting directions parallel to the display surface are defined as a first direction and a second direction. The third direction is also the thickness direction of the display panel and its substrate, and is also the direction from the substrate to the light-emitting unit.
In order to reduce the frame size, the driving circuit that is originally located in the frame area of the display panel can be partially located in an active area.
In the active area of the display panel, pixel circuits are electrically connected to light-emitting units to enable the light-emitting units to emit light. There is usually a one-to-one correspondence between the pixel circuits and the light-emitting units in the direction perpendicular to the display surface of the display panel, that is, the third direction. In order to place the driving circuit in the active area without affecting the size of the active area, the size of the pixel circuits can be reduced while the original size of the light-emitting units is maintained, so as to make room for placing the driving circuit under the area adjacent to the frame area, which can reduce the size of the frame area.
On this basis, it has been found through the inventors' study that although the space obtained by reducing the size of the pixel circuits in the active area can meet the requirements for placing the driving circuit in the active area, a distance between the corresponding two adjacent pixel circuits increases, which to some extent affects display stability. When all pixel circuits in the active area are distributed at equal intervals, although the distance between two adjacent pixel circuits increases, the increased distance is not enough for placing other materials or components, thereby failing to improve display stability.
Therefore, there is a need to provide a display panel and a display device, with improved display stability. Referring to
The plurality of light-emitting units 20 are arranged in array alignment and located in the active area AA. Each light-emitting unit 20 includes a first electrode 21. Further, each light-emitting unit 20 also includes a light-emitting element 22 and a second electrode 23. In embodiments of the present application, the first electrode 21 is an anode, and the second electrode 23 is a cathode. The light-emitting element 22 can at least include an organic light-emitting layer. In an embodiment, the plurality of light-emitting units 20 are arranged in rows along the first direction, and arranged in columns along the second direction. In an embodiment, the first direction is perpendicular to the second direction.
The plurality of first pixel circuit units 30 are arranged in array alignment and located in the active area AA. Each first pixel circuit unit 30 includes a plurality of first pixel circuits 31. The plurality of first pixel circuits 31 are in array alignment, arranged in rows along the first direction, and arranged in columns along the second direction. Each first pixel circuit 31 is electrically connected to a corresponding light-emitting unit 20 to enable the corresponding light-emitting unit 20 to emit light. Specifically, at least one first pixel circuit 31 is electrically connected to the first electrode 21 of the corresponding light-emitting unit 20. The plurality of second pixel circuit units 40 are located in the active area AA. Each second pixel circuit unit 40 includes a plurality of second pixel circuits 41. The plurality of second pixel circuits 41 are in array alignment, arranged in rows along the first direction, and arranged in columns along the second direction. At least one second pixel circuit 41 is configured to be electrically connected to a corresponding light-emitting unit 20 to enable the corresponding light-emitting unit 20 to emit light. Specifically, at least one second pixel circuit 41 is electrically connected to the first electrode 21 of the corresponding light-emitting unit 20. In some embodiments, each light-emitting unit 20 in the plurality of light-emitting units 20 in the display panel 100 is configured to be electrically connected to one of the first pixel circuit 31 and the second pixel circuit 41. In some embodiments, the first pixel circuit units 30 and the second pixel circuits 41 are arranged side by side on the same plane perpendicular to the third direction, and the plurality of light-emitting units 20 as a whole are located above the first pixel circuit units 30 and the second pixel circuits 41.
Specifically, each of the first pixel circuits 31 and the second pixel circuits 41 includes a thin-film transistor. The thin-film transistor has a current output terminal, and the current output terminal is electrically connected to the first electrode 21 of the light-emitting unit 20. More specifically, the thin-film transistor in each of the first pixel circuits 31 and the second pixel circuits 41 includes a source electrode 311, a drain electrode 312, a gate electrode 313, and a semiconductor layer 314. The source electrode 311 and the drain electrode 312 are spaced from each other, and are respectively electrically connected to the semiconductor layer 314. The gate electrode 312 is opposite to the semiconductor layer 314 in the third direction and electrically insulated from the semiconductor layer 314. In some embodiments, the thin-film transistor is a P-type transistor, and the first electrode 21 of the light-emitting unit 20 is connected to the drain electrode 312. In other embodiments, the thin-film transistor is an N-type transistor, and the first electrode 21 of the light-emitting unit 20 is connected to the source electrode 311. Referring also to
panel 100 further includes a plurality of gate lines 50 and a plurality of data lines 60 disposed on the substrate 10. Each gate line 50 extends along the first direction, and the plurality of gate lines 50 are arranged at intervals along the second direction. Each data line 60 extends along the second direction, and the plurality of data lines 60 are arranged at intervals along the first direction. The plurality of gate lines 50 intersect with the plurality of data lines 60 to define a plurality of pixel areas. Both the first direction and the second direction are parallel to the substrate 10. In an embodiment, the first direction is perpendicular to the second direction. Referring to
In embodiments of the present application, the plurality of first pixel circuit units are arranged in array alignment, and a first arrangement gap CCI is defined between any two adjacent rows of first pixel circuit units 30 and/or between any two adjacent columns of first pixel circuit units 30. In an embodiment, the plurality of first pixel circuit units 30 are arranged in rows along the first direction, and arranged in columns along the second direction.
In embodiments of the present application, in the same first pixel circuit unit 30, the distance between the orthographic projections of any two adjacent first pixel circuits 31 on the substrate 10 is smaller than the size of the first arrangement gap CC1. In this way, it is beneficial to make the display panel 100 have a relatively large size of the first arrangement gap CC1.
It can be understood that when two pixel circuits are adjacent in the first direction, the size of the arrangement gap between the two pixel circuits is the size of the arrangement gap in the first direction. When two pixel circuits are adjacent in the second direction, the size of the arrangement gap between the two pixel circuits is the size of the arrangement gap in the second direction. That is to say, the pixel circuits in the display panel 100 are not all distributed at equal intervals, and the distance between two adjacent first pixel circuits 31 located in different first pixel circuit units 30 is greater than the distance between two adjacent first pixel circuits 31 located in the same first pixel circuit unit 30.
In some embodiments, all first pixel circuits 31 located in the same first pixel circuit unit 30 are distributed at equal intervals.
In the present application, the plurality of first pixel circuits 31 are arranged to form a regular layout of the plurality of first pixel circuit units 30, so that the distance between two adjacent first pixel circuits 31 in each first pixel circuit unit 30 decreases, while the distance between any two adjacent rows and/or columns of first pixel circuit units 30 (namely the first arrangement gap CC1) correspondingly increases. This increased distance can be used to place other materials or components, such as a virtual pixel circuit, etc., thereby improving display stability of the display panel 100.
In embodiments of the present application, the orthographic projection of each first pixel circuit unit 30 on the substrate 10 forms a first projection area BB1, the orthographic projections of the first electrodes 21 of the plurality of light-emitting units 20 corresponding to the first pixel circuit unit 30 on the substrate 10 form second projection areas, and the second projection areas are located in the first projection area BB1. The first projection area BB1 includes the area of the orthographic projection of the gap between two adjacent first pixel circuits 31 on the substrate 10.
The orthographic projection of each second pixel circuit unit 40 on the substrate 10 forms a third projection area BB2, the orthographic projections of the first electrodes 21 of the plurality of light-emitting units 20 corresponding to the second pixel circuit unit 40 on the substrate 10 form fourth projection areas, and the fourth projection areas do not overlap or only partially overlap with the third projection area BB2. The third projection area BB2 includes the area of the orthographic projection of the gap between two adjacent second pixel circuits 41 on the substrate 10.
When the size of the pixel circuits is reduced, the connection wires between the pixel circuits and the corresponding light-emitting units are changed. When a large number of connection wires are changed, the circuit making process may become complicated and may affect the display stability.
In embodiments of the present application, since the second projection areas are located in the first projection area BB1, the positions of the first pixel circuits 31 in the first pixel circuit unit 30 relative to the corresponding light-emitting units 20 after the size of the first pixel circuits 31 is reduced can be kept substantially the same as those before the size of the first pixel circuits 31 is reduced, and thus there is no need to change the connection wires. In some embodiments, the position of the first pixel circuit 31 can be substantially in correspondence, in the third direction, with the position of the light-emitting unit 20 electrically connected thereto. For example, the orthographic projection of the first pixel circuit 31 on the substrate 10 at least partially overlaps with the orthographic projection of the corresponding light-emitting unit 20 on substrate 10. In contrast, the fourth projection areas do not overlap or only partially overlap with the third projection area BB2, so that the positions of the second pixel circuits 41 in the second pixel circuit unit 40 relative to the corresponding light-emitting units 20 after the size of the second pixel circuits 41 is reduced are not kept substantially the same as those before the size of the second pixel circuits 41 is reduced , and thus the connection wires have to be changed to meet the requirement for reducing the size of the pixel circuits to achieve a narrow frame. In some embodiments, the positions of at least part of the second pixel circuits 41 are not in correspondence, in the third direction, with the positions of the light-emitting units 20 electrically connected thereto. For example, the orthographic projections of at least part of the plurality of second pixel circuits 41 on the substrate 10 do not overlap at all with the orthographic projections of the corresponding light-emitting units 20 on substrate 10.
In the display panel 100 of embodiments of the present application, the pixel circuits are divided into the first pixel circuits 31 forming the first pixel circuit units 30 and the second pixel circuits 41 forming the second pixel circuit units 40, and the pixel circuits that are in need to change the connection wires are limited to the second pixel circuit units 40, which reduces the number of connection wires to be changed, and thus simplifies the wire making process, thereby improving display stability.
As the size of each first pixel circuit 31 is reduced, the distance between two adjacent first pixel circuits 31 has to be reduced in order to concentrate multiple first pixel circuits 31 into one first pixel circuit unit 30. Therefore, while two adjacent first pixel circuits 31 of reduced size are brought closer to each other, there will be a slight deviation in position correspondence in the third direction between at least part or all of the first pixel circuits 31 and the corresponding light-emitting units 20, but the slight deviation is within a controllable range.
Referring to
In an embodiment, the active area AA includes a first active area AA1 and a second active area AA2 located between the first active area AA1 and the frame area FA. The plurality of first pixel circuit units 30 are located in the first active area AA1, and the plurality of second pixel circuit units 40 are located in the second active area AA2. In order to reduce the frame size, a driving circuit 55 is partially disposed in the active area, such as the second active area AA2, and is located at the edge of the active area AA. The position of the second pixel circuit unit 40 is more adjacent to the frame area FA than the position of the first pixel circuit unit 30 is, so that the change of the relative position of the pixel circuits and the light-emitting units 20 caused by this can be limited to the second pixel circuit unit 40 as much as possible, and then the first placement spaces CC1 can be formed regularly between the first pixel circuit units 30.
Further, the display panel 100 includes a driving circuit 55. The driving circuit 55 is disposed on the substrate 10, and at least part of the driving circuit 55 is disposed in the active area AA, such as the second active area AA2. The driving circuit 55 can be electrically connected to the first pixel circuits 31 and the second pixel circuits 41 to provide driving signals. Specifically, the driving circuit 55 includes a switch circuit, a gate electrode driving circuit, and a light-emitting control circuit.
The switch circuit is electrically connected to the first pixel circuits 31 and the second pixel circuits 41 through the data lines 60. Specifically, each data line 60 is electrically connected to all first pixel circuits 31 or all second pixel circuits 41 in a corresponding same column.
The gate electrode driving circuit is electrically connected to the first pixel circuits 31 and the second pixel circuits 41 through scanning lines in the gate lines 50, and is configured to provide gate electrode driving signals. Specifically, each gate line 50 is electrically connected to all first pixel circuits 31 or all second pixel circuits 41 in a corresponding same row.
The light-emitting control circuit can also be electrically connected to the first pixel circuits 31 and the second pixel circuits 41 through light-emitting control lines in the gate lines 50 to provide light-emitting signals. Specifically, a light-emitting control circuit and a gate electrode driving circuit are distributed along the second direction on opposite sides of a gate line 50.
The pixel circuits are configured to transmit data signals from the data lines 60 to the light-emitting units 20 in response to the gate electrode driving signals from the gate lines 50, so as to control light emission of each light-emitting unit 20, or to control brightness of each light-emitting unit 20.
In some embodiments, the orthographic projection of the driving circuit 55 located in the active area AA on the substrate 10 forms a fifth projection area. The fifth projection area is located on the side of the third projection area BB2 away from the first projection area BB1, and partially overlaps with the fourth projection areas. In this way, the driving circuit 55 can be confined under the light-emitting units 20 in the active area AA adjacent to the edge of the frame area FA, thereby reducing the size of the frame.
In some embodiments, the display panel 100 further includes a power line. The power line is electrically connected to at least one of the first pixel circuits 31, the second pixel circuits 41, or the light-emitting units 20 to provide voltage signals.
The power line of the present application can be arranged in the active area AA or the frame area FA. In some embodiments, the power line can include at least one of a first power line, a second power line, or a third power line. The first power line is configured to provide a low voltage signal (VDD), the second power line is configured to provide a high voltage signal (VSS), and the third power line is configured to provide a reference voltage signal (Vref). Specifically, the first power line VDD is electrically connected to the first pixel circuits 31 and the second pixel circuits 41 in the active area AA to apply voltage to the first electrodes 21 of the light-emitting units 20. The second power line VSS is electrically connected to the second electrodes 23 of the light-emitting units 20 in the frame area FA to apply voltage to the second electrodes 23. The third power line Vref is electrically connected to the first pixel circuits 31 and the second pixel circuits 41 in the active area AA.
Referring to
In this way, by having the first virtual pixel circuits 68 connected to the power line, the transmission lines are increased to compensate for a significant voltage drop (IR Drop) generated on the relatively long power line, so that voltages on the first pixel circuits 31 and the second pixel circuits 41 are consistent, and thus the driving currents provided to the respective light-emitting units 20 are consistent, so that the luminous brightness of the display panel 100 is uniform, thereby improving display uniformity of the display panel 100. In addition, the first virtual pixel circuits 68 can be entirely disposed in the first arrangement gaps CC1, which can simplify their connection with the power line.
As shown in
Referring to
Specifically, the first virtual sub-pixel circuit 681 can include a non-metal layer 6811, a first metal layer 6812, and a second metal layer 6813 stacked along the third direction.
More specifically, the display panel 100 can include an array layer 70, a passivation layer 76, a planarization layer 78, and a light-emitting element layer 80 sequentially stacked on the substrate 10 along the third direction. The array layer 70 includes an active layer 71, a gate electrode layer 72, and a source and drain electrode layer 73. The array layer 70 further includes a first insulating layer 74 disposed between the active layer 71 and the gate electrode layer 72, and includes a second insulating layer 75 disposed between the gate electrode layer 72 and the source and drain electrode layer 73. The light-emitting element layer 80 includes a first electrode layer 81, a light-emitting layer 82, and a second electrode layer 83. The source and drain electrode layer 73 forms the source electrodes 311 and the drain electrodes 312 of the thin-film transistors of the first pixel circuits 31 and the second pixel circuits 41. The active layer 71 forms the semiconductor layers 314 of the thin-film transistors of the first pixel circuits 31 and the second pixel circuits 41. The gate electrode layer 72 forms the gate electrodes 313 of the thin-film transistors of the first pixel circuits 31 and the second pixel circuits 41. The first electrode layer 81 forms the first electrodes 21 of the light-emitting units 20. The light-emitting layer 82 forms the light-emitting elements 22 of the light-emitting units 20. The second electrode layer 83 forms the second electrodes 23 of the light-emitting units 20.
The non-metal layer 6811 is located in the same layer as the active layer 71, and the pattern and shape of the non-metal layer 6811 are respectively the same as those of the first pixel circuit 31 or the second pixel circuit 41 in the active layer 71. In some embodiments, the non-metal layer 6811 includes a virtual semiconductor layer, which is located in the same layer and has the same pattern and shape respectively as the semiconductor layers 314 of the thin-film transistors of the first pixel circuits 31 and the second pixel circuits 41. The first metal layer 6812 is located in the same layer as the gate electrode layer 72, and the pattern and shape of the first metal layer 6812 are respectively the same as those of the first pixel circuits 31 and the second pixel circuits 41 in the gate electrode layer 72. In some embodiments, the first metal layer 6812 includes a virtual gate electrode, which is located in the same layer and has the same pattern and shape as the gate electrodes 313 of the thin-film transistors of the first pixel circuits 31 and the second pixel circuits 41. The second metal layer 6813 is located in the same layer as the source and drain electrode layer 73, and the pattern and shape of the second metal layer 6813 are respectively the same as those of the first pixel circuits 31 and the second pixel circuits 41 in the source and drain electrode layer 73. In some embodiments, the second metal layer 6813 can include a virtual source electrode and a virtual drain electrode, which are respectively located in the same layer and have the same pattern and shape as the source electrodes 311 and the drain electrodes 312 of the thin-film transistors of the first pixel circuits 31 and the second pixel circuits 41.
In some embodiments, the non-metal layer 6811, the first metal layer 6812, and the second metal layer 6813 are connected to each other along the third direction. Specifically, they can be connected by through holes formed in the first insulating layer 74 and the second insulating layer 75. In other embodiments, alternatively, the non-metal layer 6811 can be connected to the first metal layer 6812, or the first metal layer 6812 can be connected to the second metal layer 6813, or the non-metal layer 6811 can be connected to the second metal layer 6813.
In some embodiments, the first virtual sub-pixel circuit 681 can include only one or any combination of the non-metal layer 6811, the first metal layer 6812, or the second metal layer 6813, which is not limited herein.
Since the first virtual pixel circuit 68 does not need to serve the function of driving the light-emitting unit 20, the first virtual pixel circuit 681 is not electrically connected to any light-emitting unit 20. In some embodiments, separation can be made to the non-metal layer 6811, separating it into two independent and mutually insulated parts. For example, the virtual semiconductor layer can be separated into two independent and mutually insulated parts. The two independent and mutually insulated parts can be respectively connected to the virtual source electrode and the virtual drain electrode of the second metal layer 6813 through the through holes in the first insulating layer 74 and the second insulating layer 75.
In other embodiments, at least one of the virtual source electrode and the virtual drain electrode of the second metal layer 6813 can be disconnected from the non-metal layer 6811, specifically, by canceling the corresponding through hole in the first insulating layer 74 or the second insulating layer 75.
As shown in
gate lines 50, and the second metal lead wires 683 extend in the same direction as the data line Since the first metal lead wires 682 and second metal lead wires 683 are to be electrically connected to the power line, rather than the signal sources of the gate lines 50 and data lines in order to distinguish the two, the first metal lead wires 682 and the second metal lead wires 683 can be located in layers different from the layers of the gate lines 50 and the data lines 60.
In some embodiments, the first metal lead wire 682 includes one selected from the first metal layers 6812 and the second metal layers 6813, and the second metal lead wire 683 includes the other one selected from the first metal layers 6812 and the second metal layers 6813. Specifically, each first metal lead wire 682 can be formed by sequentially connecting one of the plurality of first metal layers 6812 and the plurality of second metal layers 6813 aligned along the first direction in a row, and each second metal lead wire 683 can be formed by sequentially connecting the other one of the plurality of second metal layers 6813 or the plurality of first metal layers 6812 aligned along the second direction in a column.
In some embodiments, the first arrangement gap CC1 of the display panel 100 includes a first arrangement sub-gap located between two first pixel circuit units 30 adjacent along the first direction, and a second arrangement sub-gap located between two first pixel circuit units 30 adjacent along the second direction. The size of the first arrangement sub-gap is different from the size of the second arrangement sub-gap. The difference in the gaps can meet wiring requirements of different sizes, quantities, or shapes.
In some embodiments, a second arrangement gap CC2 is defined between adjacent first pixel circuit unit 30 and second pixel circuit unit 40. By having the second arrangement gap CC2, the gap between the first pixel circuit unit 30 and the second pixel circuit unit 40 can also be used to place other materials, thereby improving display stability of the display panel 100. In an embodiment, the size of the first arrangement gap CC1 is equal to the size of the second arrangement gap CC2. In this way, the size of the gap between the pixel circuit units in the entire display panel can be kept consistent, which is beneficial to optimize the display effect.
Referring to
In an embodiment, the plurality of second pixel circuit units 40 are located on one side of the plurality of first pixel circuit units 30 in the first direction, and the plurality of second pixel circuit units 40 are arranged in a column along the second direction. A third arrangement gap CC3 is defined between any two second pixel circuit units 40 adjacent in the second direction. All the first arrangement gaps CC1 between any two adjacent columns of first pixel circuit units 30 are in communication with each other, and are in communication with the corresponding third arrangement gap CC3. Further, the second virtual pixel circuit is disposed in the third arrangement gap CC3.
In some other embodiments, the plurality of second pixel circuit units 40 are located on one side of the plurality of first pixel circuit units 30 in the second direction, and the plurality of second pixel circuit units 40 are arranged in a row along the first direction. A fourth arrangement gap is defined between any two second pixel circuit units 40 adjacent in the first direction. All the first arrangement gaps CC1 between any two adjacent rows of first pixel circuit units 30 are in communication with each other, and are in communication with the corresponding fourth arrangement gap. Further, the second virtual pixel circuit is disposed in the fourth arrangement gap CC4.
In other embodiments, the arrangement of the plurality of second pixel circuit units can be a combination of the above two embodiments. The display panel 100 not only includes the second pixel circuit units 40 arranged in a column along the second direction, but also includes the second pixel circuit units 40 arranged in a row along the first direction, which is not limited herein. In this way, it can be avoided that the first arrangement gaps CC1, the third arrangement gaps CC3, and the fourth arrangement gaps are in complicated communications which make the first virtual pixel circuits 68 and the second virtual pixel circuits connected complicatedly, resulting in complicated wiring.
Of course, in other embodiments, the plurality of second pixel circuit units 40 can be arranged continuously, and the third arrangement gap CC3 or the fourth arrangement gap defined between two adjacent second pixel circuit units 40 can be canceled, which is not limited herein.
In the same second pixel circuit unit 40, the distance between the orthographic projections of any two adjacent second pixel circuits 41 on the substrate 10 is smaller than the size of the third arrangement gap CC3 or the fourth arrangement gap.
Furthermore, the first virtual pixel circuit 68 and the second virtual pixel circuit can be connected at the connecting location between the first arrangement gap CC1 and the third arrangement gap CC3 or the fourth arrangement gap. In this way, since the end of the power line is located in a binding area of the frame area FA, the wiring of the first virtual pixel circuit 68 can be avoided from being interfered by the gathered second pixel circuit unit 40, as the third arrangement gap CC3 or the fourth arrangement gap is formed between two adjacent second pixel circuit units 40, and the second virtual pixel circuit is electrically connected to the first virtual pixel circuit 68 at the connecting location between the third arrangement gap CC3 or the fourth arrangement gap and the first arrangement gap CC1. Therefore, the wiring of the second virtual pixel circuit can reach the frame area FA without the need of bypassing the gathered second pixel circuit unit 40, which is simplified.
In some embodiments, the second virtual pixel circuit includes a plurality of second virtual sub-pixel circuits connected to each other. The structure, form, film or layer arrangement, and connection relationship with other components of the second virtual sub-pixel circuit can all be the same with those of the first virtual pixel circuit and will not be repeated herein.
Based on the same inventive concept, an embodiment of the present application further provides a display device, including the above-described display panel 100.
Specifically, the display device can be applied to the fields such as mobile terminals, bionic electronics, electronic skins, wearable devices, vehicle-mounted devices, internet of things devices, and artificial intelligence devices. Specifically, the display terminal can be a digital device such as a mobile phone, a tablet, a handheld computer, an ipod, or a smart watch.
Not all possible combinations of the technical features in the above embodiments are described. However, in the case that there is no contradiction in the combination of these technical features, these combinations should be considered to be within the scope of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210108272.8 | Jan 2022 | CN | national |
This application is a continuation of international patent application No. PCT/CN2022/107403, filed on Jul. 22, 2022, which claims priority to Chinese Patent Application No. 202210108272.8, entitled “DISPLAY PANEL AND DISPLAY DEVICE” filed on Jan. 28, 2022. The contents of the above identified applications are hereby incorporated herein in their entireties by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2022/107403 | Jul 2022 | US |
| Child | 18486408 | US |
