Patent Application
20250140163
The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.
Currently, light-emitting diode (LED) display is widely used in the display of outdoor and central control large screen. The current application of LED is mainly for long-distance viewing, with relatively large pixel pitch and low pixels per inch (PPI).
It should be noted that the above information disclosed in the “BACKGROUND” section is intended only to enhance the understanding of the background of this disclosure, and therefore it may include information that does not constitute prior art known to those of ordinary skill in the art.
The purpose of the present disclosure is to overcome the deficiencies of the above prior art and to provide a display panel and a display device.
According to an aspect of the present disclosure, there is provided a display panel, including a plurality of pixel units distributed in an array along a row direction and a column direction, where the pixel unit includes: a pixel driver circuit configured to provide a driving current; a plurality of sub-pixels, where a first electrode of the sub-pixel is configured to be connected to the pixel driver circuit, a second electrode of the sub-pixel is connected to a second power supply terminal, and the sub-pixel is configured to emit light under an action of the driving current; and a switching circuit including a plurality of switching units arranged in correspondence with the plurality of sub-pixels, where the switching unit is connected in series between the pixel driver circuit and a corresponding sub-pixel, a control end of the switching unit is configured to receive a switching signal, a first end of the switching unit is connected to the pixel driver circuit, a second end of the switching unit is connected to a first electrode of the corresponding sub-pixel, and the switching unit is configured to conduct a communication path between the corresponding sub-pixel and the pixel driver circuit in response to the switching signal.
In an embodiment of the present disclosure, the display panel includes a base substrate; where in a same pixel unit, an orthographic projection of the pixel driver circuit on the base substrate is on a side, away from an orthographic projection of the second electrode of the sub-pixel on the base substrate, of an orthographic projection of the first electrode of the sub-pixel on the base substrate, and an orthographic projection of the switching unit on the base substrate is between an orthographic projection of the first electrode of the corresponding sub-pixel on the base substrate and an orthographic projection of the second electrode of the corresponding sub-pixel on the base substrate.
In an embodiment of the present disclosure, the display panel further includes a first driving circuit in a display area of the display panel, the first driving circuit being configured to output a gate control signal; where the pixel driver circuit is configured to transmit a data signal from a data signal terminal to a driving signal terminal in response to the gate control signal.
In an embodiment of the present disclosure, the first driving circuit includes a plurality of cascaded first shift register units, and the first shift register unit that provides the gate control signal to a nth row of pixel units is between the nth row of pixel units and a (n+1)th row of pixel units, n being a positive integer greater than 0.
In an embodiment of the present disclosure, the display panel further includes a switch driving circuit in the display area of the display panel, where the switch driving circuit is configured to output the switching signal.
In an embodiment of the present disclosure, the switch driving circuit includes a plurality of sub-switch driving circuits, one sub-switch driving circuit being configured to drive a column of switching units; and where the sub-switch driving circuit includes a plurality of cascaded third shift register units, and the third shift register unit that provides the switching signal to a nth row of switching circuits is in a gap between the nth row of pixel units and a (n+1)th row of pixel units, n being a positive integer greater than 0.
In an embodiment of the present disclosure, the pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel; the switching circuit includes a first switching unit, a second switching unit and a third switching unit, where the first switching unit is correspondingly connected to the first sub-pixel, the second switching unit is correspondingly connected to the second sub-pixel, and the third switching unit is correspondingly connected to the third sub-pixel; and the switch driving circuit includes a first sub-switch driving circuit, a second sub-switch driving circuit and a third sub-switch driving circuit, wherein the first sub-switch driving circuit is configured to output a first switching signal to the first switching unit, the second sub-switch driving circuit is configured to output a second switching signal to the second switching unit, and the third sub-switch driving circuit is configured to output a third switching signal to the third switching unit; where the first sub-switch driving circuit, the second sub-switch driving circuit and the third sub-switch driving circuit are configured to successively output the first switching signal, the second switching signal and the third switching signal row by row; and the first driving circuit is configured to output gate control signals respectively during a time when the first sub-switch driving circuit outputs the first switching signal, during a time when the second sub-switch driving circuit outputs the second switching signal, and during a time when the third sub-switch driving circuit outputs the third switching signal.
In an embodiment of the present disclosure, the display panel includes two switch driving circuits disposed separately along the row direction on two sides of the display area.
In an embodiment of the present disclosure, the display panel further includes: a first driving circuit, the first driving circuit being configured to output a gate control signal, wherein the pixel driver circuit is configured to transmit a data signal from a data signal terminal to a driving signal terminal in response to the gate control signal; and a driver integrated circuit configured to output switching signals to the plurality of switching units, respectively.
In an embodiment of the present disclosure, the first driving circuit is in a non-display area of the display panel.
In an embodiment of the present disclosure, the pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel. The switching circuit includes a first switching unit, a second switching unit and a third switching unit, where the first switching unit is correspondingly connected to the first sub-pixel, the second switching unit is correspondingly connected to the second sub-pixel, and the third switching unit is correspondingly connected to the third sub-pixel. In a frame of data, the driver integrated circuit is configured to successively output a first switching signal, a second switching signal and a third switching signal; during a time when the driver integrated circuit outputs the first switching signal, the first driving circuit is configured to sequentially output a first gate control signal to each pixel driver circuit, and the pixel driver circuit is configured to provide the driving current to the first sub-pixel in response to the first gate control signal; during a time when the driver integrated circuit outputs the second switching signal, the first driving circuit is configured to sequentially output a second gate control signal to each pixel driver circuit, and the pixel driver circuit is configured to provide the driving current to the second sub-pixel in response to the second gate control signal; and during a time when the driver integrated circuit outputs the third switching signal, the first driving circuit is configured to sequentially output a third gate control signal to each pixel driver circuit, and the pixel driver circuit is configured to provide the driving current to the third sub-pixel in response to the third gate control signal.
In an embodiment of the present disclosure, in the frame of data, the first switching signal, the second switching signal, and the third switching signal have a same duration.
In an embodiment of the present disclosure, the first driving circuit is configured to output the gate control signal in accordance with a first frequency and the driver integrated circuit is configured to output the switching signal in accordance with a second frequency, the first frequency being three times the second frequency.
In an embodiment of the present disclosure, the pixel driver circuit includes: a driver device connected to a first node, a second node and a third node, where the driver device is configured to provide, in response to a voltage signal from the first node, the driving current using a voltage difference between the second node and the third node; a first reset device connected to the first node, a first reset signal terminal and an initial signal terminal, where the first reset device is configured to transmit an initial signal from the initial signal terminal to the first node in response to a reset signal from the first reset signal terminal; a transmission device connected to the first node, a gate signal terminal and the second node, where the transmission device is configured to conduct a communication path between the first node and the second node in response to a signal from the gate signal terminal; a data writing device connected to a data signal terminal, the gate signal terminal and the third node, where the data writing device is configured to transmit a second data signal from the data signal terminal to the third node in response to the signal from the gate signal terminal; a second reset device connected to a fourth node, the initial signal terminal and the first reset signal terminal, where the second reset device is configured to transmit the initial signal from the initial signal terminal to the fourth node in response to the reset signal from the first reset signal terminal; a first light-emitting control device connected to the third node, an enable signal terminal and a first power supply terminal, where the first light-emitting control device is configured to conduct a communication path between the third node and the first power supply terminal in response to an enable signal from the enable signal terminal; a second light-emitting control device connected to the second node, the fourth node and an adjustment device, where the second light-emitting control device is configured to conduct a communication path between the fourth node and the second node in response to a signal from the adjustment device; a storage device connected to the first node and the first power supply terminal, where the storage device is configured to store the voltage signal written to the first node; and the adjustment device connected to the data signal terminal, a second reset signal terminal, the first reset signal terminal, the initial signal terminal and the enable signal terminal, wherein the adjustment device is configured to turn off the second light-emitting control device in response to a first data signal from the data signal terminal, or to turn on the second light-emitting control device in response to a second data signal from the data signal terminal.
In an embodiment of the present disclosure, the driver device includes: a driver transistor with a control end connected to the first node, a first end connected to the third node, and a second end connected to the second node; the first reset device includes: a first transistor with a control end connected to the first reset signal terminal, a first end connected to the first node, and a second end connected to the initial signal terminal; the transmission device includes: a second transistor with a control end connected to the gate signal terminal, a first end connected to the first node, and a second end connected to the second node; the data writing device includes: a fourth transistor with a control end connected to the gate signal terminal, a first end connected to the data signal terminal, and a second end connected to the third node; the second reset device includes: a seventh transistor with a control end connected to the first reset signal terminal, a first end connected to the initial signal terminal, and a second end connected to the fourth node; the first light-emitting control device includes: a fifth transistor with a control end connected to the enable signal terminal, a first end connected to the first power supply terminal, and a second end connected to the third node; the second light-emitting control device includes: a sixth transistor with a control end connected to a seventh node, a first end connected to the second node, and a second end connected to the fourth node; the storage device includes: a storage capacitor with a first electrode connected to the first power supply terminal, and a second electrode connected to the first node; and the adjustment device includes: an eighth transistor with a control end connected to the second reset signal terminal, a first end connected to the data signal terminal, and a second end connected to a fifth node, where the eighth transistor is configured to transmit the data signal from the data signal terminal to the fifth node in response to a reset signal from the second reset signal terminal; a ninth transistor with a control end connected to the fifth node, a first end connected to the enable signal terminal, and a second end connected to the seventh node, where the ninth transistor is configured to transmit the enable signal from the enable signal terminal to the seventh node in response to a voltage signal from the fifth node; a first capacitor connected to the fifth node and the initial signal terminal, where the first capacitor is configured to store the voltage signal written to the fifth node; a tenth transistor with a control end connected to the first reset signal terminal, a first end connected to the data signal terminal, and a second end connected to a sixth node, where the tenth transistor is configured to transmit the data signal from the data signal terminal to the sixth node in response to the reset signal from the first reset signal terminal; an eleventh transistor with a control end connected to the sixth node, a first end connected to a high-frequency signal terminal, and a second end connected to the seventh node, where the eleventh transistor is configured to transmit a signal from the high-frequency signal terminal to the seventh node in response to a voltage signal from the sixth node; and a second capacitor connected to the sixth node and the initial signal terminal, where the second capacitor is configured to store the voltage signal written to the sixth node.
In an embodiment of the present disclosure, the switching unit is a transistor.
In an embodiment of the present disclosure, the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the switching circuit includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; where a control end of the twelfth transistor is configured to receive a first switching signal, a first end of the twelfth transistor is connected to the fourth node, and a second end of the twelfth transistor is connected to a first electrode of the first sub-pixel; a control end of the thirteenth transistor is configured to receive a second switching signal, a first end of the thirteenth transistor is connected to the fourth node, and a second end of the thirteenth transistor is connected to a first electrode of the second sub-pixel; and a control end of the fourteenth transistor is configured to receive a third switching signal, a first end of the fourteenth transistor is connected to the fourth node, and a second end of the fourteenth transistor is connected to a first electrode of the third sub-pixel.
In an embodiment of the present disclosure, the display panel includes a base substrate; a first conductive layer on a side of the base substrate, the first conductive layer including: a third conductive portion configured to form a first electrode of the storage capacitor; an active layer on a side of the first conductive layer away from the base substrate, the active layer including: a first active portion, where an orthographic projection of the first active portion on the base substrate is between an orthographic projection of a first conductive portion on the base substrate and an orthographic projection of the third conductive portion on the base substrate, and the first active portion is configured to form a channel region of the first transistor; a first sub-active portion connected to a side of the first active portion and configured to form the first end of the first transistor; a second sub-active portion connected to an other side of the first active portion and configured to form the second end of the first transistor and the first end of the seventh transistor; a seventh active portion, where a side of the seventh active portion is connected to the second sub-active portion, and the seventh active portion is configured to form a channel region of the seventh transistor; a fourteenth sub-active portion connected to an other side of the seventh active portion and configured to form the second end of the seventh transistor; a third active portion, where an orthographic projection of the third active portion on the base substrate is on a side of the orthographic projection of the third conductive portion on the base substrate along the column direction, and the third active portion is configured to form a channel region of the driver transistor; a fifth sub-active portion connected to a side of the third active portion in the column direction and configured to form the first end of the driver transistor; a sixth sub-active portion connected to an other side of the third active portion and configured to form the second end of the driver transistor; a second active portion on a side of the third active portion along the row direction, the second active portion being configured to form a channel region of the second transistor; a third sub-active portion connected to a side of the second active portion close to the third active portion along the row direction, the third sub-active portion being configured to form the first end of the second transistor; a fourth sub-active portion connected to a side of the second active portion away from the third active portion, the fourth sub-active portion being configured to form the second end of the second transistor; a fourth active portion on a side of the third active portion away from the second active portion, the fourth active portion being configured to form a channel region of the fourth transistor; a seventh sub-active portion connected to a side of the fourth active portion away from the third active portion, the seventh sub-active portion being configured to form the first end of the fourth transistor; an eighth sub-active portion connected to a side of the fourth active portion close to the third active portion, the eighth sub-active portion being configured to form the second end of the fourth transistor; a fifth active portion, where an orthographic projection of the fifth active portion on the base substrate is between the orthographic projection of the third active portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate, and the fifth active portion is configured to form a channel region of the fifth transistor; a ninth sub-active portion connected to a side of the fifth active portion away from the third active portion, the ninth sub-active portion being configured to form the first end of the fifth transistor; a tenth sub-active portion connected to a side of the fifth active portion close to the third active portion, the tenth sub-active portion being configured to form the second end of the fifth transistor; a sixth active portion on a side of the fifth active portion along the row direction, the sixth active portion being configured to form a channel region of the sixth transistor; an eleventh sub-active portion connected to a side of the sixth active portion close to the third active portion, the eleventh sub-active portion being configured to form the first end of the sixth transistor; a twelfth sub-active portion connected to an other side of the sixth active portion, the twelfth sub-active portion being configured to form the second end of the sixth transistor; a second conductive layer on a side of the active layer away from the base substrate, the second conductive layer including: a third conductive block including a first component, a second component and a third component connected in sequence, where an orthographic projection of the first component on the base substrate partially overlaps with the orthographic projection of the third conductive portion on the base substrate, an orthographic projection of the third component on the base substrate covers the orthographic projection of the third active portion on the base substrate, and a portion of the third conductive portion is configured to form the second electrode of the storage capacitor and a portion of the third conductive portion is configured to form a top gate of the driver transistor; a gate signal line, where an orthographic projection of the gate signal line on the base substrate extends in the row direction, the orthographic projection of the gate signal line on the base substrate is on a side of the orthographic projection of the third component on the base substrate away from the orthographic projection of the first component on the base substrate, the orthographic projection of the gate signal line on the base substrate partially covers an orthographic projection of the second active portion on the base substrate, and partially covers an orthographic projection of the fourth active portion on the base substrate, and a portion of the gate signal line is configured to form a gate of the second transistor and a portion of the gate signal line is configured to form a gate of the fourth transistor; an enable signal line including a main body portion, a first sub-extension portion and a second sub-extension portion connected in sequence, where an orthographic projection of the main body portion on the base substrate is on a side of an orthographic projection of the third conductive block on the base substrate away from the orthographic projection of the gate signal line on the base substrate, an orthographic projection of the second sub-extension portion on the base substrate covers the orthographic projection of the fifth active portion on the base substrate, and a portion of the enable signal line is configured to form a gate of the fifth transistor; a sixth conductive block including a first sub-conductive block and a second sub-conductive block, where an orthographic projection of the first sub-conductive block on the base substrate extends in the column direction, an orthographic projection of the second sub-conductive block on the base substrate covers an orthographic projection of the sixth active portion on the base substrate, and a portion of the sixth conductive block is configured to form a gate of the sixth transistor; and a first reset signal line, where an orthographic projection of the first reset signal line on the base substrate extends in the row direction and is on a side of the orthographic projection of the third conductive block on the base substrate away from the orthographic projection of the third active portion on the base substrate, and the orthographic projection of the first reset signal line on the base substrate covers the orthographic projection of the first active portion on the base substrate and an orthographic projection of the seventh active portion on the base substrate, and a portion of the first reset signal line is configured to form a gate of the first transistor and a gate of the seventh transistor; and a third conductive layer on a side of the second conductive layer away from the base substrate, the third conductive layer including: a third transfer portion, where an end of the third transfer portion is connected to the third sub-active portion through a via hole, and an other end of the third transfer portion is connected to the third conductive block through a via hole; a fourth transfer portion connected to the fourth sub-active portion, the sixth sub-active portion, and the eleventh sub-active portion through via holes, respectively; a fifth transfer portion connected to the fifth sub-active portion, the eighth sub-active portion, and the tenth sub-active portion through via holes, respectively; a sixth transfer portion connected to the twelfth sub-active portion through a via hole; a seventeenth conductive block including a main conductive portion and a sub-conductive portion, where an orthographic projection of the main conductive portion on the base substrate is on the orthographic projection of the third conductive block on the base substrate, and where the seventeenth conductive block is connected to the third conductive portion and to the ninth sub-active portion through via holes, respectively, and a portion of the seventeenth conductive block is configured to form the first electrode of the storage capacitor and a portion of the seventeenth conductive block is configured to form the first end of the fifth transistor; and a data signal line, where an orthographic projection of the data signal line on the base substrate extends in the column direction, and the data line is connected to the seventh sub-active portion through a via hole.
In an embodiment of the present disclosure, the first conductive layer further includes: a first conductive portion configured to form a first electrode of the first capacitor; a second conductive portion configured to form a second electrode of the second capacitor; a fourth conductive portion on a side of the third conductive portion away from the first conductive portion, where an orthographic projection of the fourth conductive portion on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the fourth conductive portion is configured to form a bottom gate of the driver transistor; and a fifth conductive portion connected to a side of the fourth conductive portion, where the fifth conductive portion is connected to the third transfer portion through a via hole; the active layer further includes: an eighth active portion, where an orthographic projection of the eighth active portion on the base substrate is between an orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate, and the eighth active portion is configured to form a channel region of the eighth transistor; a fifteenth sub-active portion connected to a side of the eighth active portion and configured to form the first end of the eighth transistor; a sixteenth sub-active portion connected to an other side of the eighth active portion and configured to form the second end of the eighth transistor; a ninth active portion, where an orthographic projection of the ninth active portion on the base substrate is between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate, and the ninth active portion is configured to form a channel region of the ninth transistor; a seventeenth sub-active portion connected to a side of the ninth active portion and configured to form the first end of the ninth transistor; an eighteenth sub-active portion connected to an other side of the ninth active portion and configured to form the second end of the ninth transistor; a tenth active portion, where an orthographic projection of the tenth active portion on the base substrate is between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate, and the tenth active portion is configured to form a channel region of the tenth transistor; a nineteenth sub-active portion connected to a side of the tenth active portion and configured to form the first end of the tenth transistor; a twentieth sub-active portion connected to an other side of the tenth active portion and configured to form the second end of the tenth transistor; an eleventh active portion, where an orthographic projection of the eleventh active portion on the base substrate is between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate, and the eleventh active portion is configured to form a channel region of the eleventh transistor; a twenty-first sub-active portion connected to a side of the eleventh active portion and configured to form the first end of the eleventh transistor; and a twenty-second sub-active portion connected to an other side of the eleventh active portion and configured to form the second end of the eleventh transistor; the second conductive layer further includes: a first high-frequency signal line, where an orthographic projection of the first high-frequency signal line on the base substrate extends in the row direction and is on a side of the orthographic projection of the first conductive portion on the base substrate away from the orthographic projection of the third conductive portion on the base substrate; a third power line, where an orthographic projection of the third power line on the base substrate extends in the row direction and is between the orthographic projection of the first high-frequency signal line on the base substrate and the orthographic projection of the first conductive portion on the base substrate, and the third power line is configured to provide the second power supply terminal of the first sub-pixel; a second power line, where an orthographic projection of the second power line on the base substrate extends in the row direction and is between the orthographic projection of the third power line on the base substrate and the orthographic projection of the first conductive portion on the base substrate, and the second power line is configured to provide the second power supply terminal of the second sub-pixel and the second power supply terminal of the third sub-pixel; an initial signal line, where an orthographic projection of the initial signal line on the base substrate extends in the row direction and is between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate; a second reset signal line, where an orthographic projection of the second reset signal line on the base substrate extends in the row direction and is between the orthographic projection of the initial signal line on the base substrate and the orthographic projection of the third conductive block on the base substrate, the orthographic projection of the second reset signal line on the base substrate covers the orthographic projection of the eighth active portion on the base substrate, and a portion of the second reset signal line is configured to form a gate of the eighth transistor; a first power line, where an orthographic projection of the first power line on the base substrate extends in the row direction and is between the orthographic projection of the first reset signal line on the base substrate and the orthographic projection of the third conductive block on the base substrate, and the orthographic projection of the main body portion of the enable signal line on the base substrate is between the orthographic projection of the first power line on the base substrate and the orthographic projection of the third conductive portion on the base substrate; a first conductive block, where an orthographic projection of the first conductive block on the base substrate is on the orthographic projection of the first conductive portion on the base substrate, and the first conductive block is configured to form a second electrode of the first capacitor; a second conductive block, where an orthographic projection of the second conductive block on the base substrate is on the orthographic projection of the second conductive portion on the base substrate, and the second conductive block is configured to form a second electrode of the second capacitor; the third conductive block including the first component, the second component and the third component, where the orthographic projection of the first component on the base substrate is on the orthographic projection of the third conductive portion on the base substrate, and the first component is configured to form the second electrode of the storage capacitor; and where the orthographic projection of the third component on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the third component is configured to form a gate of the driver transistor; a fourth conductive block, where an orthographic projection of the fourth conductive block on the base substrate covers the orthographic projection of the ninth active portion on the base substrate, and a portion of the fourth conductive block is configured to form a gate of the ninth transistor; a sixth conductive block including a first sub-conductive block and a second sub-conductive block, where an orthographic projection of the first sub-conductive block on the base substrate extends in the column direction, an orthographic projection of the second sub-conductive block on the base substrate extends in the row direction, the orthographic projection of the second sub-conductive block on the base substrate covers the orthographic projection of the sixth active portion on the base substrate, and a portion of the sixth conductive block is configured to form a gate of the sixth transistor; a ninth conductive block, where an orthographic projection of the ninth conductive block on the base substrate overs the orthographic projection of the eleventh active portion on the base substrate, a portion of the ninth conductive block is configured to form a gate of the eleventh transistor, and the ninth conductive block is connected to an eleventh transfer portion and a twelfth transfer portion through via holes, respectively; and a tenth conductive block connected to the seventeenth sub-active portion through a via hole; and the third conductive layer further includes: a second high-frequency signal line, where an orthographic projection of the second high-frequency signal line on the base substrate extends in the column direction, and the second high-frequency signal line is connected to the first high-frequency signal line through a via hole; a data signal line, where an orthographic projection of the data signal line on the base substrate extends in the column direction, and the data signal line is connected to the seventh sub-active portion, the fifteenth sub-active portion, and the nineteenth sub-active portion through via holes; a first transfer portion connected to the first sub-active portion and the third conductive block through via holes, respectively; a second transfer portion connected to the second sub-active portion and the initial signal line through via holes, respectively; a seventh transfer portion connected to the first conductive block, the sixteenth sub-active portion, and the fourth conductive block through via holes, respectively; an eighth transfer portion connected to the seventeenth sub-active portion and the enable signal line through via holes, respectively; a ninth transfer portion connected to a fifth conductive block in the second conductive layer and the eighteenth sub-active portion and the twenty-second sub-active portion through via holes, respectively; a tenth transfer portion connected to the fifth conductive block and the sixth conductive block through via holes, respectively; an eleventh transfer portion connected to the twentieth sub-active portion and the ninth conductive block through via holes, respectively; a twelfth transfer portion connected to the ninth conductive block and the second conductive block through via holes, respectively; and a sixteenth transfer portion connected to the twenty-first sub-active portion and a seventh conductive block in the second conductive layer through via holes, respectively, where the seventh conductive block is further connected to the second high-frequency signal line through a via hole; where the orthographic projection of the first reset signal line on the base substrate further covers the orthographic projection of the tenth active section on the base substrate, and where a portion of the first reset signal line is configured to form a gate of the tenth transistor.
In an embodiment of the present disclosure, the active layer further includes: a twelfth active portion configured to form a channel region of the twelfth transistor; a twenty-third sub-active portion connected to a side of the twelfth active portion, where the twenty-third sub-active portion is configured to form the first end of the twelfth transistor, and the twenty-third sub-active portion is connected to the sixth transfer portion through a via hole; a twenty-fourth sub-active portion connected to an other side of the twelfth active portion and configured to form the second end of the twelfth transistor; a thirteenth active portion configured to form a channel region of the thirteenth transistor; a twenty-fifth sub-active portion connected to a side of the thirteenth active portion and configured to form the first end of the thirteenth transistor, where the twenty-fifth sub-active portion is connected to the sixth transfer portion through a via hole; a twenty-sixth sub-active portion connected to an other side of the thirteenth active portion and configured to form the second end of the thirteenth transistor; a fourteenth active portion configured to form a channel region of the fourteenth transistor; a twenty-seventh sub-active portion connected to a side of the fourteenth active portion and configured to form the first end of the fourteenth transistor, where the twenty-seventh sub-active portion is connected to the sixth transfer portion through a via hole; a twenty-eighth sub-active portion connected to an other end of the fourteenth active portion and configured to form the second end of the fourteenth transistor; the second conductive layer further includes: a twelfth conductive block, where an orthographic projection of the twelfth conductive block on the base substrate covers an orthographic projection of the twelfth active portion on the base substrate, and the twelfth conductive block is configured to form a gate of the twelfth transistor; a thirteenth conductive block, where an orthographic projection of the thirteenth conductive block on the base substrate covers an orthographic projection of the thirteenth active portion on the base substrate, and the thirteenth conductive block is configured to form a gate of the thirteenth transistor; and a fourteenth conductive block, where an orthographic projection of the fourteenth conductive block on the base substrate covers an orthographic projection of the fourteenth active portion on the base substrate, and the fourteenth conductive block is configured to form a gate of the fourteenth transistor; and the third conductive layer further includes: a thirteenth transfer portion connected to the twenty-fourth sub-active portion through a via hole; a fourteenth transfer portion connected to the twenty-sixth sub-active portion through a via hole; and a fifteenth transfer portion connected to the twenty-eighth sub-active portion through a via hole; and where the display panel further includes: a fourth conductive layer on a side of the third conductive layer away from the base substrate, the fourth conductive layer including: a twentieth conductive block configured to form the first electrode of the first sub-pixel, where the twentieth conductive block is connected to the thirteenth transfer portion through a via hole; a twenty-first conductive block configured to form the first electrode of the second sub-pixel, where the twenty-first conductive block is connected to the fourteenth transfer portion through a via hole; and a twenty-second conductive block configured to form the first electrode of the third sub-pixel, where the twenty-second conductive block is connected to the fifteenth transfer portion through a via hole.
According to a second aspect of the present disclosure, there is provided a display device including the display panel described in any one of embodiments of the present disclosure.
It should be understood that the above general description and the following detailed descriptions are exemplary and explanatory only and do not limit the present disclosure.
The accompanying drawings herein are incorporated into and form part of the specification, show embodiments that are consistent with the present disclosure, and are used in conjunction with the specification to explain the concepts of the present disclosure. It will be apparent that the accompanying drawings in the following description are only some of embodiments of the present disclosure, and that other drawings may be obtained from these drawings without creative effort by those of ordinary skill in the art.
Embodiments will now be described more fully with reference to the accompanying drawings. However, the embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; rather, the provision of these embodiments makes the present disclosure comprehensive and complete and conveys the concepts of the embodiments to those skilled in the art in a comprehensive manner. The same reference numerals in the drawings indicate the same or similar structures, and thus their detailed description will be omitted. In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.
The present disclosure provides a display panel that includes a plurality of sub-pixels and a pixel driver circuit P-Drive in a pixel unit, the plurality of sub-pixels being connected to the pixel driver via a switching circuit MSW arranged, such that the plurality of sub-pixels in the pixel unit multiplex a pixel driver circuit P-Drive via the switching circuit MSW. In addition, the connection between the pixel driver circuit P-Drive and the sub-pixel can be switched by each switching unit in the switching circuit MSW in response to a corresponding switching signal, and the pixel driver circuit P-Drive can provide a corresponding driving current to the connected sub-pixel in accordance with a set timing to realize a normal display of the display panel. In the present disclosure, a plurality of sub-pixels in a pixel unit multiplex a pixel driver circuit P-Drive, which can reduce the space occupied by a single pixel unit, and thus can increase the number of pixels that can be laid out in the display area, i.e., increase the pixel density.
In the present disclosure, the sub-pixels in the pixel unit are set to share the same pixel driver circuit P-Drive, and the switching circuit MSW performs conduction (on/off) switching between the sub-pixels and the pixel driver circuit P-Drive, which can greatly reduce the space occupied by the pixel unit and thus increase the pixel layout density of the display area because the switching unit in the switching circuit MSW occupies a much smaller space than that of a single pixel driver circuit P-Drive. Compared to a structure of a display panel in which one sub-pixel corresponds to one pixel driver circuit P-Drive, the overall occupied area of a single pixel unit in the display panel of the present disclosure can be reduced by more than 30%, and it is clear that the pixel density in the display panel of the present disclosure can be greatly increased.
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It should be understood that the orthographic projection of the pixel driver circuit P-Drive on the base substrate described in the present disclosure can be understood as the orthographic projection of the layout structure for forming each component in the pixel driver circuit P-Drive on the base substrate. Similarly, the orthographic projection of the switching unit on the base substrate may be understood as the orthographic projection of the layout structure for forming the switching unit on the base substrate.
In the embodiment, the switching circuit MSW may be controlled by the switching signal output from a switch driving circuit MOA. The switch driving circuit MOA may include a plurality of cascaded third shift register units. Each third shift register unit provides the switching signal to the switching units in the pixel row corresponding to it, and the plurality of shift register units are cascaded such that the switch driving circuit MOA provides the switching signals to the switching units in each row in turn.
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For example, the first sub-switch driving circuit MOAR of the first row may first output a first switching signal to turn on all the first switching units MUX1 of the first row, so that each of the first sub-pixels of the first row is connected to a corresponding pixel driver circuit P-Drive, and, at the same time, a third driving circuit RST GOA, a first driving circuit Gated GOA, and a second driving circuit EM GOA in the display panel may sequentially provide a reset signal, a gate control signal, and an enable signal to the pixel drive circuits P-Drive of the first row, and the pixel driver circuits P-Drive provide driving currents to the first sub-pixels of the first row in response to the above-described signals, so that each of the first sub-pixels of the first row emits light for display during an effective time of the first switching signal. Then, the second sub-switch driving circuit MOAG of the first row outputs a second switching signal to turn on all the second switching units MUX2 of the first row to connect the second sub-pixels of the first row to the corresponding pixel driver circuits P-Drive, and during the second switching signal, the above-described process is repeated for the third driving circuit RST GOA, the first driving circuit Gate GOA, and the second driving circuit EM GOA to output the reset signal, the gate control signal, and the enable signal, respectively, so that at this time, the pixel driver circuits P-Drive of the first row can provide driving currents to the second sub-pixels to drive the second sub-pixels of the first row to emit light for display. Then, the third sub-switch driving circuit MOAB of the first row outputs a thirdswitching signal to turn on all the third switching units MUX3 of the first row to connect the pixel driver circuits P-Drive of the first row to the third sub-pixels, and the third driving circuit RST GOA, the first driving circuit Gate GOA, and the second driving circuit EM GOA of the display panel respectively output the reset signal, the gate control signal and the enable signal in sequence, and at this time, the pixel driver circuit P-Drive of the first row can provide driving currents to the third sub-pixels to drive the third sub-pixels of the first row to emit light for display. Thereafter, the switch driving circuit MOA, the third driving circuit RST GOA, the first driving circuit Gate GOA, and the second driving circuit EM GOA repeat the signal output process described above, respectively, to light up the first sub-pixels, the second sub-pixels, and the third sub-pixels row by row and time-sharing.
As can be seen that, in the present disclosure, the display panel of the present disclosure can be driven to emit light for display by increasing the operating frequency of the third driving circuit RST GOA, the first driving circuit Gate GOA, and the second driving circuit EM GOA, and by outputting corresponding switching signals from the set switch driving circuit MOA, i.e., normal light-emitting display of the display panel can be realized under the structure in which the PPI of the pixels is increased. It should be understood that in other embodiments, the display panel may also be provided with other driving methods, and based on the other driving methods, the display panel of the present disclosure may also be driven to display normally.
For example, as described above, the display panel typically includes a third driving circuit RST GOA, a first driving circuit Gate GOA, and a second driving circuit EM GOA, each of which includes a plurality of cascaded shift register units, and the shift register units of the respective driving circuits are distributed between two adjacent rows of pixels. It could be known that a driving circuit has only one or a few columns of shift register units, which is much less than the number of columns of pixels in the display panel, and thus most of the gaps between two adjacent rows in the pixel columns are unused, and in the present disclosure, these existing unoccupied inter-row gaps can be used to place all the cascaded shift register units of the switch driving circuits MOA, so as to eliminate the need to occupy additional space in the display area and improve the utilization of space in the display area. This structure is particularly suitable for splicing screen display products, which have only the display area, and this layout can utilize the existing space so that the switch driving circuits MOA do not need to occupy other display space.
In some embodiments, the switching circuit MSW may be driven by time-sharing without the switch driving circuit MOA. For example, a driver integrated circuit DIC may output a corresponding switching signal to control the time-sharing conduction of each switching unit in the switching circuit MSW. Exemplarily,
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In the embodiment, each functional device in the pixel driver circuit P-Drive may be implemented by a transistor. Exemplarily, as shown in
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In the reset phase t1, the second reset signal terminal RSTB outputs a low-level second reset signal to turn on the eighth transistor M8, the data signal terminal Vdata outputs a low-level signal that is transmitted to the fifth node N5 and stored by the first capacitor C1, and the ninth transistor M9 is turned on under the signal from the fifth node N5 in order to write a high-level signal from the enable signal terminal EM to the control end of the sixth transistor M6, and the sixth transistor M6 is turned off. Then, the first reset signal terminal RSTA outputs a first reset signal to turn on the first transistor M1 and the seventh transistor M7, respectively, and the initial signal terminal Vinit outputs an initial signal to reset the first node N1 and the fourth node N4 as well as the first capacitor C1 and the second capacitor C2. Thereafter, the ninth transistor M9 maintains a turn-on state under the low-level signal stored in the first capacitor C1, and the eleventh transistor M11 is turned off.
In the compensation phase t2, the gate signal terminal Gate outputs a low-level gate control signal to turn on the fourth transistor M4, the fourth transistor M4 writes the data signal signal from the data signal terminal Vdata to the third node N3, and writes it to the gate of the driver transistor M3 through the action of the driver transistor M3, in order to realize the compensation of the threshold voltage of the driver transistor M3.
In the light-emitting phase t3, the enable signal terminal EM outputs a low-level signal to turn on the fifth transistor M5, and the low-level signal output from the enable signal terminal EM is written to the gate of the sixth transistor M6 through the ninth transistor M9 to control the sixth transistor M6 to turn on, at which time the switching unit that is turned on connects the first electrode P-AOD of the corresponding sub-pixel to the fourth node N4 so that the sub-pixel is driven to emit light.
In the reset phase t1, the second reset signal terminal RSTB outputs a low-level second reset signal to turn on the eighth transistor M8, the data signal terminal Vdata outputs a high-level signal that is transmitted to the fifth node N5, and the ninth transistor M9 is turned off. Then, the first reset signal terminal RSTA outputs a low-level first reset signal to turn on the tenth transistor M10, the data signal terminal Vdata outputs a low-level data signal that is transmitted to the sixth node N6, and the eleventh transistor M11 is turned on under the action of the low-level signal from the sixth node N6. Thereafter, under the action of the low-level signal stored in the second capacitor C2, the eleventh transistor M11 maintains the turn-on state and the ninth transistor M9 is turned off.
In the compensation phase t2, the gate signal terminal Gate outputs a low-level gate control signal to turn on the fourth transistor M4, and the fourth transistor M4 writes the data signal written by the data signal terminal Vdata to the third node N3 and to the first node N1 through the action of the driver transistor M3, in order to realize the threshold voltage compensation for the driver transistor M3.
In the light-emitting phase t3, the enable signal terminal EM outputs a low-level signal to turn on the fifth transistor M5, and the high-frequency signal terminal HF outputs a low-level signal that is transmitted to the gate of the sixth transistor M6 through the eleventh transistor M11, and the sixth transistor M6 is turned on, at which time the switching unit that is turned on connects the first electrode P-AOD of the corresponding sub-pixel to the fourth node N4 so that the sub-pixel is driven to emit light.
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A third active portion 23 is used to form a channel region of the driver transistor M3. A fifth sub-active portion 205 and a sixth sub-active portion 206 are connected to two sides of the third active portion 23 to form a first end and a second end of the driver transistor M3, respectively. The fifth sub-active portion 205 may be connected to a fifth transfer portion 405 disposed in the third conductive layer 4 through a via hole to connect the first end of the driver transistor M3 to the third node N3. The sixth sub-active portion 206 may be connected to the fourth transfer portion 404 through a via hole to connect the second end of the drive transistor M3 to the second node N2, i.e., to the second end of the second transistor M2.
A fourth active portion 24 is used to form a channel region of the fourth transistor M4. A seventh sub-active portion 207 and an eighth sub-active portion 208 are connected to two sides of the fourth active portion 24 to form the first end and the second end of the fourth transistor M4, respectively. The seventh sub-active portion 207 may be connected to the data signal line Data through a via hole in order to connect the first end of the fourth transistor M4 to the data signal terminal Vdata. The eighth sub-active portion 208 may be connected to the fifth transfer portion 405 disposed in the third conductive layer 4 through a via hole in order to connect the second end of the fourth transistor M4 to the third node N3 through the fifth transfer portion 405.
A fifth active portion 25 is used to form a channel region of the fifth transistor M5. A ninth sub-active portion 209 and a tenth sub-active portion 210 are connected to two ends of the fifth active portion 25, respectively, to form the first end and the second end of the fifth transistor M5. The ninth sub-active portion 209 may be connected to a seventeenth conductive block 417 (specifically, it may be connected to a sub-conductive portion of the seventeenth conductive block 417) through a via hole in order to connect the first end of the fifth transistor M5 to the first power supply terminal VDD. The tenth sub-active portion 210 may be connected to the fifth transfer portion 405 through a via hole in order to connect the second end of the fifth transistor M5 to the third node N3.
A sixth active portion 26 is used to form a channel region of the sixth transistor M6. An eleventh sub-active portion 211 and a twelfth sub-active portion 212 are connected to two ends of the sixth active portion 26 to form the first end and the second end of the sixth transistor M6, respectively. The eleventh sub-active portion 211 may be connected to the fourth transfer portion 404 through a via hole in order to connect the first end of the sixth transistor M6 to the second node N2. The twelfth sub-active portion 212 may be connected to a sixth transfer portion 406 through a via hole in order to connect the second end of the sixth transistor M6 to the fourth node N4.
A seventh active portion 27 is used to form a channel region of the seventh transistor M7. The second sub-active portion 202 and a fourteenth sub-active portion 214 are connected to two sides of the seventh active portion 27 to form the first end and the second end of the seventh transistor M7. The second sub-active portion 202 may be connected to the second transfer portion 402 through a via hole in order to connect the first end of the seventh transistor M7 to the initial signal terminal Vinit through the second transfer portion 402. The fourteenth sub-active portion 214 may be connected to the sixth transfer portion 406 through a via hole in order to connect the second end of the seventh transistor M7 to the fourth node N4 through the sixth transfer portion 406.
An eighth active portion 28 is used to form a channel region of the eighth transistor M8. A fifteenth sub-active portion 215 and a sixteenth sub-active portion 216 are connected to two ends of the eighth active portion 28 to form the first end and the second end of the eighth transistor M8, respectively. The fifteenth sub-active portion 215 may be connected to the data signal line Data through a via hole in order to connect the first end of the eighth transistor M8 to the data signal terminal Vdata. The sixteenth sub-active portion 216 may be connected to a seventh transfer portion 407 through a via hole to connect the second end of the eighth transistor M8 to the first electrode of the first capacitor C1 through the seventh transfer portion 407.
A ninth active portion 29 is used to form a channel region of the ninth transistor M9. A seventeenth sub-active portion 217 and an eighteenth sub-active portion 218 are connected to two sides of the ninth active portion 29 to form the first end and the second end of the ninth transistor M9, respectively. The seventeenth sub-active portion 217 may be connected to a tenth conductive block 310 through a via hole (the tenth conductive block 310 is connected to an eighth transfer portion 408 through a via hole), in order to connect the first end of the ninth transistor M9 to the enable signal terminal EM through the tenth conductive block 310. The eighteenth sub-active portion 218 may be connected to a ninth transfer portion 409 through a via hole in order to connect the second end of the ninth transistor M9 to the gate of the sixth transistor M6 through the ninth transfer portion 409.
A tenth active portion 230 is used to form a channel region of the tenth transistor M10. A nineteenth sub-active portion 219 and a twentieth sub-active portion 220 are connected to two sides of the tenth active portion 230 in order to form the first end and the second end of the tenth transistor M10, respectively. The nineteenth sub-active portion 219 may be connected to the data signal line Data through a via hole in order to connect the first end of the tenth transistor M10 to the data signal terminal Vdata. The twentieth sub-active portion 220 may be connected to an eleventh transfer portion 411 through a via hole, the eleventh transfer portion 411 may be connected to a ninth conductive block 39 through a via hole, the ninth conductive block 39 is connected to a twelfth transfer portion 412 through a via hole, and the other end of the twelfth transfer portion 412 is connected to the second conductive block 32 (the second electrode of the second capacitor C2) through a via hole, so that the second end of the tenth transistor M10 is connected to the second electrode of the second capacitor C2.
An eleventh active portion 240 is used to form a channel region of the eleventh transistor M11. A twenty-first sub-active portion 221 and the twenty-second sub-active portion 222 are connected to two sides of the eleventh active portion 240 to form the first end and the second end of the tenth transistor M10, respectively. The twenty-first sub-active portion 221 may be connected to a sixteenth transfer portion 416 through a via hole, and the sixteenth transfer portion 416 is connected to a second high-frequency signal line HF2 through a seventh conductive block 37 so as to connect the first end of the eleventh transistor M11 to the high-frequency signal terminal HF. The twenty-second sub-active portion 222 may be connected to the ninth transfer portion 409 through a via hole so as to connect the second end of the eleventh transistor M11 to the gate of the sixth transistor M6 through the ninth transfer portion 409.
A twelfth active portion 250 is used to form a channel region of the twelfth transistor M12. A twenty-third sub-active portion 223 and a twenty-fourth sub-active portion 224 are connected to two sides of the twelfth active portion 250 to form the first end and the second end of the twelfth transistor M12, respectively. The twenty-third sub-active portion 223 may be connected to the sixth transfer portion 406 through a via hole to connect the first end of the twelfth transistor M12 to the fourth node N4 through the sixth transfer portion 406. The twenty-fourth sub-active portion 224 may be connected to a thirteenth transfer portion 413 through a via hole to connect the second end of the twelfth transistor M12 to the first electrode of the first sub-pixel through the thirteenth transfer portion 413.
A thirteenth active portion 260 is used to form a channel region of the thirteenth transistor M13. A twenty-fifth sub-active portion 225 and a twenty-sixth sub-active portion 226 are connected to two sides of the thirteenth active portion 260 to form the first end and the second end of the thirteenth transistor M13, respectively. The twenty-fifth sub-active portion 225 may be connected to the sixth transfer portion 406 through a via hole in order to connect the first end of the thirteenth transistor M13 to the fourth node N4 through the sixth transfer portion 406. The twenty-sixth sub-active portion 226 may be connected to a fourteenth transfer portion 414 through a via hole in order to connect the second end of the thirteenth transistor M13 to the first electrode of the second sub-pixel through the fourteenth transfer portion 414.
A fourteenth active portion 270 is used to form a channel region of the fourteenth transistor M14. A twenty-seventh sub-active portion 227 and a twenty-eighth sub-active portion 228 are connected to two sides of the fourteenth active portion 270 to form the first end and the second end of the fourteenth transistor M14, respectively. The twenty-seventh sub-active portion 227 may be connected to the sixth transfer portion 406 through a via hole in order to connect the first end of the fourteenth transistor M14 to the fourth node N4 through the sixth transfer portion 406. The twenty-eighth sub-active portion 228 may be connected to a fifteenth transfer portion 415 through a via hole in order to connect the second end of the fourteenth transistor M14 to the first electrode of the third sub-pixel through the fifteenth transfer portion 415.
The active layer 2 of the present disclosure may be formed from a polysilicon semiconductor material, and accordingly, the transistor in the display panel of the present disclosure may be a P-type low-temperature polysilicon thin-film transistor.
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In the display panel of the present disclosure, the second conductive layer 3 may be used as a mask to perform conductorization processing on the active layer 2, i.e., the active layer 2 covered by the second conductive layer 3 forms a channel region of the transistor, and the region of the active layer 2 not covered by the second conductive layer 3 forms a conductor structure.
It will be understood that an orthographic projection of a certain structure A on the base substrate covering an orthographic projection of another structure B on the base substrate described in the present disclosure, may be understood to be that an outline of the projection of structure B in the plane of the base substrate lies entirely within an outline of the projection of structure A in the same plane.
In addition, a certain structure A extending along a direction B described in the present disclosure means that the structure A may include a major portion and a minor portion connected to the major portion, the major portion being a line, line segment, or bar-shaped body, the major portion extending along the direction B, and the length of the major portion extending along direction B is greater than the length of the minor portion extending along the other direction.
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A twenty-third conductive block 503 is used to form the second electrode P-CTO of the first sub-pixel. The twenty-third conductive block 503 may be connected to the second power line VSS1 of the second conductive layer 3 through a via hole, in order to connect the second electrode P-CTO of the first sub-pixel to the corresponding second power supply terminal. A twenty-fourth conductive block 504 is used to form the second electrode P-CTO of the second sub-pixel, and a twenty-fifth conductive block 505 is used to form the second electrode P-CTO of the third sub-pixel. The twenty-fourth conductive block 504 and the twenty-fifth conductive block 505 may be connected to the third power line VSS2 of the second conductive layer 3 through via holes, respectively, in order to connect the second electrode P-CTO of the second sub-pixel and the second electrode P-CTO of the third sub-pixel to the corresponding second power supply terminal.
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The present disclosure further provides a display device including a display panel described in any of the embodiments of the present disclosure.
Those skilled in the art, after considering the specification and practicing the invention disclosed herein, will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and that include common knowledge or customary technical means in the technical field that are not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the disclosure is indicated by the appended claims.
The present application is the U.S. National phase application of International Application No. PCT/CN2022/101312, filed on Jun. 24, 2022, the entire contents of which are hereby incorporated by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/101312 | 6/24/2022 | WO |
