Patent Application
20250131874
This application claims priority to Chinese Patent Application No. 202410141857.9, entitled “DISPLAY PANEL AND DISPLAY DEVICE,” filed on Jan. 31, 2024, the content of which is hereby incorporated herein in its entirety by reference.
The present application relates to the field of display technologies, and in particular, to a display panel and a display device.
With the development of display technologies, display panels are more and more widely used in people's production and daily life. Accordingly, people's requirements for display panels are becoming increasingly high. How to reduce the power consumption of display panels has always been a subject of significant attention.
In view of this, the present application is dedicated to providing a display panel and a display device, which can effectively reduce signal interference and improve touch performance.
In a first aspect, the present application provides a display panel. The display panel includes: a demultiplexer circuit and a plurality of driving modules,
Optionally, the duration of the first pulse received by all of the select lines in the select line group covers a plurality of the hold frames; and
Optionally, the select line group includes a first type of select line and a second type of select line; and the first pulse includes a first type of pulse and a second type of pulse;
Optionally, the display panel further includes a plurality of light-emitting pixels, where a plurality of select lines of the at least one select line group are respectively connected to corresponding light-emitting pixels through the switching elements and the driving modules; and
Optionally, the bias voltage includes a first type of bias voltage and a second type of bias voltage, a voltage value of the first type of bias voltage being different from a voltage value of the second type of bias voltage.
Optionally, the light-emitting pixels include a first color light-emitting pixel;
Optionally, the bias voltage further includes a third type of bias voltage; and
Optionally, the light-emitting pixels include a first color light-emitting pixel, a second color light-emitting pixel, and a third color light-emitting pixel;
Optionally, a number of select lines in the select line group is greater than or equal to 2 and less than or equal to 12;
Optionally, the select line group includes a first color select line, a second color select line, and a third color select line, where
Optionally, voltage values of bias voltages received by the driving modules in the plurality of hold frames are the same and remain constant;
Optionally, the select lines in the at least one select line group receive the first pulse in a time-division manner in the hold frames.
In a second aspect, an embodiment of the present application further provides a display device, including the display panel according to the first aspect of the present application.
In the solution of the present application, the display panel includes a demultiplexer circuit and a plurality of driving modules, where the demultiplexer circuit includes at least one select line group and a plurality of switches, the select line group including a plurality of select lines, and a plurality of select lines of the at least one select line group being respectively connected to the corresponding driving modules through the switching elements; one frame of image of the display panel includes a plurality of hold frames; the select line is configured to receive a first pulse in the hold frame, and during the duration of the first pulse, a switching element connected to the select line conducts to cause the corresponding driving module to receive a bias voltage, so as to mitigate the bias problem, where the duration of the first pulse received by at least one of the select lines in the select line group covers a plurality of the hold frames. In this way, while ensuring the mitigation of the problem of low-frequency flicker, by setting the duration of the first pulse received by the at least one select line to cover a plurality of the hold frames, the number of pulses received by the demultiplexer circuit in all of the hold frame phases can be greatly reduced, thereby decreasing the action of the clock signal and lowering the power consumption of the display panel.
By providing a more detailed description of the embodiments of the present application in conjunction with the accompanying drawings, the above and other objectives, features, and advantages of the present application will become more apparent. The accompanying drawings are intended to provide further understanding of the embodiments of the present application and constitute a part of the specification, and, together with the embodiments of the present application, are used to explain the present application without constituting a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.
Unless otherwise defined, the technical or scientific terms used in the embodiments of the specification shall have the common meanings as understood by those of ordinary skill in the art to which the specification belongs. “First”, “second”, and like words used in the embodiments of the specification do not indicate any order, quantity, or importance, but are merely employed to avoid confusion among constituent elements.
Unless the context requires otherwise, throughout the specification, “a plurality of” means “at least two”, and “comprising/including” is to be interpreted as an open, inclusive meaning, that is, “including, but not limited to”. In the description of the specification, “one embodiment”, “some embodiments”, “exemplary embodiment”, “example”, “specific example”, or “some examples” and other terms are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the specification. The schematic expressions of the above terms do not necessarily refer to the same embodiments or examples.
The technical solutions in the embodiments of the specification will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the specification. Apparently, the embodiments described are merely some rather than all of the embodiments of the specification. All other embodiments derived by those of ordinary skill in the art on the basis of the embodiments in the specification without creative efforts are within the scope of protection of the specification.
At present, in order to reduce the overall power consumption, there is a growing demand for low-frequency display. Low-temperature polycrystalline oxide (LTPO) transistors have become the mainstream solution for low-frequency display due to their low current leakage.
Taking 1 Hz timing as an example, a 1 Hz timing solution is implemented in the form of 60 Hz frame skip, that is, sharing 60 Hz timing, and only emitting light without performing data write operations during a hold frame phase. In addition, during the hold frame phase, in order to improve the bias of a driving transistor, a bias voltage is applied through a data line to act on the source of the driving transistor to mitigate the problem of voltage bias. Moreover, in order to reduce wiring arrangements, a display panel further incorporates a demultiplexer circuit (demux). The demultiplexer circuit, also known as a data distribution circuit, is a circuit that switches a signal on a common input line to one of several separate output lines. The data distribution function of the demultiplexer circuit can greatly reduce the number of wiring arrangements in the bezel, so as to meet the requirement for the narrow bezel of the display panel while meeting the data transmission requirement of a large number of display pixels.
Referring to
A timing diagram corresponding to
In view of this, the present application provides a solution that can effectively reduce the power consumption of the display panel. During a plurality of hold frames, in response to a first pulse, a bias voltage is supplied to a plurality of driving modules to mitigate the problem of voltage bias, thereby ensuring the light-emitting effect of the display panel. In addition, by adjusting the duration of the first pulse, the duration of at least one type of first pulse in the demultiplexer circuit covers a plurality of hold frames, which can greatly reduce the number of first pulses received by the demultiplexer circuit in all of the hold frame phases, thereby reducing the number of clock signals, for reducing the power consumption of the display panel.
Specifically, as an optional implementation of the disclosure of the present application, an embodiment of the present application provides a display panel.
The demultiplexer circuit 01 may include m select line groups Group and a plurality of switching elements K, where m is a positive integer greater than or equal to 1. The select line group Group includes a plurality of select lines. Select lines Mux in the select line group Group are respectively connected to the corresponding driving modules 02 through the switching elements K.
In some embodiments, as shown in
Taking an example where there are 2 select line groups, with each select line group having 6 select lines, as shown in
It should be noted that in the embodiments of the present application, the grouping of the select lines is performed based on their electrical connection to light-emitting pixels of different colors, and no physical changes to the select lines in the same select line group in the display panel are required.
One frame of image of the display panel may include a plurality of hold frames.
Specifically, the select line in the m select line groups Group is configured to receive a first pulse in the hold frames, and during the duration of the first pulse, a switching element connected to the select line conducts to cause the corresponding driving module to receive a bias voltage.
When receiving the first pulse in the hold frames, the select lines in the m select line groups Group may receive the first pulse in a time-division manner.
During implementation, the switching elements K may include a thin film transistor. That is, a first terminal of the switching element K is a first terminal of the thin film transistor and a second terminal of the switching element K is a second terminal of the thin film transistor, and the first terminal of the switching element K is connected to a DDIC data line and the second terminal of the switching element K is connected to a data write terminal of the driving module 02. Specifically, a control terminal of the thin film transistor is connected to the select line, the first terminal of the thin film transistor is connected to the DDIC data line (Source1), and the second terminal is connected to the data write terminal of the driving module 02, and the control terminal of the thin film transistor is configured to control the conduction between the first terminal and the second terminal. In an embodiment of the present application, when the control terminal of the thin film transistor receives the first pulse, the thin film transistor is in a conducting state. That is, during the duration of the first pulse received by a select line Mux in the select line group Group, the bias voltage provided by the Source1 is written to the data write terminal of the driving module through the thin film transistor that has received the first pulse, for the purpose of voltage bias improvement.
The duration of the first pulse received by at least one of the select lines in the select line group covers a plurality of the hold frames. That is, there is at least one select line in the select line group that only receives the first pulse once in a plurality of consecutive hold frame phases. Compared with the conventional method in which each hold frame contains a first pulse, the total number of first pulses received in all of the hold frame phases is significantly reduced, thereby reducing the power consumption.
In some embodiments, the one frame of image of the display panel may further include a data write frame.
Correspondingly, select lines in the m select line groups Group may also be configured to receive a second pulse in a time-division manner in the data write frame, and during the duration of the second pulse, switching elements connected to the select lines conduct to cause the corresponding driving modules to receive a data write voltage.
Specifically, if the switching element K is a thin film transistor, during the duration of the second pulse received by a select line Mux in the select line group Group, a data write voltage provided by the Source1 is written to the data write terminal of the driving module through the thin film transistor that has received the second pulse, so as to complete a data write operation. In this way, by responding to the second pulse through the demultiplexer circuit 01 during the data write frame, the data write voltage is provided to the corresponding plurality of driving modules 02 to cause the driving modules 02 to drive the corresponding light-emitting pixels 03 to emit light.
It should be noted that, for different select lines, the spacing between the rising edge of a pulse signal received in the T1 phase and the falling edge of a pulse signal received in the T2 phase may be the same or different. That is, the time interval between receiving the second pulse in the T1 phase and receiving the first pulse in the T2 phase may be the same or different.
Certainly,
In addition, it should be noted that all of the select lines in the demultiplexer circuit 01 receiving the second pulse in the data write frame in a time-division manner and receiving the first pulse in the hold frames in a time-division manner is to avoid the situation where there are at least two of the switching elements receiving the second pulse or the first pulse simultaneously, thereby avoiding data crosstalk caused by the simultaneous conduction of the switching elements.
In some embodiments, the duration of the first pulse received by all of the select lines in the select line groups Group covers a plurality of hold frames.
Comparing the case where the duration of the first pulse received by all of the select lines covers a plurality of hold frames to the case where the duration of the first pulse received by part of the selection lines covers the plurality of hold frames, when the condition of the plurality of hold frames covered by the duration is the same, it can further reduce the total number of pulses in the case where the duration of the first pulse received by all of the select lines covers a plurality of hold frames, thereby reducing the power consumption of the display panel.
Certainly, the present application is not limited thereto, and in some other embodiments, the duration of the first pulse received by all of the select lines may cover all of the hold frames.
Compared to the case where the duration of the first pulse covers not all of the hold frames, if the duration of the first pulses covers all of the hold frames, the total number of pulses can be further reduced, thereby further reducing the power consumption of the display panel.
In addition, considering that driving transistors in driving modules corresponding to the light-emitting pixels of different colors have different characteristics, the select lines may be divided in order to balance the reduction of power consumption and the effect of low-frequency flicker improvement. Specifically, in some embodiments, the select line group may include a first type of select line and a second type of select line; and the first pulse may include a first type of pulse and a second type of pulse.
The first type of select line receives at least the first type of pulse in the plurality of hold frames, and the second type of select line receives the second type of pulse in each of the plurality of hold frames; the duration of the first type of pulse covers a plurality of the hold frames; and the duration of the second type of pulse is less than the duration of one of the hold frames. During implementation, among the plurality of hold frames, the first type of select line may receive the first type of pulse in part of the hold frames, or may receive the first type of pulse in all of the hold frames. For example, in the timing control shown in
In this way, by using the first type of select line to receive at least the first type of pulse in the plurality of hold frames, the number of the first type of pulses received throughout the entire hold frame phase can be effectively reduced, that is, the number of first pulses is reduced, thereby achieving the effect of reducing the power consumption.
On the one hand, when the first type of select line receives the first type of pulse in all of the hold frames, the duration of the first type of pulse may cover all of the hold frames. Compared to the case where the duration of the first type of pulse covers part of the hold frames, if the duration of the first type of pulse covers all of the hold frames, the total number of pulses can be further reduced, thereby reducing the power consumption of the display panel.
On the other hand, when the first type of select line receives the first type of pulse in part of the hold frames, the first type of select line may further receive the second type of pulse in the plurality of hold frames.
Specifically, when the first type of select line receives the first type of pulse in part of the plurality of hold frames, the first type of select line may receive the second type of pulse in the remaining part (the part in which the first type of pulse is not received) of the plurality of hold frames.
In some embodiments, the select line group may further include a third type of select line; and accordingly, the first pulse may further include a third type of pulse. The third type of select line receives the third type of pulse in the plurality of hold frames, and the duration of the third type of pulse covers all of the hold frames.
For the same select line, if the duration of the first pulse it receives covers all of the hold frames, it is clear that fewer first pulses are required than that in the case where the duration of the first pulse it receives covers part of the hold frames. That is, when the duration of the first pulse received by the select line covers all of the hold frames, a greater power consumption reduction can be achieved.
Thus, in some embodiments, in the select line group, the first type of select line may receive the first type of pulse in part of the hold frames among all of the hold frames, and receive the second type of pulse in the remaining part of the hold frames; the second type of select line may receive the second type of pulse; and the third type of select line may receive the third type of pulse. This can effectively reduce the number of pulses received in the entire hold frame phase while taking into account the display requirements, thereby achieving the effect of reducing the power consumption.
In addition, in order to balance the reduction of power consumption and the effect of low-frequency flicker improvement, the bias voltage may also be divided. Specifically, the bias voltage may include a first type of bias voltage and a second type of bias voltage, the first type of bias voltage and the second type of bias voltage having different voltage values.
Providing bias voltages with different voltage values for the driving modules corresponding to the light-emitting pixels of different light-emitting colors can enable the corresponding driving modules to better mitigate the problem of voltage bias based on the received bias voltages, thereby improving the display effect of the display panel more flexibly.
During implementation, the light-emitting pixels may include a first color light-emitting pixel. The second type of select line is connected to the corresponding first color light-emitting pixel through the switching element and the driving module. During the duration of the second type of select line, the switching element connected to the second type of select line conducts to cause the corresponding driving module to receive the first type of bias voltage, thereby achieving bias improvement for the first color light-emitting pixel.
During implementation, the voltage value of the first type of bias voltage may be less than the voltage value of the second type of bias voltage. Accordingly, the first color light-emitting pixel may include a blue light-emitting pixel. Alternatively, the voltage value of the first type of bias voltage may be greater than the voltage value of the second type of bias voltage. Accordingly, the first color light-emitting pixel may include a green light-emitting pixel.
As such, the bias voltages received by the driving modules corresponding to the light-emitting pixels of different light-emitting colors are adjusted, so that the display effect of the display panel can be improved while reducing the power consumption of the display panel.
It should be noted that the bias value of the bias voltage required by a driving module corresponding to the blue light-emitting pixel is lower than that required in the case of the conventional red light-emitting pixel and green light-emitting pixel. Therefore, the voltage value provided to the driving module corresponding to the blue light-emitting pixel is the first type of bias voltage, which is lower than the second type of bias voltage, thereby reducing the power consumption while taking into account the light-emitting effect of the blue light-emitting pixel. Similarly, appropriate bias voltages are respectively provided for the red light-emitting pixel and the green light-emitting pixel, thereby achieving the purpose of reducing the power consumption and improving the light-emitting effect.
As shown in
In order to further improve the display effect of the display panel, in some embodiments, the bias voltage may further include a third type of bias voltage. The voltage value of the first type of bias voltage, the voltage value of the second type of bias voltage, and a voltage value of the third type of bias voltage are different from each other.
Specifically, the light-emitting pixels may include a first color light-emitting pixel, a second color light-emitting pixel, and a third color light-emitting pixel. During the duration of the first pulse, the switching element connected to the second type of select line conducts to cause the driving module corresponding to the first color light-emitting pixel to receive the first type of bias voltage and the driving module corresponding to the second color light-emitting pixel to receive the second type of bias voltage; or the driving module corresponding to the first color light-emitting pixel to receive the first type of bias voltage and the driving module corresponding to the third color light-emitting pixel to receive the third type of bias voltage; or the driving module corresponding to the second color light-emitting pixel to receive the second type of bias voltage and the driving module corresponding to the third color light-emitting pixel to receive the third type of bias voltage.
The voltage values of the first type of bias voltage, the second type of bias voltage, and the third type of bias voltage can be set based on the light-emitting colors of the corresponding light-emitting pixels.
As such, the bias voltages with different voltage values are set for the driving modules corresponding to the light-emitting pixels of different colors, so that the light-emitting effects of the color light-emitting pixels can be further improved, thereby further enhancing the display effect of the display panel.
During implementation, the voltage value of the first type of bias voltage is less than the voltage value of the second type of bias voltage, and the voltage value of the second type of bias voltage is less than the voltage value of the third type of bias voltage. The first color light-emitting pixel includes a blue light-emitting pixel, the second color light-emitting pixel includes a red light-emitting pixel, and the third color light-emitting pixel includes a green light-emitting pixel. A lower bias voltage is provided to a driving module with a lower bias voltage requirement, and a higher bias voltage is provided to a driving module with a higher bias voltage requirement, thereby optimizing the bias voltage supply and improving the light-emitting effects of the light-emitting pixels.
As mentioned above, in the display panel according to the embodiment of the present application, the plurality of select lines in the at least one select line group are respectively connected to the corresponding light-emitting pixels 03 through the switching elements K and the driving modules 02, and the number of select lines in the at least one select line group may be greater than or equal to 2 and less than or equal to 12. Setting the number of select lines to be greater than or equal to 2 can reduce the number of wirings in a bezel, meeting a narrow bezel demand of the display panel; and setting the number of select lines to be less than or equal to 12 can reduce the complexity of the demultiplexer circuit and improve the efficiency of data distribution. Specifically, the number of select lines in the select line group may be 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, or 12.
During implementation, the light-emitting pixels 03 may include a first color light-emitting pixel, a second color light-emitting pixel, and a third color light-emitting pixel. Correspondingly, a number of select lines in the at least one select line group is N, N being a multiple of 3. A number of driving modules connected to the first color light-emitting pixel is N/3; a number of driving modules connected to the second color light-emitting pixel is N/3; and a number of driving modules connected to the third color light-emitting pixel is N/3.
The first color light-emitting pixel includes a blue light-emitting pixel; the second color light-emitting pixel includes a red light-emitting pixel; and the third color light-emitting pixel includes a green light-emitting pixel.
For example, if N is 9, the number of driving modules connected to the first color light-emitting pixel is 3, the number of driving modules connected to the second color light-emitting pixel is 3, and the number of driving modules connected to the third color light-emitting pixel is 3. Optionally, there may be 3 select line groups, and the number of select lines in each select line group is 3 as well, and the select lines in each select line group are respectively connected to the first color light-emitting pixel, the second color light-emitting pixel, and the third color light-emitting pixel through the corresponding switching elements.
Correspondingly, the select line group may include a first color select line, a second color select line, and a third color select line. Specifically, the first color select line is connected to the corresponding driving module and first color light-emitting pixel through the switching element; the second color select line is connected to the corresponding driving module and second color light-emitting pixel through the switching element; and the third color select line is connected to the corresponding driving module and third color light-emitting pixel through the switching element. Specifically, the first color select line, the second color select line, and the third color select line are arranged alternately in sequence. For example, when the select line group includes 6 select lines, the arrangement order may be the first color select line, the second color select line, the third color select line, the first color select line, the second color select line, and the third color select line.
In order to further reduce the power consumption, the duration of the first pulse received by each of the first color select line, the second color select line, and the third color select line cover all of the hold frames. As such, in one frame of image, the duration of the first pulse received by all of the select lines covers all of the hold frames, thereby greatly reducing the number of first pulses required by the demultiplexer circuit and reducing the power consumption of the display panel.
In some embodiments, voltage values of bias voltages received by the driving modules in the plurality of hold frames are the same and remain constant. Thus, there is no need to match the time for providing the bias voltages based on the different light-emitting pixels and the duration of the first pulses. This simplifies the timing solution while ensuring a certain effect of low-frequency flicker improvement, making the timing control easier to implement.
During implementation, the number of hold frames can be 59. Thus, one frame of image includes 1 data write frame and 59 hold frames. For a display panel with an original 60 Hz refresh rate, the refresh rate is automatically reduced to 1 Hz to achieve low frequency and low power consumption, while further reducing the power consumption of the display panel.
Alternatively, the number of hold frames may be 3. Thus, one frame of image includes 1 data write frame and 3 hold frames. For the display panel with the original 60 Hz refresh rate, the refresh rate is automatically reduced to 15 Hz. Alternatively, the number of hold frames may be 2. Thus, one frame of image includes 1 data write frame and 2 hold frames. For the display panel with the original 60 Hz refresh rate, the refresh rate is automatically reduced to 20 Hz. In this way, the low frequency and low power consumption is achieved, while further reducing the power consumption of the display panel.
In practical applications, the number of hold frames can be set based on the actual refresh rate adjustment requirements, and no specific limitation is made here.
As an optional implementation of the disclosure of the present application, an implementation of the present application further provides a display device. The display device includes: the display panel according to any of the above embodiments. Referring to
In this embodiment, the display device includes the display panel. During a plurality of hold frames of the display panel, in response to a first pulse, a bias voltage is provided to a plurality of driving modules to mitigate the problem of voltage bias, thereby ensuring the light-emitting effect of the display panel. At the same time, by adjusting the duration of the first pulse, the duration of at least one type of first pulse in the demultiplexer circuit is made to cover a plurality of hold frames, which can greatly reduce the number of first pulses received by the demultiplexer circuit in all of the hold frame phases, thereby reducing the number of clock signals and the power consumption of the display panel. In this way, the display device equipped with this display panel can effectively reduce the power consumption while maintaining the original display effect, thereby improving the cost-effectiveness of the product.
The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments may be referenced to each other.
With respect to the above description of the disclosed embodiments, those skilled in the art could implement or use the present application. Various modifications to these embodiments are apparent to those skilled in the art, and the general principle defined herein may be practiced in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments described herein but is to be accorded with the broadest scope consistent with the principle and novel features disclosed herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202410141857.9 | Jan 2024 | CN | national |
