Patent Application
20240161703
This application claims priority to Chinese Patent Application No. CN 202311322114.3, filed on Oct. 12, 2023, the disclosure of which is incorporated herein by reference in its entirety.
The present application relates to the field of display technology and, in particular, to a display panel and a display device.
With the development of display technology, electronic products having a display function are widely applied in various fields, such as televisions, mobile phones, computers and personal digital assistants which are all electronic products having a display function, and have become an indispensable part of people's life and work. A display panel is a core structure for implementing a display function in an electronic product.
Generally, a pixel array and a driver circuit for driving the pixel array are disposed in the display panel. The driver circuit can scan the pixel array row by row to enable the pixel array to display a picture. However, limited by the function and structure of the driver circuit in the related art, the driver circuit in the related art cannot drive a row of pixels accurately, resulting in inaccurate display brightness of the pixels and affecting the overall display effect of the display panel.
The present application provides a display panel and a display device so that a driver circuit can accurately drive pixels in the display panel, thereby improving the display effect of the display panel.
According to an aspect of the present application, a display panel is included. The display panel includes a driver circuit, a plurality of scan lines, and a plurality of pixels arranged in an array.
Each pixel of the plurality of pixels includes at least one switch transistor, and gates of switch transistors in at least part of a same row of pixels of the plurality of pixels are electrically connected to a same one scan line of the plurality of scan lines.
The driver circuit includes multiple shift register units, and in the multiple shift register units, an i-th shift register unit is cascaded with an (i+n)-th shift register unit, n is a positive integer greater than or equal to 2, and i is a positive integer.
Shift register units are electrically connected to the plurality of scan lines respectively and supply gate drive signals to the plurality of scan lines respectively, and valid pulses of the gate drive signals received by the plurality of scan lines are shifted successively.
The valid pulses of the gate drive signals each have a width denoted as T0; T0>(Th+k*Th), 0<k≤(n−1), and Th=1/(F*L), where F denotes a refresh rate of the display panel, and L denotes the number of rows of the plurality of pixels; and in the multiple shift register units, valid pulses of gate drive signals output by any two adjacent shift register units have a shift amount greater than or equal to Th.
According to another aspect of the present application, a display device is provided and includes the preceding display panel.
To illustrate the technical solutions of embodiments of the present application more clearly, the drawings used in the description of the embodiments are briefly described below. Apparently, the drawings described below merely illustrate part of the embodiments of the present application, and those of ordinary skill in the art may obtain other drawings based on the drawings described below on the premise that no creative work is done.
To make the solutions of the present application better understood by those skilled in the art, the technical solutions of the embodiments of the present application are described below clearly and completely in conjunction with the drawings in the embodiments of the present application. Apparently, the embodiments described below are part, not all, of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art are within the scope of the present application on the premise that no creative work is done.
It is to be noted that terms such as “first” and “second” in the description, claims and drawings of the present application are used for distinguishing between similar objects and are not necessarily used for describing a particular order or sequence. It is to be understood that the data used in this manner is interchangeable in appropriate cases so that the embodiments of the present application described herein can be implemented in an order not illustrated or described herein. Additionally, the terms “including”, “having” and variations thereof are intended to encompass a non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units not only includes the expressly listed steps or units but may also include other steps or units that are not expressly listed or are inherent to such process, method, product, or device.
As described in the background,
When the display panel 01 includes L rows of pixels 010, and the refresh rate of the display panel is F, the driving time period Th of each row of pixels 010 is denoted as 1/(F*L) so that the signal refresh time period of the each row of pixels 010 should be less than or equal to Th to ensure that the driving of the L rows of pixels 010 can be completed within one-frame time period 1/F of the display panel. To satisfy the driving requirement of the each row of pixels 010, in the related art, the valid pulses of the gate drive signals G′ output by the multiple shift register units 031 in the driver circuit 030 each have a width denoted as Th. When a respective shift register unit 031 starts to output the valid pulse of a gate drive signal G′ and transmit the valid pulse of the gate drive signal G′ to the gates of the switch transistors M′ in the same row of pixels 010 through a scan line 020, the valid pulse of the gate drive signal G′ first charges the gates of the switch transistors M′ in the same row of pixels 010. Moreover, when the voltage differences Vgs between the gates and the sources of the switch transistors M′ each satisfy |Vgs|>|Vth| (Vth denotes the threshold voltage of each switch transistor M′), the switch transistors M′ can be turned on. When the display panel 01 has a relatively large size, the number of a row of pixels 010 in the display panel 01 is relatively large, and the number of pixels 010 electrically connected to each scan line 020 is relatively large so that the load at a signal output terminal of a respective shift register unit 031 is relatively large, and thereby all switch transistors in the same row of pixels 010 can be in a normal on state after being charged for a relatively long time period. Consequently, within the time period of the valid pulse of the gate drive signal G′ output by the respective shift register unit 031, the charging duration requirement of the same row of pixels 010 cannot be satisfied, resulting in a relatively short or even impossible conduction duration of the switch transistors M′ in the same row of pixels 010. As a result, signals cannot be insufficiently written into the nodes electrically connected to the switch transistors M′ so that the display brightness of the same row of pixels 010 can be affected, thereby affecting the overall display effect of the display panel 01.
To solve the preceding technical solutions, an embodiment of the present application provides a display panel. The display panel includes a driver circuit, multiple scan lines, and multiple pixels arranged in an array; each pixel includes at least one switch transistor; gates of switch transistors in at least part of the same row of pixels are electrically connected to the same one scan line; the driver circuit includes multiple shift register units; the i-th shift register unit is cascaded with the (i+n)-th shift register unit; n is a positive integer greater than or equal to 2, and i is a positive integer; the multiple shift register units are electrically connected to the multiple scan lines respectively and supply gate drive signals to the multiple scan lines respectively, and valid pulses of the gate drive signals received by the multiple scan lines are shifted successively, where the valid pulses of the gate drive signals each have a width denoted as T0; T0>(Th+k*Th), 0<k≤(n−1), and Th=1/(F*L), where F denotes the refresh rate of the display panel, and L denotes the number of rows of the multiple pixels; and valid pulses of gate drive signals output by any two adjacent shift register units have a shift amount greater than or equal to Th.
By adopting the above technical solution, the i-th shift register unit is cascaded with the (i+n)-th shift register unit so that the valid pulses of the gate drive signals output by the shift register units can each have a width denoted as Th+k*Th while the gate drive signals output by the shift register units are ensured to be shifted successively. The valid pulses of the gate drive signals output by the shift register units each have a width greater than the driving time period Th of one row of pixels so that when the gate drive signals output by the shift register units are each used for controlling switch transistors in a respective same row of pixels to turn on or off, the time period of a valid pulse of a gate drive signal received by switch transistors in each row of pixels can be greater than the driving time period Th of one row of pixels, that is, the time period for charging the gates of the switch transistors in the each row of pixels is greater than the driving time period Th of one row of pixels. Compared with the related art, the time period for charging the gates of the switch transistors in the each row of pixels is increased so that the switch transistors in the each row of pixels can have a sufficiently long conduction time period, especially for display panels having a large size and high resolution; even if the number of pixels connected to the each scan line is relatively large, and the load carried by the each shift register unit is relatively large, a relatively long charging time period can also enable all the gates of the switch transistors in the each row of pixels to be charged until the conduction condition is satisfied so that when the signals at the nodes electrically connected to the switch transistors are refreshed, respective signals can be ensured to be written into the nodes accurately, facilitating the improvement of the display light emission accuracy of the each row of pixels and the improvement of the display light emission effect of the display panel. Additionally, since valid pulses of gate drive signals of two adjacent shift register units have a shift amount greater than or equal to the driving time period Th of one row of pixels, gates of switch transistors in the row of pixels can be pre-charged within the first k*Th time period of the valid pulses of the gate drive signals output by the shift register units so that the switch transistors in the row of pixels can tend to be in a normal on state from an off state. Moreover, within the last Th time period of the valid pulses of the gate drive signals output by the shift register units, the switch transistors in the row of the pixels can be in a normal on state quickly so that within the driving time period Th of at least one row of pixels, the switch transistors in the row of the pixels can be in a normal on state, and so that the time period for supplying the respective signals to the nodes electrically connected to the switch transistors can be the driving time period Th of the at least one row of pixels. Consequently, the respective signals can be written into the rows of pixels accurately so that the rows of pixels can perform light emission for display accurately, thereby improving the display effect of the display panel.
The preceding is a core idea of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art are within the scope of the present application on the premise that no creative work is done. Technical solutions of the embodiments of the present application are described clearly and completely hereinafter in conjunction with the drawings in the embodiments of the present application.
The display panel 100 may be a self-luminous display panel or a non-self-luminous display panel. When being a non-self-luminous display panel, the display panel 100 may include, but is not limited to, a liquid crystal display panel. In this case, the each pixel 10 may further include a pixel electrode and a common electrode. When the at least one switch transistor M0 is turned on, a data signal can be transmitted to the pixel electrode to enable an electric field to be generated between the pixel electrode and the common electrode so that the light-transmissive brightness of the each pixel 10 can be controlled under the action of the electric field, thereby controlling the display brightness of the each pixel 10. When being a self-luminous display panel, the display panel 100 includes, but is not limited to, an organic light-emitting display panel or a micro/mini light-emitting diode (LED) display panel. In this case, the each pixel may include a pixel circuit and a light-emitting element. The pixel circuit may include a drive transistor and at least one switch transistor M0. Each switch transistor M0 can control a data signal to supply to a gate of the drive transistor so that the drive transistor can supply a drive current to the light-emitting element according to the data signal of the gate of the drive transistor, controlling the display brightness of the light-emitting element, that is, controlling the display brightness of the each pixel 10.
It is to be noted that the preceding merely exemplifies that the each switch transistor M0 is a transistor that controls the data signal to write into a respective pixel 10, and in the embodiments of the present application, the each switch transistor M0 may also be a transistor that controls the writing of another signal. This is not specifically limited in the embodiments of the present application. For ease of description, the technical solutions of the embodiments of the present application are illustrated using an example in which the each switch transistor M0 can control the writing of the data signal in the embodiments of the present application.
In an optional embodiment, as shown in
With continued reference to
Exemplarily, using n=2 as an example, the first shift register unit 311 is cascaded with the third shift register unit 313, the second shift register unit 312 is cascaded with the fourth shift register unit 314, the third shift register unit 313 is cascaded with the fifth shift register unit 315, and the fourth shift register unit 314 is cascaded with the sixth shift register unit 316. In this way, the any two adjacent shift register units 31 in the driver circuit 30 are not interconnected so that a gate drive signal Gi output by the previous shift register unit 31i cannot affect a gate drive signal G(i+1) output by the next shift register unit 31(i+1). In this case, during the time period of the valid pulse of the gate drive signal Gi output by the previous shift register unit 31i, the gate drive signal G(i+1) output by the next shift register unit 31(i+1) may also be a valid pulse, that is, the time period of the valid pulse of the gate drive signal Gi output by the previous shift register unit 31i may overlap the time period of the valid pulse of the gate drive signal G(i+1) output by the next shift register unit 31(i+1), so that the valid pulses of the gate drive signals G output by the shift register units 31 can each have a width greater than the driving time period Th of a row of pixels, that is, the valid pulses of the gate drive signals G transmitted by the multiple scan lines 20 can each have a width greater than the driving time period Th of a row of pixels.
The gates of the switch transistors M0 in the same row of pixels 10 are electrically connected to the same one scan line 20 so that a gate drive signal G transmitted by the same one scan line 20 can control the switch transistors M0 in the same row of pixels 10 to turn on or off. When being at a valid level, the gate drive signal G can control the switch transistors M0 to be in an on state, and when being at an invalid level, the gate drive signal G can control the switch transistors M0 to be in an off state.
It is to be understood that the width of the valid pulse of the gate drive signal G is the length of time period for which the gate drive signal G remains at the valid level. The switch transistors M0 may be n-type transistors or p-type transistors. When the switch transistors M0 are n-type transistors, the valid level of the gate drive signal G is a high level, and the invalid level of the gate drive signal is a low level; and when the switch transistors M0 are p-type transistors, the valid level of the gate drive signal G is a low level, and the invalid level of the gate drive signal G is a high level. For ease of description, unless special limitations are made, the technical solutions of the embodiments of the present application are illustrated using an example in which the switch transistors M0 are n-type transistors in the embodiments of the present application.
When the same one scan line 20 is used for transmitting the gate drive signal G, as the transmission distance of the gate drive signal G increases, the voltage drop of the gate drive signal G is more noticeable so that voltages of the gate drive signals received by the same row of pixels 10 at different positions can be different. Consequently, when the valid pulse of the gate drive signal G is used for charging the gates of the switch transistors M0 in the same row of pixels 10, charging durations required for the switch transistors M0 in the same row of pixels 10 at different positions are different. When the time period of the valid pulse of the gate drive signal G transmitted by the same one scan line 20 is sufficiently long, all the switch transistors M0 in the same row of pixels 10 can be ensured to be in a normal on state.
In an embodiment, the valid pulses of the gate drive signals output by the shift register units 31 each have a width denoted as Th+k*Th, that is, the time period for which the gate drive signals G output by the shift register units 31 are remained at the valid pulses is Th+k*Th, and since 0<k≤(n−1), the valid pulses of the gate drive signals G output by the shift register units 31 can each have a width greater than the driving time period Th of a row of pixels 10. When the gate drive signals G output by the shift register units 31 are each used for controlling the switch transistors M0 in the respective same row of pixels 10 to turn on or off, the time period of the valid pulse of the gate drive signal G received by the switch transistors M0 in the each row of pixels 10 is greater than the driving time period Th of a row of pixels 10, that is, the time period for charging the gates of the switch transistors M0 in the each row of pixels 10 is greater than the driving time period Th of a row of pixels 10, so that the gates of the switch transistors M0 in the same row of pixels 10 can have a sufficiently long charging time period, and so that all the switch transistors 10 in the same row of pixels 10 can be in a normal on state. Consequently, through the turned-on switch transistors M0, a data signal can be accurately written into pixels 10 to which the switch transistors M0 belong so that when the pixels 10 perform light emission for display according to the written data signal, the accuracy of the display brightness of the pixels 10 can be improved, thereby improving the overall display effect of the display panel 100.
Exemplarily, an example in which a gate drive signal G1 output by the first shift register unit 311 is transmitted to gates of switch transistors M0 in the first row of pixels 10 through a respective scan line 20, and a gate drive signal G2 output by the second shift register unit 312 is transmitted to gates of switch transistors M0 in the second row of pixels 10 through a respective scan line 20 is used as an example. Since the gate drive signals G output by the shift register units 31 are shifted successively, and the valid pulses of the gate drive signals G output by the two adjacent shift register units 31 have a shift amount T14 greater than or equal to Th, the start time period of the valid pulse of the gate drive signal G1 output by the first shift register unit 311 is located before the start time period of the valid pulse of the gate drive signal G2 output by the second shift register unit 312, the valid pulse of the gate drive signal G1 output by the first shift register unit 311 and the valid pulse of the gate drive signal G2 output by the second shift register unit 312 may have an overlapping time period T13 less than or equal to k*Th, and compared with the valid pulse of the gate drive signal G1 output by the first shift register unit 311, the valid pulse of the gate drive signal G2 output by the second shift register unit 312 has a shift amount T14 greater than or equal to Th.
In the time period T11, the valid level of the gate drive signal G1 output by the first shift register unit 311 is transmitted to the gates of the switch transistors M0 in the first row of pixels 10 through the respective scan line 20 to charge the gates of the switch transistors M0 in the first row of pixels 10 so that the voltage of the gates of the switch transistors M0 in the first row of pixels 10 can tend to be at the valid level of the gate drive signal G1 from the invalid level of the gate drive signal G1, and the switch transistors M0 in the first row of pixels 10 can tend to be in an on state from an off state. Within the time period T12, the gate drive signal G1 output by the first shift register unit 311 continues remaining at the valid level so that the gates of the switch transistors M0 in the first row of pixels 10 can continue being charged based on the voltage charged to the gates of the switch transistors M0 in the first row of pixels 10 in the time period T11, and so that the voltage of the gates of the switch transistors M0 in the first row of pixels 10 can be charged quickly until the conduction condition of the switch transistors M0 is satisfied, that is, in the time period T12, the switch transistors M0 in the first row of pixels 10 can be turned on quickly. At this time period, a data signal of the first row of pixels 10 transmitted by a respective data line 40 is written into the first row of pixels 10 through the turned-on switch transistors M0 so that the time period for writing the data signal can tend to be the total time period of the time period T12. Consequently, the data signal of the first row of pixels 10 can have a sufficiently long writing time period to ensure the accuracy of the data signal written into the first row of pixels 10 so that the first row of pixels 10 can perform light emission for display accurately.
Within the time period T13 in the time period T12, the second shift register unit 312 also outputs the valid level of the gate drive signal G2, and the valid level of the gate drive signal G2 can be transmitted to the gates of the switch transistors M0 in the second row of pixels 10 through the respective scan line 20 to charge the gates of the switch transistors M0 in the second row of pixels 10 so that the voltage of the gates of the switch transistors M0 in the second row of pixels 10 can tend to be at the valid level of the gate drive signal G2 from the invalid level of the gate drive signal G2, and the switch transistors M0 in the second row of pixels 10 can tend to be in a normal on state. Within the time period T14, the first shift register unit 311 outputs the invalid level of the gate drive signal G1, the switch transistors M0 in the first row of pixels 10 tend to be in an off state, and the gate drive signal G2 output by the second shift register unit G2 continues remaining at the valid level so that the gates of the switch transistors M0 in the second row of pixels 10 can continue being charged based on the voltage charged to the gates of the switch transistors M0 in the second row of pixels 10 in the time period T13, and so that the voltage of the gates of the switch transistors M0 in the second row of pixels 10 can be charged quickly until the conduction condition of the switch transistors M0 is satisfied, that is, in the time period T14, the switch transistors M0 in the second row of pixels 10 can be turned on quickly. At this time, a respective data line 40 transmits a data signal of the second row of pixels 10 so that the time for writing the data signal of the second row of pixels 10 can also tend to be the total time of the time period T14, that is, the time period for writing the data signal of the second row of pixels 10 can be greater than or equal to the driving time period Th of a row of pixels. Consequently, the data signal of the second row of pixels 10 can also have a sufficiently long writing time period to ensure the accuracy of the data signal written into the second row of pixels 10 so that the second row of pixels 10 can perform light emission for display accurately.
If the switch transistors M0 in the second row of pixels 10 have been in an on state within the time period T13, the data signal of the first row of pixels 10 transmitted by the respective data line 40 is also written into the second row of pixels 10. In this case, the data signal of the first row of pixels 10 may be used for pre-charging the nodes electrically connected to the switch transistors M0 in the second row of pixels 10 so that the data signal of the second row of pixels 10 can continue being written into the nodes electrically connected to the switch transistors M0 in the second row of pixels based on the signal written into the nodes electrically connected to the switch transistors M0 in the time period T13 when entering the time period T14, and so that the signal at the nodes electrically connected to the switch transistors M0 in the second row of pixels 10 can still remain consistent with the data signal of the second row of pixels 10.
In this way, the any two adjacent shift register units are not interconnected so that the valid pulses of the gate drive signals output by the any two adjacent shift register units can each have a width greater than Th. Consequently, when the shift register units output the valid levels of the gate drive signals, the valid levels of the gate drive signals can charge the gates of the switch transistors in the rows of pixels for a sufficiently long time period, especially for the display panels having a large size and high resolution. Even if the number of pixels electrically connected to the each scan line is relatively large, and the load carried by the each shift register unit is relatively large, all gates of switch transistors in a row of pixels can be charged until the conduction condition is satisfied in the period in which the shift register units output the valid levels of the gate drive signals, ensuring that the switch transistors in the row of pixels can be in a normal on state, and so that the respective signals can be written into the rows of pixels accurately, ensuring that the rows of pixels can perform light emission for display accurately, thereby facilitating the improvement of the display effect of the display panel.
Additionally, since the valid pulses of the gate drive signals of the two adjacent shift register units have a shift amount greater than or equal to the driving time period Th of a row of pixels, the gates of the switch transistors in the row of pixels can be pre-charged within the first k*Th time period of the valid pulses of the gate drive signals output by the shift register units so that the switch transistors in the row of pixels can tend to be in a normal on state from an off state. Moreover, within the last Th time period of the valid pulses of the gate drive signals output by the shift register units, the switch transistors in the row of pixels can be in a normal on state quickly so that within the driving time period Th of the at least one row of pixels, the switch transistors in the row of the pixels can be in a normal on state, and the time period for supplying the respective signals to the nodes electrically connected to the switch transistors can be the driving time period Th of the at least one row of pixels. Consequently, the respective signals can be written into the rows of pixels accurately so that the rows of pixels can perform light emission for display accurately, thereby improving the display effect of the display panel.
It is to be understood that the valid pulses of the gate drive signals output by the shift register units each have a width T10 denoted as Th+k*Th, where k is a positive integer greater than 0 and less than or equal to n−1, so that the valid pulse of the gate drive signal output by the each shift register unit can have a width greater than Th and less than or equal to n*Th. For example, when n is equal to 2, the valid pulse of the gate drive signal may have a width T10 denoted as (4/3)*Th, (3/2)*Th, or 2Th. This may be designed according to actual requirements and is not specifically limited in the embodiments of the present application.
Optionally, with continued reference to
It is to be noted that the technical solutions of the embodiments of the present application are merely illustrated using the preceding example in which n=2, and in the embodiments of the present application, n may be any positive integer greater than or equal to 2, for example, as shown in
In an optional embodiment,
A shift output terminal Next of the i-th shift register unit 31i is electrically connected to a first input terminal IN1 of the (i+n)-th shift register unit 31(i+n). Drive output terminals OUT of the shift register units 31 are electrically connected to the multiple scan lines 20 respectively. For example, when n is equal to 2, the shift output terminal Next of the first shift register unit 311 is electrically connected to the first input terminal IN1 of the third shift register unit 313, and the shift output terminal Next of the second shift register unit 312 is electrically connected to the first input terminal of the fourth shift register unit 314.
It is to be understood that the clock signal CKA received by the clock signal terminal A and the output control signal CKB received by the each output control terminal B may be pulse signals each composed of a high level and a low level, and the clock signal CKA and the output control signal CKB may have the same clock cycle or different clock cycles, and this is not specifically limited in this embodiment. Effective levels of the clock signal CKA and the output control signal CKB may be high levels or low levels, and this may be disposed according to actual requirements and is not specifically limited in the embodiments of the present application. For ease of description, the technical solutions of the embodiments of the present application are illustrated using an example in which the valid levels of the clock signal CKA and the output control signal CKB are high levels in the embodiments of the present application.
In an embodiment, since the shift output terminal Next of the i-th shift register unit 31i is electrically connected to the first input terminal IN1 of the (i+n)-th shift register unit 31(i+n), a shift signal Vnexti output by the shift output terminal of the i-th shift register unit 31i can also serve as a first input signal Vin1(i+n) received by the first input terminal IN1 of the (i+n)-th shift register unit 31(i+n) so that the (i+n)-th shift register unit 31(i+n) can control a shift signal Vnext(i+n) output by a shift output terminal Next of the (i+n)-th shift register unit 31(i+n) and a gate drive signal G(i+n) output by a drive output terminal OUT of the (i+n)-th shift register unit 31(i+n) according to the shift signal Vnexti output by the shift output terminal Next of the i-th shift register unit 31i. In this case, first input terminals IN1 of the shift register units from the first shift register unit 311 to the n-th shift register unit 31n may receive start signals STV1, . . . , STVn respectively, and valid pulses of the start signals STV1, . . . , STVn should be shifted successively to successively start the shift register units from the first shift register unit 311 to the n-th shift register unit 31n so that shift signals Vnext output by shift output terminals Next of the shift register units from the first shift register unit 311 to the n-th shift register unit 31n can be shifted successively, and gate drive signals G output by drive output terminals OUT of the shift register units can be shifted successively, thereby avoiding signal crosstalk and improving the accuracy of the shift signals Vnext and the gate drive signals G that are output by the shift register units 31.
It is to be understood that on the basis that the each shift register unit includes the first input terminal, the clock signal terminal A, the shift output terminal, the at least one drive output terminal and the at least one output control terminal, the each shift register unit may further include other signal terminals and modules so that signals of signal terminals can mutually cooperate with modules to output respective shift signals and gate drive signals.
In an optional embodiment,
The each latch module 310A may include a latch and others. The each latch module 310A may latch the first input signal Vin1 of the first input terminal IN1 and control the shift output terminal Next to output the valid level of the shift signal Vnext when the clock signal CKA is at a valid level, and the each latch module 310A stops latching the first input signal Vin1 of the first input terminal IN1 when the clock signal CKA is at an invalid level. After stopping latching the first input signal Vin1 of the first input terminal IN1, the each latch module 310A may continue controlling the shift output terminal Next to output the valid level of the shift signal Vnext, and the shift output terminal Next starts to output the invalid level of the shift signal Vnext when the clock signal CKA hops to be at the valid level again. In this way, the each latch module 310A may output the valid level or invalid level of the shift signal Vnext under the control of the clock signal CKA and the first input signal Vin1.
In an exemplary embodiment, as shown in
The first inverter U11 and the second inverter U12 may each be composed of one n-type transistor and one p-type transistor. Consequently, when the input terminal of the first inverter U11 receives a high level of the clock signal CKA, the n-type transistor can be controlled to turn on so that the n-type transistor can transmit a low-level signal VGL to the output terminal of the first inverter U11, and the first inverter U11 can output a low-level signal. When the input terminal of the first inverter U11 receives a low level of the clock signal CKA, the p-type transistor can be controlled to turn on so that the p-type transistor can transmit a high-level signal VGH to the output terminal of the first inverter U11, and the first inverter U11 can output a high-level signal. Similarly, when the input terminal of the second inverter U12 is at a high level, the n-type transistor of the second inverter U12 can be controlled to turn on, and when the input terminal of the second inverter U12 is at a low level, the p-type transistor of the second inverter U12 can be controlled to turn on so that a signal of the input terminal of the second inverter U12 and a signal of the output terminal of the second inverter U12 can have opposite polarities.
The first tri-state gate U13 and the second tri-state gate U14 may each be composed of two p-type transistors and two n-type transistors that are successively connected in series. Consequently, when the input terminal of the first tri-state gate U13 receives a high level of the first input signal Vin1, the negative signal control terminal of the first tri-state gate U13 receives the high level of the clock signal CKA, and the positive signal control terminal of the first tri-state gate U13 receives the low-level signal output by the first inverter U11, the two n-type transistors of the first tri-state gate U13 can transmit the low-level signal VGL to the output terminal of the first tri-state gate U13 so that the first tri-state gate U13 can output a low-level signal. When the input terminal of the first tri-state gate U13 receives a low level of the first input signal Vin1, the negative signal control terminal of the first tri-state gate U13 receives the high level of the clock signal CKA, and the positive signal control terminal of the first tri-state gate U13 receives the low-level signal output by the first inverter U11, the two p-type transistors of the first tri-state gate U13 can transmit the high-level signal VGH to the output terminal of the first tri-state gate U13 so that the first tri-state gate U13 can output a high-level signal. Accordingly, the second tri-state gate U14 and the first tri-state gate U13 have similar operation principles, so details are not repeated, and similarities may be referred to the description of the operation process of the first tri-state gate U13.
With continued reference to
In an optional embodiment, with continued reference to
In an exemplary embodiment, as shown in
Since the transistor M1 and the transistor M2 have different types, the transistor M1 and the transistor M2 may be turned on in a time-sharing manner, that is, when the shift output terminal Next is at a high level, the transistor M2 may be in an on state, and when the shift output terminal Next is at a low level, the transistor M1 may be in an on state. Accordingly, the transistor M5 and the transistor M3 are turned on in a time-sharing manner, and the transistor M4 and the transistor M6 are turned on in a time-sharing manner. In this way, when the set signal Vgas of the set signal terminal GAS is at a high level, the transistor M6 may be controlled to turn on, and the transistor M4 may be controlled to turn off so that the low-level signal VGL can be transmitted to the output terminal of the each level conversion module 320A through the transistor M6, and the each level conversion module 320A can output the low level of the respective gate drive signal G. When the set signal Vgas is at a low level, the transistor M6 may be controlled to turn off, and the transistor M4 may be controlled to turn on. At this time, the high-level signal VGH may be transmitted to the first electrode of the transistor M1 and the first electrode of the transistor M5 through the transistor M4. If at least one of the shift signal Vnext of the shift output terminal Next or the output control signal CKB of the respective output control terminal B is at a low level at this time, at least one of the transistor M1 and the transistor M5 may be controlled to turn on correspondingly, and the high-level signal VGH may be transmitted to the output terminal of the each level conversion module 320A through the at least one of the transistor M1 and the transistor M5 so that the each level conversion module 320A can output the high level of the respective gate drive signal G. When the output control signal B and the shift signal Vnext are each at a high level, the transistor M2 and the transistor M3 are turned on so that the low-level signal can be transmitted to the output terminal of the each level conversion module 320A through the transistor M2 and the transistor M3 successively, and so that the each level conversion module 320A can output the low level of the respective gate drive signal. In this way, the each level conversion module 320A may supply the high level or low level of the respective gate drive signal G to the respective output module 330A under the control of the shift signal Vnext, the output control signal CKB and the set signal Vgas.
With continued reference to
In an exemplary embodiment, the each output module 330A may include at least one buffer. Each buffer may be composed of one or more inverters. The number of inverters in the each output module 330A may be odd or even. When the number of inverters in the respective output module 330A is odd, the respective output module 330A can not only convert the polarity of the respective gate drive signal G output by the each level conversion module 320A but also improve the driving capability of the respective gate drive signal G. When the number of inverters in the respective output module 330A is even, the respective output module 330A only needs to improve the driving capability of the respective gate drive signal G, without converting the polarity of the respective gate drive signal G output by the each level conversion module 320A.
Exemplarily, as shown in
Exemplarily,
In an optional embodiment, with continued reference to
In an exemplary embodiment, as shown in
It is to be understood that
Optionally, in conjunction with
A first input signal Vin1 of a first input terminal IN1 of the current shift register unit 31 is a shift signal Vnext output by another shift register unit cascaded with the current shift register unit 31, and a clock signal CKA may control the current shift register unit 31 to latch the first input signal Vin1 received by the first input terminal IN1 of the current shift register unit 31 and control a shift signal Vnext output by the current shift register unit 31. The shift signal Vnext and an output control signal CKB that are output by the current shift register unit 31 can control a gate drive signal G output by the drive output terminal OUT of the current shift register unit 31. In this way, the clock signal CKA and the output control signal CKB of the same one shift register unit 31 are shifted successively, and the time periods of valid pulses of the clock signal CKA and the output control signal CKB do not overlap so that the time period of the valid pulse of the first input signal Vin1 latched by the current shift register unit 31 cannot overlap the time period of the valid pulse of the gate drive signal G output by the each drive output terminal OUT. Meanwhile, since the time period of the valid pulse of the gate drive signal G output by the each drive output terminal OUT overlaps the time period of the valid pulse of the shift signal output by the shift output terminal Next, when the time period of the valid pulse of the first input signal Vin 1 does not overlap the time period of the valid pulse of the gate drive signal G in the same one shift register unit 31, the time periods of valid pulses of gate drive signals output by two shift register units 31 that are cascaded with each other do not overlap so that the valid pulses of the gate drive signals G output by the shift register units 31 do not interfere with each other, and the accuracy of the gate drive signals G output by the shift register units 31 can be improved. Consequently, when the shift register units 31 are used for controlling the switch transistors in the rows of pixels to turn on or off, the states of the switch transistors in the rows of pixels can be controlled accurately so that the respective signals can be written into the rows of pixels accurately, facilitating the improvement of the accuracy of the display light emission of the multiple pixels and improving the overall display effect of the display panel.
It is to be understood that in the same one shift register unit, the clock signal CKA and the output control signal CKB are shifted successively, and the time periods of the valid pulses of the clock signal CKA and the output control signal CKB do not overlap so that when the clock signal CKA is at the valid level, the output control signal CKB can be at the invalid level, and when the output control signal CKB is at the valid level, the clock signal CKA can be at the invalid level. In this case, the clock signal CKA and the output control signal CKB may have the same clock cycle and may be two signals having opposite polarities at the same moment. In this way, a corresponding inverter may be disposed between a terminal for supplying the clock signal CKA and a terminal for supplying the output control signal CKB, without the requirement of disposing a corresponding timing circuit for supplying the clock signal CKA or the output control signal CKB, facilitating the simplification of the structure of the display panel and reducing the cost of the display panel.
Optionally, with continued reference to
In an embodiment, when the valid pulse of the clock signal CKA and the valid pulse of the output control signal CKB each have a width equal to the width of the valid pulse of the gate drive signal, the width of the valid pulse of the gate drive signal G output by the each drive output terminal OUT of the each shift register unit 31 can be controlled by controlling the widths of the valid pulses of the clock signal CKA and the output control signal CKB that are supplied to the each shift register unit 31, that is, the value of k may be selected according to actual requirements, so that the widths of the valid pulses of the clock signal CKA and the output control signal CKB can be disposed according to the value of k, and so that the normal conduction time period of the rows of pixels can be greater than or equal to the driving time period Th of a row of pixels on the premise that the valid pulse of the gate drive signal G has a width greater than the driving time period Th of a row of pixels, thereby enabling the time period for writing signals to the rows of pixels to be greater than or equal to the driving time period Th of a row of pixels, ensuring the accuracy of the signals written into the rows of pixels, improving the accuracy of the display light emission of the multiple pixels and facilitating the improvement of the display effect of the display panel.
Optionally, the time period of the valid pulse of a clock signal received by the i-th shift register unit does not overlap the time period of the valid pulse of a clock signal received by the (i+n)-th shift register unit, and the time period of the valid pulse of an output control signal received by the i-th shift register unit does not overlap the time period of the valid pulse of an output control signal received by the (i+n)-th shift register unit.
In an embodiment, using n=2 as an example, with continued reference to
Accordingly, output control signals CKB received by the shift register units 31 can control the time periods of the valid pulses of the gate drive signals G output by the drive output terminals OUT of the shift register units 31, so when the time period of the valid pulse of an output control signal ckb1 received by the first shift register unit 311 does not overlap the time period of the valid pulse of an output control signal ckb2 received by the third shift register unit 313, the valid pulse of the gate drive signal G1 output by the first shift register unit 311 and the valid pulse of the gate drive signal G3 output by the third shift register unit 313 can be shifted successively, and compared with the valid pulse of the gate drive signal G1, the valid pulse of the gate drive signal G3 can have a shift amount greater than or equal to the width of the valid pulse of an output control signal CKB (ckb1 or ckb2). Similarly, when the time period of the valid pulse of an output control signal ckb2 received by the second shift register unit 312 does not overlap the time period of the valid pulse of an output control signal ckb4 received by the fourth shift register unit 314, the valid pulse of the gate drive signal G2 output by the second shift register unit 312 and the valid pulse of the gate drive signal G4 output by the fourth shift register unit 314 can be shifted successively, and compared with the valid pulse of the gate drive signal G2, the valid pulse of the gate drive signal G4 can have a shift amount greater than or equal to the width of the valid pulse of an output control signal CKB (ckb2 or ckb4). In this way, the time periods of valid pulses of output control signals CKB received by the two cascaded shift register units do not overlap so that valid pulses of gate drive signals G output by the two cascaded shift register units can be ensured to be shifted successively and have a shift amount greater than or equal to the time period of the valid pulse of the output control signal CKB. In this way, when the width of the valid pulse of the output control signal CKB is equal to the width of the valid pulse of the gate drive signal G, the valid pulses of the gate drive signals G output by the two cascaded shift register units have a shift amount greater than the width of the valid pulse of the gate drive signal G so that the valid pulses of the gate drive signals G output by the two cascaded shift register units cannot overlap, and the valid pulses of the gate drive signals G output by the two cascaded shift register units can be ensured to not affect each other, thereby facilitating the improvement of the accuracy of the gate drive signals G output by the shift register units.
Exemplarily, using the structure of the each shift register unit as shown in
Before the time period T01, the start signal STV1 is at an invalid level so that a latch module 310A of the first shift register unit 311 can latch the invalid level of the start signal STV1; the shift output terminal Next of the first shift register unit 311 outputs the invalid level of the shift signal Vnext1, and the each drive output terminal OUT of the first shift register unit 311 outputs the invalid level of the gate drive signal G1 so that the third shift register unit 313 cascaded with the first shift register unit 311 can output the invalid level of the shift signal Vnext3 and the invalid level of the gate drive signal G3. Similarly, before the time period T01, the start signal STV2 is also at an invalid level so that a latch module 310A of the second shift register unit 312 can latch the invalid level of the start signal STV2; the shift output terminal Next of the second shift register unit 312 outputs the invalid level of the shift signal Vnext2, and the each drive output terminal OUT of the second shift register unit 312 outputs the invalid level of the gate drive signal G2 so that the fourth shift register unit 314 cascaded with the second shift register unit 312 can output the invalid level of the shift signal Vnext4 and the invalid level of the gate drive signal G4.
At the time T0, the start signal STV1 hops to be at a valid level, and the latch module 310A of the first shift register unit 311 latches the start signal STV1, but since the clock signal cka1 received by the clock signal terminal A of the first shift register unit 311 is at an invalid level at the time period, the shift signal Vnext1 output by the shift output terminal Next of the first shift register unit 311 can remain at an invalid level; and the start signal STV2 still remains at an invalid level so that the second shift register unit 312 can remain at the state before the moment T01.
In the stage T1, the start signal STV1 remains at the valid level, the clock signal cka1 received by the clock signal terminal A of the first shift register unit 311 hops to be at a valid level, the first shift register unit 311 starts to output the valid level of the shift signal Vnext1, and the valid level of the shift signal Vnext1 is supplied to each level conversion module 320A of the first shift register unit 311 and the first input terminal IN1 of the third shift register unit 313 separately; since the output control signal ckb1 received by the each output control terminal B of the first shift register unit 311 is at an invalid level at the time period, after the gate drive signal G1 output by the each level conversion module 320A of the first shift register unit 311 is supplied to a respective drive output terminal OUT after undergoing level conversion by a respective output module 330A, the respective drive output terminal OUT of the first shift register unit 311 outputs the invalid level of the gate drive signal G1 to the respective scan line 20 electrically connected to the first shift register unit 311; meanwhile, the third shift register unit 313 latches the valid level of the shift signal Vnext1 received by the first input terminal IN1 of the third shift register unit 313, but since the clock signal cka3 received by the clock signal terminal A of the third shift register unit 313 is at an invalid level, the shift signal Vnext3 output by the shift signal terminal Next of the third shift register unit 313 can remain at an infective level so that the each drive output terminal OUT of the third shift register unit 313 can output the invalid level of the gate drive signal G3; additionally, since at least one of the start signal STV2 or the clock signal cka2 that is received by the second shift register unit 312 is at an invalid level in the stage T1, the second shift register unit 312 can continue outputting the invalid level of the shift signal Vnext2 and the invalid level of the gate drive signal G2 so that the fourth shift register unit 314 cascaded with the second shift register unit 312 can also continue outputting the invalid level of the shift signal Vnext4 and the invalid level of the gate drive signal G4.
In the stage T2, the clock signal cka1 and the start signal STV1 that are received by the first shift register unit 311 continue remaining at the valid levels, and the output control signal ckb1 received by the first shift register unit 311 continues remaining at the invalid level so that the shift output terminal Next of the first shift register unit 311 can continue outputting the valid level of the shift signal Vnext1, and the each drive output terminal OUT of the first shift register unit 311 can continue outputting the invalid level of the gate drive signal G1; accordingly, the clock signal cka3 received by the clock signal terminal A of the third shift register unit 313 cascaded with the first shift register unit 311 continues remaining at the invalid level so that the third shift register unit 313 can continue outputting the invalid levels of the shift signal Vnext3 and the gate drive signal G3; meanwhile, in the stage T2, the start signal STV2 is at a valid level so that the latch module 310A of the second shift register unit 312 can start to latch the valid level of the start signal STV2, and since the clock signal cka2 received by the clock signal terminal A of the second shift register unit 312 is at a valid level at the time period, the second shift register unit 312 can start to output the valid level of the shift signal Vnext2, and the valid level of the shift signal Vnext2 is supplied to each level conversion module 320A of the second shift register unit 312 and the first input terminal IN1 of the fourth shift register unit 314 separately; however, since the output control signal ckb2 received by the each output control terminal B of the second shift register unit 312 is at an invalid level, after the gate drive signal G2 output by the each level conversion module 320A of the second shift register unit 312 is supplied to a respective drive output terminal OUT after undergoing polarity conversion by a respective output module 330A, and the respective drive output terminal OUT of the second shift register unit 312 can output the invalid level of the gate drive signal G2 to the respective scan line 20 electrically connected to the second shift register unit 312; the fourth shift register unit 314 latches the valid level of the shift signal Vnext2 received by the first input terminal IN1 of the fourth shift register unit 314, but since the clock signal cka4 received by the clock signal terminal A of the fourth shift register unit 314 is at an invalid level, the shift signal Vnext4 output by the shift signal terminal Next of the fourth shift register unit 314 can remain at an invalid level so that the each drive output terminal OUT of the fourth shift register unit 314 can output the invalid level of the gate drive signal G4.
In the stage T3, the clock signal cka1 received by the first shift register unit 311 hops to be at an invalid level, the output control signal ckb1 received by the first shift register unit 311 hops to be at a valid level, and the shift output terminal Next of the first shift register unit 311 continues outputting the valid level of the shift signal Vnext1 so that the each level conversion module 320A of the first shift register unit 311 can supply the low level of the gate drive signal G1 to the respective output module 330A of the first shift register unit 311 under the control of the valid level of the shift signal Vnext1 and the valid level of the output control signal ckb1, and the low-level gate drive signal G1 is output by the respective drive output terminal OUT after undergoing polarity conversion by the respective output module 330A so that the respective scan line 20 electrically connected to the first shift register unit 311 can transmit the valid level of the gate drive signal G1 to the gates of the switch transistors in the first row of pixels to charge the gates of the switch transistors in the first row of pixels; the start signal STV2 and the clock signal cka2 that are received by the second shift register unit 312 are at valid levels so that the second shift register unit 312 can continue outputting the valid level of the shift signal Vnext2, but since the output control signal ckb2 of the each output control terminal B of the second shift register unit 312 is still at the invalid level, the second shift register unit 312 can continue outputting the invalid level of the gate drive signal G2; accordingly, since the clock signal cka3 of the third shift register unit 313 hops to be at the valid level, the third shift register unit 313 can start to output the valid level of the shift signal Vnext3, and the output control signal ckb3 of the third shift register unit 313 is at the invalid level at this time period so that the each drive output terminal OUT of the third shift register unit 313 can continue outputting the invalid level of the gate drive signal G3; meanwhile, under the control of the invalid level of the clock signal cka4 received by the fourth shift register unit 314, the fourth shift register unit 314 continues outputting the invalid level of the shift signal Vnext4 so that the each drive output terminal OUT of the fourth shift register unit 314 can continue outputting the invalid level of the gate drive signal G4.
In the time period T4, the clock signal cka1 received by the first shift register unit 311 continues remaining at the invalid level, the output control signal ckb1 received by the first shift register unit 311 continues remaining at the valid level, and the shift output terminal Next of the first shift register unit 311 continues outputting the valid level of the shift signal Vnext1 so that the each level conversion module 320A of the first shift register unit 311 can continue supplying the valid level of the gate drive signal G1 to the respective scan line 20 electrically connected to the respective drive output terminal OUT of the first shift register unit 311, and so that the gates of the switch transistors in the first row of pixels electrically connected to the respective scan line 20 can continue being charged to enable the gates of the switch transistors in the first row of pixels to be charged until the normal conduction condition is satisfied, thereby enabling a respective signal to be accurately written into the first row of pixels through the switch transistors; the clock signal cka2 received by the second shift register unit 312 hops to be at the invalid level, and the output control signal ckb2 received by the second shift register unit 312 hops to be at the valid level so that the second shift register unit 312 can start to output the valid level of the gate drive signal G2 while continuing outputting the valid level of the shift signal Vnext2, and the valid level of the gate drive signal G2 can be transmitted to the gates of the switch transistors in the second row of pixels through the respective scan line to charge the gates of the switch transistors in the second row of pixels; the clock signal cka3 received by the clock signal terminal A of the third shift register unit 313 continues remaining at the valid level, and the output control signal ckb3 of the each output control terminal B of the third shift register unit 313 continues remaining at the invalid level so that the third shift register unit 313 can continue outputting the valid level of the shift signal Vnext3 and the invalid level of the gate drive signal G3; meanwhile, since the clock signal cka4 received by the clock signal terminal A of the fourth shift register unit 314 hops to be at the valid level, the shift signal terminal Next of the fourth shift register unit 314 can start to output the valid level of the shift signal Vnext4, but since the output control signal ckb4 of the each output control terminal B of the fourth shift register unit 314 is at the invalid level, the each drive output terminal OUT of the fourth shift register unit 314 can continue outputting the invalid level of the gate drive signal G4.
In the time period T5, the clock signal cka1 received by the first shift register unit 311 hops to be at the valid level, and the output control signal ckb1 received by the first shift register unit 311 hops to be at the invalid level so that the shift output terminal Next of the first shift register unit 311 can start to output the invalid level of the shift signal Vnext1, and meanwhile, the each drive output terminal OUT of the first shift register unit 311 starts to output the invalid level of the gate drive signal G1 to the respective scan line 20 to control the switch transistors electrically connected to the respective scan line 20 to be in an off state, and the writing of the respective signal into the first row of pixels electrically connected to the respective scan line 20 is stopped so that the signal in the first row of pixels can remain as the signal written in the previous stage; at this time period, the clock signal cka2 received by the second shift register unit 312 continues remaining at the invalid level, and the output control signal ckb2 received by the second shift register unit 312 continues remaining at the valid level so that the second shift register unit 312 can continue outputting the valid levels of the shift signal Vnext2 and the gate drive signal G2, and the valid level of the gate drive signal G2 can continue charging the gates of the switch transistors in the second row of pixels so that the gates of the switch transistors in the second row of pixels can be charged until the normal conduction condition is satisfied, and so that a respective signal can be written into the second row of pixels through the switch transistors in the second row of pixels; accordingly, the clock signal cka3 received by the clock signal terminal A of the third shift register unit 313 hops to be at the invalid level, and the output control signal ckb3 of the each output control terminal B of the third shift register unit 313 hops to be at the valid level so that the each output control terminal of the third shift register unit 313 can start to output the valid level of the gate drive signal G3 while the third shift register unit 313 continues outputting the valid level of the shift signal Vnext3, and the valid level of the gate drive signal G3 can be transmitted to the gates of the switch transistors in the third row of pixels through the respective scan line 20 to charge the gates of the switch transistors in the third row of pixels; additionally, the clock signal cka4 of the clock signal terminal A of the fourth shift register unit 314 continues remaining at the valid level, and the output control signal ckb4 of the each output control terminal B of the fourth shift register unit 314 continues remaining at the invalid level so that the fourth shift register unit 314 can continue outputting the valid level of the shift signal Vnext4 and the invalid level of the gate drive signal G4.
In the time period T6, the clock signal cka1 received by the first shift register unit 311 continues remaining at the valid level, and the output control signal ckb1 received by the first shift register unit 311 continues remaining at the invalid level so that the first shift register unit 311 can continue outputting the invalid levels of the shift signal Vnext1 and the gate drive signal G1; meanwhile, the clock signal cka2 of the second shift register unit 312 hops to be at the valid level, and the output control signal ckb2 of the second shift register unit 312 hops to be at the invalid level so that the second shift register unit 312 can start to output the invalid levels of the shift signal Vnext2 and the gate drive signal G2, and the invalid level of the gate drive signal G2 can charge the gates of the switch transistors in the second row of pixels to control the switch transistors in the second row of pixels to be in an off state, and the writing of the respective signal into the second row of pixels is stopped so that the signal in the second row of pixels can remain as the signal written in the previous stage; at this time period, the clock signal cka3 of the third shift register unit 313 continues remaining at the invalid level, and the output control signal ckb3 of the third shift register unit 313 continues remaining at the valid level so that the third shift register unit 313 can continue outputting the valid levels of the shift signal Vnext3 and the gate drive signal G3, and so that the valid level of the gate drive signal G3 can continue charging the gates of the switch transistors in the third row of pixels to enable the switch transistors in the third row of pixels to be in a normal on state and the respective signal to be accurately written into the third row of pixels through the turned-on switch transistors; additionally, the clock signal cka4 of the fourth shift register unit 314 hops to be at the invalid level, and the output control signal ckb4 of the fourth shift register unit 314 hops to be at the valid level so that the each drive output terminal OUT of the fourth shift register unit 314 can start to output the valid level of the gate drive signal G4 while the fourth shift register unit 314 continues outputting the valid level of the shift signal Vnext4, and the valid level of the gate drive signal G4 can be transmitted to the gates of the switch transistors in the fourth row of pixels through the respective scan line 20 to charge the gates of the switch transistors in the fourth row of pixels.
In the time period T7, since the start signals STV1 and STV2 continue remaining at the invalid levels, the first shift register unit 311 continues outputting the invalid levels of the shift signal Vnext1 and the gate drive signal G1, and the second shift register unit 312 also outputs the invalid levels of the shift signal Vnext2 and the gate drive signal G2; the clock signal cka3 received by the third shift register unit 313 hops to be at the valid level, and the output control signal ckb3 received by the third shift register unit 313 hops to be at the invalid level so that the third shift register unit 313 can start to output the invalid levels of the shift signal Vnext3 and the gate drive signal G3, and the invalid level of the gate drive signal G3 can be transmitted to the switch transistors in the third row of pixels through the respective scan line 20 to enable the switch transistors in the third row of pixels to be in an off state, and the writing of the respective signal into the third row of pixels is stopped so that the signal in the third row of pixels can remain as the signal written in the previous stage; at this time period, the clock signal cka4 of the fourth shift register unit 314 continues remaining at the invalid level, and the output control signal ckb4 of the fourth shift register unit 314 continues remaining at the valid level so that the fourth shift register unit 314 can continue outputting the valid levels of the shift signal Vnext4 and the gate drive signal G4, and the valid level of the gate drive signal G4 can continue charging the gates of the switch transistors in the fourth row of pixels so that the switch transistors in the fourth row of pixels can be in a normal on state to enable a respective signal to be accurately written into the fourth row of pixels through the turned-on switch transistors.
In the stage T8, the shift signal Vnext1 and the gate drive signal G1 that are output by the first shift register unit 311, the shift signal Vnext2 and the gate drive signal G2 that are output by the second shift register unit 312, and the shift signal Vnext3 and the gate drive signal G3 that are output by the third shift register unit 313 continue remaining at the invalid levels; at this time period, the clock signal cka4 of the fourth shift register unit 314 hops to be at the valid level so that the fourth shift register unit 314 can start to output the invalid level of the shift signal Vnext4, and meanwhile, the output control signal ckb4 of the fourth shift register unit 314 hops to be at the invalid level so that the fourth shift register unit 314 can start to output the invalid level of the gate drive signal G4, and the invalid level of the gate drive signal G4 is transmitted to the gates of the switch transistors in the fourth row of pixels through the respective scan line 20 to enable the switch transistors in the fourth row of pixels to be in an off state, and the writing of the respective signal into the fourth row of pixels is stopped so that the signal in the fourth row of pixels can remain as the signal written in the previous stage.
In this way, the shift signals Vnext output by the shift register units 31 are shifted successively, and the shift signals Vnext output by the two cascaded shift register units 31 have a shift amount equal to the widths of the valid pulses of the clock signals CKA received by the two cascaded shift register units 31; meanwhile, the gate drive signals G output by the shift register units 31 can also be shifted successively, and the valid pulses of the gate drive signals G output by the two cascaded shift register units 31 do not overlap. Consequently, on the premise that the switch transistors in the rows of pixels are ensured to be turned on normally, the accuracy of the signals written into the rows of pixels can also be ensured so that the accuracy of the display light emission of the rows of pixels can be improved, thereby improving the display effect of the display panel.
It is to be understood that, as shown in
Optionally, with continued reference to
In an embodiment, since the clock signals CKA of the n shift register units 31 can control the time periods of valid pulses of shift signals Vnext output by shift output terminals Next of the n shift register units 31, and the output control signals CKB of the n shift register units 31 can control the time periods of valid pulses of gate drive signals G output by drive output terminals OUT of the n shift register units 31, the clock signals CKA received by the n shift register units 31 in the same one shift register unit group 301 are shifted successively so that the shift signals Vnext output by the n shift register units 31 in the same one shift register unit group 301 can be shifted successively, and the output control signals CKB received by the n shift register units 31 in the same one shift register unit group 301 are shifted successively so that the gate drive signals G output by the n shift register units 31 in the same one shift register unit group 301 can be shifted successively. Consequently, when the gate drive signals G output by the shift register units 31 are transmitted to the gates of the switch transistors in the rows of pixels through the multiple scan lines 20 respectively, the rows of pixels can be scanned row by row so that the switch transistors in the rows of pixels can be turned on row by row, data signals transmitted by the multiple data lines can be written into the rows of pixels in a time-sharing manner, the accuracy of the data signals written into the rows of pixels can be ensured, and the display effect of the display panel can be improved.
In an optional embodiment, in two adjacent shift register unit groups 301, n shift register units 31 in the previous shift register unit group are cascaded with n shift register units 31 in the next shift register unit group respectively, for example, the first shift register unit 311 in the shift register unit group 3011 is cascaded with the third shift register unit 313 in the shift register unit group 3012, and the second shift register unit 312 in the shift register unit group 3011 is cascaded with the fourth shift register unit 314 in the shift register unit group 3012. In this case, clock signals CKA received by the shift register units 31 in the two adjacent shift register unit groups 301 are shifted successively, for example, the control signal CK1 may also serve as the clock signal CKA of the first shift register unit 311, the control signal CK2 may also serve as the cock signal CKA of the second shift register unit 312, the control signal CK3 may also serve as the clock signal CKA of the third shift register unit 313, and the control signal CK4 may also serve as the clock signal CKA of the fourth shift register unit 314, and the control signals CK1, CK2, CK3 and CK4 are shifted successively within one clock cycle t10. Similarly, output control signals CKB received by the 2n shift register units 31 in the two adjacent shift register unit groups 301 are also shifted successively, for example, the control signal CK3 may also serve as the output control signal CKB of the first shift register unit 311, the control signal CK4 may also serve as the output control signal CKB of the second shift register unit 312, the control signal CK1 may also serve as the output control signal CKB of the third shift register unit 313, and the control signal CK2 may also serve as the output control signal CKB of the fourth shift register unit 314.
Optionally, with continued reference to
In an embodiment, the gate drive signals G output by the two adjacent shift register units 31 control switch transistors in two adjacent two rows of pixels to turn on or off respectively, for example, the i-th shift register unit 31i can control switch transistors in the i-th row of pixels to turn on or off, and the (i+1)-th shift register unit 31(i+1) can control switch transistors in the (i+1)-th row of pixels to turn on or off. In this case, in the period of the valid pulse of the gate drive signal Gi output by the i-th shift register unit 31i, the (i+1)-th shift register unit 31(i+1) also outputs the valid pulse of the gate drive signal G(i+1), and the time period for the i-th shift register unit 31i and the (i+1)-th shift register unit 31(i+1) to output the gate drive signals G (Gi and G(i+1)) simultaneously is denoted as k*Th. In this time period, the gate drive signal Gi output by the i-th shift register unit 31i can control the switch transistors in the i-th row of pixels to be in a normal on state to write data signals and other signals of the i-th row of pixels into the i-th row of pixels in a one-to-one correspondence, and the gate drive signal G(i+1) output by the (i+1)-th shift register unit 31(i+1) can pre-charge the gates of the switch transistors in the (i+1)-th row of pixels so that the switch transistors in the (i+1)-th row of pixels can tend to be in an on state. Meanwhile, when the gate drive signal Gi output by the i-th shift register unit 31i hops to be at the invalid level, the gate drive signal G(i+1) of the (i+1)-th shift register unit 31(i+1) can continue remaining at the valid level, and the hold time period of the valid level is denoted as Th. Since the switch transistors in the (i+1)-th row of pixels have tended to be in an on state, the valid level of the gate drive signal G(i+1) can continue being supplied to the gates of the switch transistors in the (i+1)-th row of pixels so that the switch transistors in the (i+1)-th row of pixels can turn to be in an on state quickly. In this case, data signals and other signals can be supplied to the (i+1)-th row of pixels so that the data signal can be written into the (i+1)-th row of pixels, ensuring that the time period for writing the data signal can tend to remain consistent with the driving time period Th of a row of pixels. In this way, the valid pulses of the gate drive signals G output by the two adjacent shift register units 31 have an overlapping time period equal to k*Th so that the valid pulses of the gate drive signals G output by the two adjacent shift register units 31 can have a shift amount denoted as Th. Consequently, the time period for writing data signals and other signals into the rows of pixels can be sufficiently long so that the accuracy of the data signals and other signals that are written into the rows of pixels can be ensured, thereby improving the accuracy of the display light emission of the rows of pixels and facilitating the improvement of the display effect of the display panel.
Optionally, with continued reference to
Optionally, with continued reference to
The output control signals CKB received by the n shift register units 31 are used for controlling the time periods of the valid pulses of the gate drive signals G output by the drive output terminals OUT of the n shift register units 31, and in the same one shift register unit 31, the time period of the valid pulse of the output control signal CKB generally overlaps the time period of the valid pulse of the gate drive signal G, so when the time periods of the valid pulses of the output control signals CKB of the n shift register units 31 in the same one shift register unit group 301 overlap, the time periods of the valid pulses of the gate drive signals G output by the n shift register units 31 in the same one shift register unit group 301 can overlap so that the sufficient lengths of the time periods of the valid pulses of the gate drive signals G output by the n shift register units 31 can be ensured, and so that the gates of the switch transistors in the rows of pixels can have a sufficiently long charging time period, ensuring that data signals in the rows of pixels can be written into respective nodes accurately through respective switch transistors. Consequently, when the rows of pixels display light emission according to the written data signals, the accuracy of the display light emission of the rows of pixels can be improved, thereby facilitating the improvement of the display effect of the display panel.
Optionally, the clock signal supplied to the i-th shift register unit also serves as a clock signal supplied to the (i+2*n)-th shift register unit; and the output control signal supplied to the i-th shift register unit also serves as an output control signal supplied to the (i+2*n)-th shift register unit.
Exemplarily, using n=2 as an example,
Accordingly, the output control signal CK3 of the first shift register unit 311 may also serve as an output control signal of the fifth shift register unit 315, the output control signal CK4 of the second shift register unit 312 may also serve as an output control signal of the sixth shift register unit 316, the output control signal CK1 of the third shift register unit 313 may also serve as an output control signal of the seventh shift register unit 317, and the output control signal CK2 of the fourth shift register unit 314 may also serve as an output control signal of the eighth shift register unit 318. In this way, on the premise that the gate drive signals G output by the shift register units 31 are ensured to be shifted successively, the number of output control signals supplied to the driver circuit can be reduced so that the number of signal lines for transmitting the output control signals can be reduced, thereby facilitating the reduction in the size of the non-display region and the narrow bezel of the display panel.
It is to be noted that the embodiment of the present application is illustrated using the preceding example in which the each shift register unit includes the latch module, the at least one level conversion module, the at least one output module and the reset module, and the structure of the each shift register unit in the embodiments of the present application is not limited herein.
In an optional embodiment,
Exemplarily, as shown in
Optionally,
The reset module 330B is electrically connected to the first reset terminal C, the first control module 310B and the second control module 320B and is electrically connected to the first control module 310B and the second control module 320B at a first node N1. The reset module 330B is configured to control a signal of the first node N1 in response to a first reset signal CKC of the first reset terminal C. The first reset signal CKC may be a pulse signal including a high level and a low level. The valid level of the first reset signal CKC may be the first reset signal CKC at the high level or the low level. In this way, when the first reset signal CKC is at a valid level, the reset module 330B may control the signal of the first node N1 to be at a valid level, and when the first reset signal CKC is at an invalid level, the reset module 330B may control the signal of the first node N1 to be at an invalid level.
In an exemplary embodiment,
With continued reference to
In an exemplary embodiment, with continued reference to
With continued reference to
In an exemplary embodiment, with continued reference to
With continued reference to
In an exemplary embodiment, with continued reference to
In an optional embodiment,
In an embodiment, since the first input signal Vin1 is a gate drive signal output by another shift register unit cascaded with the current shift register unit 31, when the first input signal Vin1 is at the valid level, the clock signal CKA may be at the valid level so that the valid level of the first input signal Vin1 can be transmitted to the second node N2 through the first control module 310B. In this case, the signal of the second node N2 can control the each output module 340B to transmit the output control signal CKB to the respective drive output terminal OUT so that the gate drive signal output by the respective drive output terminal OUT can remain consistent with the output control signal CKB. To ensure that the valid pulses of the gate drive signals G output by the two cascaded shift register units 31 do not overlap, the output control signal CKB should be at the invalid level at this time period, that is, in the period when the clock signal CKA is at the valid level, the output control signal CKB is at the invalid level. When the first input signal Vin1 hops to be at the invalid level, the clock signal CKA may also be at the invalid level. At this time period, if a new signal is not written into the second node N2, the signal of the second node N2 remains at the valid level so that the signal of the second node N2 can continue controlling the each output module 340B to transmit the output control signal CKB to the respective drive output terminal OUT, and so that the gate drive signal G of the respective drive output terminal OUT can continue remaining consistent with the output control signal CKB. In this case, if the output control signal CKB hops to be at the valid level, the gate drive signal G of the respective drive output terminal OUT is also at the valid level. After the output control signal CKB hops to be at the invalid level, the respective drive output terminal OUT may also hop to be at the invalid level. At this time period, the first reset signal CKC of the first reset terminal C may control the reset module 330B to hop the signal of the first node N1 to be at the valid level so that the invalid level of the first input signal Vin1 can be transmitted to the second node N2, and the second voltage signal Vgh of the second voltage terminal V2 is transmitted to the third node N3 through the second control module 320B so that the third node N3 can be at the valid level, and the each output module 340B transmits the first voltage signal Vgl to the respective drive output terminal OUT under the control of the valid level of the third node N3 so that the respective drive output terminal OUT can output the invalid level of the gate drive signal. In this way, the valid pulses of the clock signal CKA, the output control signal CKB and the first reset signal CKC are shifted successively so that the cascaded shift register units 31 can output the valid pulses of the gate drive signals G successively, thereby ensuring the accuracy of the gate drive signals output by the shift register units 31.
In an optional embodiment, with continued reference to
In an exemplary embodiment, the node mutual control module 350B may include a first mutual control transistor M51 and a second mutual control transistor M52. A gate of the first mutual control transistor M51 is electrically connected to the first input terminal IN1, a first electrode of the first mutual control transistor M51 is electrically connected to the first voltage terminal V1, and a second electrode of the first mutual control transistor M51 is electrically connected to the third node N3 so that the first input signal Vin1 of the first input terminal IN1 can control the first mutual control transistor M51 to turn on or off, and when the first mutual control transistor M51 is turned on, the first voltage signal Vgl of the first voltage terminal V1 can be transmitted to the third node N3 so that the third node N3 can be at the invalid level. A gate of the second mutual control transistor M52 is electrically connected to the third node N3, a first electrode of the second mutual control transistor M52 is electrically connected to the first voltage terminal V1, and a second electrode of the second mutual control transistor M52 is electrically connected to the second node N2 so that the signal of the third node N3 can control the second mutual control transistor M52 to turn on or off, and when the second mutual control transistor M52 is turned on, the first voltage signal Vgl of the first voltage terminal V1 can be transmitted to the second node N2 so that the second node N2 can be at the invalid level. The first mutual control transistor M51 and the second mutual control transistor M52 may be n-type transistors or p-type transistors. This may be disposed according to actual requirements and is not specifically limited in the embodiments of the present application.
Optionally, the each shift register unit 31 may further include a storage capacitance C2. The storage capacitance C2 is electrically connected between the first voltage terminal V1 and the third node N3 to store the signal of the third node N3 and maintain the voltage of the third node N3 so that the voltage of the third node N3 can control the each output module 340B to accurately output the respective gate drive signal.
Optionally, the each shift register unit 31 may further include a bootstrap capacitance C1. The bootstrap capacitance C1 is electrically connected between the each drive output terminal OUT and the second node N2 to control the second node N2 to have the same hopping amount when the each drive output terminal OUT hops so that the signal of the second node N2 can control the first output transistor M41 in the each output module 340B to accurately turn on or off.
Optionally, the second node N2 may include a first sub-node N21 and a second sub-node N22. In this case, the each shift register unit 31 may further include a voltage regulation transistor M60. A gate of the voltage regulation transistor M60 receives a fixed signal such as the second voltage signal Vgh that can control the voltage regulation transistor M60 to be in a normal on state. A first electrode of the voltage regulation transistor M60 may be electrically connected to the first control module 310B at the first sub-node N21 and may be electrically connected to the each output module 340B at the second sub-node N22. The voltage regulation transistor M60 may stabilize the voltages of the first sub-node N21 and the second sub-node N22 to prevent the accuracy of a respective gate drive signal output by the each drive output terminal OUT from being affected by the unstable voltages of the first sub-node N21 and the second sub-node N22.
Optionally, when the each shift register unit includes the clock signal terminal, the at least one output control terminal and the first reset terminal, on the premise that the clock signal, the output control signal and a first reset signal that are received by the same one shift register unit are ensured to be shifted successively, the clock signals, the output control signals and first reset signals of the shift register units may be mutually multiplexed. For example, as shown in
In an optional embodiment,
In an optional embodiment, with continued reference to
In an optional embodiment, with continued reference to
It is to be understood that the driving process of the driver circuit in the embodiments of the present application is merely illustrated using the preceding example of the structures of two shift register units, and the structure of the each shift register unit is not limited in the embodiments of the present application, and on the premise that the core application points of the embodiments of the present application can be achieved, the specific structure of the each shift register unit is not limited in the embodiments of the present application.
It is to be noted that the structure and driving process of the driver circuit are illustrated using the preceding example in which the each shift register unit includes one drive output terminal and one output control terminal corresponding to the drive output terminal, and in the embodiments of the present application, the each shift register unit may be provided with one or more drive output terminals, and the each shift register unit may also be provided with one or more output control terminals accordingly, and in the same one shift register unit, the number of drive output terminals may be the same as the number of output control terminals so that the output control terminals can control gate drive signals output by the drive output terminals in a one-to-one correspondence.
Optionally, when the each shift register unit includes m drive output terminals, in the same one shift register unit, valid pulses of gate drive signals output by m drive output terminals are shifted successively; m is a positive integer greater than or equal to 2; in the same one shift register unit, the j-th drive output terminal outputs a j-th valid pulse of a gate drive signal; j is a positive integer less than or equal to m; and in the same one shift register unit, the valid pulse of the gate drive signal output by the j-th drive output terminal and the valid pulse of a gate drive signal output by the (j+1)-th drive output terminal have an overlapping time period denoted as k*Th.
Exemplarily, when the m drive output terminals also serve as m shift output terminals in the same one shift register unit,
Meanwhile, when the each shift register unit 31 includes the clock signal terminal A and the two output control terminals B1 and B2, three control signals need to be supplied to the each shift register unit 31. For example, in the first shift register unit 311, the clock signal terminal A receives a clock signal CK1, an output control terminal B1 receives an output control signal CK3, and an output control terminal B2 receives an output control signal CK4. In this case, valid pulses of the clock signal CK1, the output control signal CK3 and the output control signal CK4 in the first shift register unit 311 are shifted successively, and the time period of the valid pulse of the clock signal CK1 does not overlap the time periods of the valid pulses of the output control signal CK3 and the output control signal CK4. The shift situations of valid pulses of control signals received by other shift register units 31 are similar to the shift situation of the valid pulses of the control signals received by the first shift register unit 311, and details are not repeated herein.
It is to be understood that when the each shift register unit includes the clock signal terminal and the two output control terminals, the clock signals and the output control signals that are received by the shift register units may also be multiplexed between each other to reduce the number of control signals supplied to the driver circuit. For example, referring to
Accordingly, as shown in
Optionally, when the drive output terminal also serves as the shift output terminal in the same one shift register unit, in the same one shift register unit including the m drive output terminals, the j-th drive output terminal outputs a j-th valid pulse of a gate drive signal; m is a positive integer, and j is a positive integer less than or equal to m; and in the same one shift register unit, the m-th drive output terminal also serves as the shift output terminal.
Exemplarily,
Meanwhile, when the each shift register unit 31 includes the clock signal terminal A, the two output control terminals B1 and B2 and the first reset terminal C, four control signals need to be supplied to the each shift register unit 31. For example, in the first shift register unit 311, the clock signal terminal A receives the clock signal CK1, the output control terminal B1 receives an output control signal CK8, the output control terminal B2 receives an output control signal CK9, and the first reset terminal C receives the first reset signal CK11. In this case, valid pulses of the clock signal CK1, the output control signal CK8, the output control signal CK9 and the first reset signal CK11 in the first shift register unit 311 are shifted successively, the time period of the valid pulse of the clock signal CK1 does not overlap the time periods of the valid pulses of the output control signal CK8 and the output control signal CK9, and the time period of the valid pulse of the first reset signal CK11 does not overlap the time periods of the valid pulses of the output control signal CK8 and the output control signal CK9. The shift situations of valid pulses of control signals received by other shift register units 31 are similar to the shift situation of the valid pulses of the control signals received by the first shift register unit 311, and details are not repeated herein.
It is to be understood that when the each shift register unit includes the clock signal terminal, the two output control terminals and the first reset terminal, the clock signals, the output control signals and the first reset signals that are received by the shift register units may also be multiplexed between each other to reduce the number of control signals supplied to the driver circuit. For example, referring to
Accordingly, as shown in
It is to be noted that the technical solutions of the embodiments of the present application are merely illustrated using the preceding example in which the each shift register unit including the two drive output terminals is described using the structures of two shift register units, and in the embodiments of the present application, the number of drive output terminals in the each shift register unit may be disposed according to actual requirements. In this case, the number of drive output terminals in the each shift register unit may be equal to n, greater than n, or less than n, and this is not specifically limited in the embodiments of the present application.
Optionally, the valid pulse of a gate drive signal output by the m-th drive output terminal in the i-th shift register unit and the valid pulse of a gate drive signal output by the first drive output terminal in the (i+1)-th shift register unit have an overlapping time period denote as k*Th. In this case, compared with the valid pulse of the gate drive signal output by the m-th drive output terminal in the i-th shift register unit, the valid pulse of the gate drive signal output by the first drive output terminal in the (i+1)-th shift register unit has a shift amount denoted as Th so that the time period for writing a signal into pixels electrically connected to the first drive output terminal in the (i+1)-th shift register unit can be ensured to tend to remain consistent with the driving time period Th of a row of pixels, and so that the time period for writing signals into the rows of pixels can be sufficiently long, thereby ensuring the accuracy of the data signals and other signals that are written into the rows of pixels, further improving the accuracy of the display light emission of the rows of pixels and facilitating the improvement of the display effect of the display panel.
Optionally, when m≤n, the time periods of the valid pulses of the gate drive signals output by the m drive output terminals in the same one shift register unit overlap. In this case, the time periods of the valid pulses of the gate drive signals output by the m drive output terminals in the same one shift register unit may be greater than or equal to m*Th so that on the premise that the accuracy of the gate drive signals output by the shift register units is ensured, the valid pulses of the gate drive signals output by the shift register units can have a sufficiently long time period. Consequently, when the gate drive signals output by the shift register units are used for controlling the switch transistors in the rows of pixels to turn on or off, the switch transistors in the rows of pixels can have a sufficiently long conduction time period so that the respective signals can be written into the rows of pixels accurately.
Optionally, the time periods of valid pulses of output control signals received by the same one shift register unit overlap.
The output control signals received by the output control terminals of the shift register units control the time periods of the valid pulses of the gate drive signals output by the drive output terminals of the shift register units respectively. In this way, the time periods of the valid pulses of the output control signals received by the same one shift register unit overlap so that the time periods of the valid pulses of the gate drive signals output by the m drive output terminals in the same one shift register unit can overlap, thereby ensuring the sufficient lengths of the time periods of the valid pulses of the gate drive signals output by the m drive output terminals, and so that the gates of the switch transistors M0 in the rows of pixels 10 can have a sufficiently long charging time period, ensuring that all the switch transistors M0 in the rows of pixels 10 can be in a normal on state. Consequently, through the turned-on switch transistors M0, the data signals can be accurately written into the rows of pixels 10 to which the switch transistors M0 belong so that when the rows of pixels 10 perform light emission for display according to the written data signals, the accuracy of the display light emission of the rows of pixels 10 can be improved, facilitating the improvement of the overall display effect of the display panel 100.
Optionally, when m>n, the time periods of valid pulses of gate drive signals output from the first drive output terminal to the n-th drive output terminal in the same one shift register unit overlap; and in the same one shift register unit, the time period of the valid pulse of the gate drive signal output by the first drive output terminal does not overlap the time period of the valid pulse of a gate drive signal output by the (n+1)-th drive output terminal. In this way, the time periods of the valid pulses of the gate drive signals output by the drive output terminals may be less than or equal to n*Th so that on the premise that the sufficient lengths of the gate drive signals output by the shift register units are ensured, the valid pulses of the gate drive signals output by the drive output terminals can be shifted successively, and so that the gate drive signals output by the drive output terminals can successively control the switch transistors in the rows of pixels to turn on respectively. Consequently, the data signals transmitted by the multiple data lines can be written into the rows of pixels respectively, and the rows of pixels can be ensured to accurately perform light emission for display according to the written data signals so that the improvement of the overall display effect of the display panel can be facilitated.
Optionally, when an output control terminal corresponding to the j-th drive output terminal is the j-th output control terminal in the same one shift register unit, the time periods of valid pulses of output control signals received from the first output control terminal to the n-th output control terminal in the same one shift register unit overlap; and in the same one shift register unit, the time period of the valid pulse of the output control signal received by the first output control terminal does not overlap the time period of the valid pulse of an output control signal received by the (n+1)-th output control terminal.
The output control signals received by the output control terminals of the shift register units control the time periods of the valid pulses of the gate drive signals output by the drive output terminals of the shift register units respectively, and the time periods of the valid pulses of the gate drive signals output by the drive output terminals generally overlap the time periods of valid pulses of output control signals of corresponding output control terminals, so the time periods of the valid pulses of the output control signals received from the first output control terminal to the n-th output control terminal in the same one shift register unit overlap so that the time periods of the valid pulses of the gate drive signals output from the first drive output terminal to the n-th drive output terminal in the same one shift register unit can overlap, and the time periods of valid pulses of output control signals received by the first output control terminal and the (n+1)-th output control terminal in the same one shift register unit do not overlap so that the time periods of valid pulses of gate drive signals output by the first drive output terminal and the (n+1)-th drive output terminal cannot overlap. Consequently, on the premise that the sufficient lengths of the time periods of the valid pulses of the gate drive signals output by the drive output terminals are ensured, the valid pulses of the gate drive signals output by the drive output terminals can be shifted successively, and the data signals transmitted by the multiple data lines can be written into the rows of pixels respectively so that the rows of pixels can be ensured to accurately perform light emission for display according to the written data signals, thereby facilitating the improvement of the overall display effect of the display panel. It is to be noted that the preceding is illustrated using an example in which the gate drive signals output from the first drive output terminal to the m-th drive output terminal in the same one shift register unit are shifted successively and the gate drive signals output by the drive output terminals of the shift register units are also shifted successively, that is, the start time period of the valid pulse of the gate drive signal output by the j-th drive output terminal is located before the start time period of the valid pulse of a gate drive signal output by the (j+1)-th drive output terminal, and the start time period of the valid pulse of a gate drive signal output by the m-th drive output terminal in the i-th shift register unit is located before the start time period of the valid pulse of a gate drive signal output by the first drive output terminal in the (i+1) shift register unit, and in this case, the gate drive signals output by the drive output terminals of the shift register units can control the switch transistors from the first row of pixels to the last row of pixels to successively turn on, that is, the gate drive signals output by the drive output terminals of the shift register units can forward scan the rows of pixels in the display panel. In other embodiments of the present application, the gate drive signals output by the shift register units can also backward scan the rows of pixels. In this case, the each shift register unit further includes a first scan control terminal and a second scan control terminal. A first scan control signal received by the first scan control terminal may be at a valid level when the forward scan is performed on the rows of pixels, and a second scan control signal received by the second scan control terminal may be at a valid level when the backward scan is performed on the rows of pixels. For ease of description, the technical solutions of the embodiments of the present application are illustrated below using an example in which the each shift register unit includes one drive output terminal.
Optionally,
Optionally,
In this way, the input module 350A is disposed in the each shift register unit 31 so that the signal supplied to the latch module 310A can be selected, avoiding the mutual influence between signals output by the cascaded shift register units 31, ensuring the accurate operation of the shift register units 31 and improving the accuracy of the gate drive signals output by the shift register units.
In an exemplary embodiment, with continued reference to
Each transmission gate (Tr1 and Tr2) may be composed of two different types of transistors. A gate of an n-type transistor of the transmission gate Tr1 may be electrically connected to the first scan control terminal U2D, and a gate of a p-type transistor of the transmission gate Tr1 may be electrically connected to the second scan control terminal D2U. A gate of an n-type transistor of the transmission gate Tr2 may be electrically connected to the second scan control terminal D2U, and a gate of a p-type transistor of the transmission gate Tr2 may be electrically connected to the first scan control terminal U2D.
In another optional embodiment,
It is to be understood that when the each shift register unit includes the m drive output terminals, on the premise that the gate drive signals output by the drive output terminals of the shift register units are shifted successively, any one drive output terminal in the (i+n)-th shift register unit may be electrically connected to the second input terminal of the i-th shift register unit. This is not specifically limited in the embodiments of the present application. In an optional embodiment, the second input terminal IN2 of the i-th shift register unit may be electrically connected to the m-th drive output terminal OUT of the (i+n)-th shift register unit.
Optionally,
In an embodiment, when the forward scan is performed on the rows of pixels, the valid level of the first scan control signal u2d can be controlled to supply to the first control module 310B when the first input signal Vin1 of the first input terminal IN1 is at the valid level, and the invalid level of the second scan control signal d2u can be controlled to supply to the first control module 310B when the second input signal Vin2 of the second input terminal IN2 is at the valid level so that the first control module 310B can transmit the valid level of the first scan control signal u2d or the invalid level of the second scan control signal d2u to the second node N2 under the control of the clock signal CKA of the clock signal terminal A. Conversely, when the backward scan is performed on the rows of pixels, the valid level of the second scan control signal d2u can be controlled to supply to the first control module 310B when the second input signal Vin2 of the second input terminal IN2 is at the valid level, and the invalid level of the first scan control signal u2d can be controlled to supply to the first control module 310B when the first input signal Vin1 of the first input terminal IN1 is at the valid level so that the first control module 310B can transmit the invalid level of the first scan control signal u2d or the valid level of the second scan control signal d2u to the second node N2 under the control of the clock signal CKA of the clock signal terminal A. In this way, the first scan control terminal U2D, the second scan control terminal D2U, the second input terminal IN2 and the input module 360B are disposed in the each shift register unit 31 so that the input module 360B can select the signal supplied to the latch module 310A, avoiding the mutual influence between the signals output by the cascaded shift register units 31.
In an exemplary embodiment, the input module 360B may include a first input transistor M61 and a second input transistor M62. Agate of the first input transistor M61 may be electrically connected to the first input terminal IN1, a first electrode of the first input transistor M61 may be electrically connected to the first scan control terminal U2D, and a second electrode of the first input transistor M61 may be electrically connected to the first control module 310B. A gate of the second input transistor M62 may be electrically connected to the second input terminal IN2, a first electrode of the second input transistor M62 may be electrically connected to the second scan control terminal D2U, and a second electrode of the second input transistor M62 may be electrically connected to the first control module 310B. In this case, the first input signal Vin1 of the first input terminal IN1 may control the first input transistor M61 to turn on or off so that when the first input signal Vin1 of the first input terminal IN1 controls the first input transistor M61 to turn on, the first scan control signal u2d of the first scan control terminal U2D can be supplied to the first control module 310B; and the second input signal Vin2 of the second input terminal IN2 may control the second input transistor M62 to turn on or off so that when the second input signal Vin2 of the second input terminal IN2 controls the second input transistor M62 to turn on, the second scan control signal d2u of the second scan control terminal D2U can be supplied to the first control module 310B. The first input transistor M61 and the second input transistor M62 may be n-type transistors or p-type transistors. This may be disposed according to actual requirements and is not specifically limited in the embodiments of the present application.
With continued reference to
In an exemplary embodiment, with continued reference to
Based on the same inventive concept, an embodiment of the present application further provides a display device. The display device includes the display panel provided in the embodiments of the present application. Therefore, the display device has the technical features of the display panel and the driving method provided in the embodiments of the present application and can achieve the beneficial effects of the display panel provided in the embodiment of the present application. Similarities may be referred to the preceding description of the display panel provided in the embodiments of the present application and are not repeated herein.
Exemplarily,
It is to be understood that various forms of operation processes of the pixel circuit shown in the preceding may be adopted with steps reordered, added, or deleted. For example, the steps in the operation process of each pixel circuit described in the present application may be performed in parallel, sequentially, or in different sequences, as long as the desired results of the technical solutions of the present application can be achieved, and no limitation is imposed herein.
The preceding embodiments do not limit the scope of the present application. It is to be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be performed according to design requirements and other factors. Any modification, equivalent substitution and improvement or the like made within the spirit and principle of the present application falls within the scope of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311322114.3 | Oct 2023 | CN | national |
