Patent Application
20240379043
This application claims priority to Chinese patent application No. 202310942643.7 filed with the China National Intellectual Property Administration (CNIPA) on Jul. 28, 2023, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technologies and, in particular, a display panel and a display device.
With the development of display technologies, electronic products having a display function are widely applied to various fields. Televisions, mobile phones, computers, and personal digital assistants are all electronic products that have the display function and become an indispensable part of people's lives and work. A display panel is the core structure for implementing the display function in each electronic product.
Generally, a pixel array and a drive circuit for driving the pixel array are provided in the display panel, and the drive circuit can implement scanning for the pixel array row by row to allow the pixel array to perform image display. However, due to the function and structure of the drive circuit in the related art, the drive modes of rows of pixels in the pixel array are made identical, so that the display panel cannot meet diversified display requirements.
A display panel and a display device are provided according to the present disclosure to enable the display panel to meet diversified functional requirements and broaden the application scenario of the display panel.
According to one aspect of the present disclosure, a display panel is provided, which includes a drive circuit.
The drive circuit includes cascaded N stages of shift registers, where N≥2.
A shift register includes a control unit, an initial output unit and a first output unit.
The control unit is configured to at least receive an input signal and control a signal of the first output node and a signal of the second output node.
The initial output unit is configured to at least receive the signal of the first output node and the signal of the second output node, and control an initial output signal, and the initial output signal of an xth stage shift register is the input signal of a yth stage shift register, 1≤x≤N, and 1≤y≤N.
The first output unit is configured to at least receive the signal of the first output node and the signal of the second output node, and control a first output signal.
According to another aspect of the present disclosure, a display device is provided, which includes the above-described display panel.
It is to be appreciated that the contents described in this part are not intended to identify key or important features of the embodiments of the present disclosure, and are not intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the description hereinafter.
To illustrate technical solutions in embodiments of the present disclosure more clearly, drawings used in description of the embodiments are briefly described hereinafter. Apparently, the drawings described hereinafter merely illustrate some embodiments of the present disclosure, and for the person of ordinary skill in the art, other drawings can be obtained based on these drawings on the premise that no creative efforts are made.
To enable the person skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure are described clearly and completely in conjunction with the drawings in the embodiments of the present disclosure. Apparently, the embodiments described below are part, rather than all, of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by the person skilled in the art on the premise that no creative efforts are made are within the scope of the present disclosure.
It is to be noted that the terms “first”, “second” and the like in the description, claims and the above drawings of the present disclosure are intended to distinguish between similar objects and are not necessarily used to describe a particular order or sequence. It is to be appreciated that the data used in this way is interchangeable where appropriate so that the embodiments of the present disclosure described herein may also be implemented in a sequence besides those sequences illustrated or described herein. Furthermore, terms such as “include”, “have”; and any deformation thereof, are intended to cover non-exclusive inclusion, e.g., a process, method, system, product, or device including a series of steps or units is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to such process, method, system, product or device.
As described in the background,
To address the above-described technical issue, a display panel is provided according to an embodiment of the present disclosure and includes a drive circuit. The drive circuit includes N cascaded stages of shift registers, where N≥2. A shift register includes a control unit, an initial output unit and a first output unit. The control unit is configured to control a signal of the first output node and a signal of the second output node. The initial output unit is configured to at least receive the signal of the first output node and the signal of the second output node and control an initial output signal, the initial output signal of an xth stage shift register is the input signal of a yth stage shift register, 1≤x≤N, and 1≤y≤N. The first output unit is configured to at least receive the signal of the first output node and the signal of the second output node, and control a first output signal.
With the above-described technical solution, the shift register includes the control unit, the initial output unit and the first output unit, and in response to an input signal, the control unit may control the initial output unit to output an initial output signal and control the first output unit to output a first output signal, and the control unit may use the initial output signal of an xth stage shift register as the input signal of a yth stage shift register, the first output signal is taken as a control signal of pixel circuits in the display panel, so that the initial output signal provided to other stage shift register and the first output signal provided to the pixel circuits are independent from rom each other and do not affect each other, thereby flexibly controlling the polarity of the first output signal provided to the pixel circuit while ensuring that the cascading and shifting of signals can be performed among the shift registers, so that the drive modes of the pixel circuits of different rows in the display panel can be the same or different, thereby enabling the display panel to meet diversified display requirements, and widening the application scenario of the display panel.
The preceding is the core idea of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by the person of ordinary skill in the art without creative work are within the scope of the present disclosure. Technical solutions in embodiments of the present disclosure are clearly and completely described in conjunction with drawings in the embodiments of the present disclosure.
The display panel 100 may include a display region 101 and a non-display region 102 surrounding the display region 101, the drive circuit 10 may be arranged in the non-display region 102, multiple pixel circuits 20 arranged in an array and multiple drive signal lines 31 may be arranged in the display region 101, and at least part of pixel circuits 20 located in the same row are electrically connected to the same drive signal line 31. In this case, output terminals of the first output units 131 of shift registers G of all stages may be electrically connected to different drive signal lines 31 respectively, to output the first output signals Gout1 to the drive signal lines respectively. In this manner, the drive signal lines 31 may transmit the first output signals Gout1 output by the first output units 131 of the N stages of shift registers G to the rows of pixel circuits 20, to drive the pixel circuits 20 in each row.
It is to be noted that the above only illustrates by taking it as an example that the drive circuit 10 is located in the non-display region 102 and the pixel circuits 20 are located in the display region 101, while in another embodiment of the present disclosure, the pixel circuits 20 and the drive circuit 10 may all be located at the display region 101, so that devices arranged in the non-display region 102 of the display panel 100 are less enough to reduce the dimension of the non-display region 102 in the display panel 100, thereby facilitating realization of narrow bezel of the display panel 100 and enabling the display panel 100 to have a higher screen-to-body ratio.
For the convenience of description, on the premise that no special limitation is imposed, in each of the embodiments of the present disclosure, the technical solution of the embodiment of the present disclosure is described by taking it as an example that the drive circuit is located at the non-display region of the display panel and the pixel circuits are located at the display region of the display panel.
With continued reference to
For the convenience of description, on the premise that no special limitation is imposed, the technical solution of the embodiment of the present disclosure is described in each embodiment of the present disclosure by taking the case that the xth stage shift register and the yth stage shift register are two adjacent stages of shift registers as an example.
Referring to
Accordingly, in the same shift register G, the initial output unit 120 may output a corresponding initial output signal Vnext according to the signal of the first output node N1 and the signal of the second output node N2 received by the initial output unit 120. At the same time, the first output unit 131 may output a corresponding first output signal Gout1 according to the signal of the first output node N1 and the signal of the second output node N2 received by the first output unit 131. The initial output signal Vnext and the first output signal Gout1 may each be a pulse signal composed of a high level and a low level.
Since the initial output signal Vnext and the first output signal Gout1 are respectively provided by the initial output unit 120 and the first output unit 131, and the structures and/or working modes of the initial output unit 120 and the first output unit 131 may be the same or different, the initial output signal Vnext and the first output signal Gout1 may be the same or different. For example, in some application scenarios, the voltage of the initial output signal Vnext may be different from the voltage of the first output signal Gout1, and/or, the frequency of the initial output signal Vnext may be different from the frequency of the first output signal Gout1. In some other application scenarios, the voltage and/or frequency of the initial output signal Vnext may be the same as that of the first output signal Gout1.
In one or more embodiments,
In one or more embodiments, within at least a part of the time period of the working process of the display panel, the pulse change frequency F1 of the first output signal Gout1 is set to be different from the pulse change frequency F0 of the initial output signal Vnext, i.e., period t01 of the first output signal Gout1 is different from period t00 of the initial output signal Vnext. In this case, within a part of the time period of the working process of the display panel, the time of the effective pulse of the initial output signal Vnext overlaps the time of the inactive level of the first output signal Gout1, and/or, the time of the effective pulse of the first output signal Gout1 overlaps the time of the inactive level of the initial output signal Vnext, so that the time of the effective pulse of the initial output signal Vnext provided for the next stage shift register G does not overlap with the time of the effective pulse of the first output signal Gout1 provided to the pixel circuits. In this manner, the first output signal Gout1 and the initial output signal Vnext output by the same shift register G are independent of each other and do not affect each other, thereby meeting the driving requirements of the drive circuit while ensuring the normal display of the display panel.
In one or more embodiments,
Within at least a part of the time period of the working process of the display panel, the pulse change frequency F0 of the initial output signal Vnext is set to be greater than the pulse change frequency F1 of the first output signal Gout1, i.e., period t01 of the first output signal Gout1 is greater than period t00 of the initial output signal Vnext, such that within a part of the time period of the working process of the display panel, the time of the effective pulse of the initial output signal Vnext overlaps the time of the inactive level of the first output signal Gout1, and within another part of the time period of the working process of the display panel, the time of the effective pulse of the first output signal Gout1 overlaps the time of the effective pulse of the initial output signal Vnext. As a result, within part of the time period, the initial output signal Vnext provided normally by the shift register G to the next stage shift register G includes an active level while the first output signal Gout1 provided normally by the shift register G to the pixel circuits is an inactive level, so that the next stage shift register G can work normally, and the pixel circuits may not perform signal refreshing. In the other part of the time period, the initial output signal Vnext provided by the shift register G to the next stage shift register G includes an active level while the first output signal Gout1 provided by the shift register G to the pixel circuits also includes an active level, so that the next stage shift register G can work normally and the pixel circuits can also perform signal refreshing. In this way, in a part of the time period, the power consumption caused by the signal refreshing of the pixel circuits can be reduced, thereby facilitating low power consumption of the display panel, while within another part of the time period, the signal in the pixel circuits is refreshed, thereby ensuring the normal display of the display panel and preventing the flicker of the image.
In one or more embodiments, when the pulse change frequency F0 of the initial output signal Vnext is greater than the pulse change frequency F1 of the first output signal Gout1, the pulse change frequency F0 of the initial output signal Vnext may be an integer multiple of the pulse change frequency F1 of the first output signal Gout1, for example, F0 may be equal to 2*F1 or 3*F1, or the like. In another embodiment, the pulse change frequency F0 of the initial output signal Vnext may also be a non-integer multiple of the pulse change frequency F1 of the first output signal Gout1, for example, F0 may be equal to 3/2*F1 or 12/5*F1, or the like. The relationship between F0 and F1 is not limited in the embodiments of the present disclosure.
It may be understood that when the drive circuit of the display panel includes multiple stages of shift register G, the pulse change frequency F0 of the initial output signal Vnext of each stage shift register G may be greater than the pulse change frequency F1 of the first output signal Gout1, in this case, the drive frequency of the drive circuit may be greater than the signal refresh rate of each pixel circuit. Alternatively, it is possible that only a part of the shift registers G have the pulse change frequency F0 of the initial output signal Vnext greater than the pulse change frequency F1 of the first output signal Gout1 thereof, while for another part of the shift registers G, the pulse change frequency F0 of the initial output signal Vnext may be less than or equal to the pulse change frequency F1 of the first output signal Gout1 thereof, which is not limited in the embodiments of the present disclosure as long as the diversified display requirements of the display panel can be met.
In an exemplary embodiment,
It may be appreciated that the above only provides an exemplary explanation with the first display region A1 located between two second display regions A2 as an example, while in the embodiments of the present disclosure, the first display region and the second display region may be designed according to practical display requirements. For example, when the display panel is in a static standby image for displaying only the time, the image at the time display region changes in real time, and it is required to refresh the pixel circuits at the time display region in real time, ensuring that the region can accurately display the time. The image in the other region remains unchanged, it is not required to refresh the pixel circuits in those regions in real time. In this case, the refresh rate of the time display region may be greater than the refresh rate of the other region, that is, the time display region is the first display region while the other region is the second display region.
In this embodiment, the initial output signal output by the initial output unit is used as the input signal of a shift register of another stage, and the first output signal output by the first output unit is used as the drive signal of the pixel circuits in the display panel, so that the initial output signal provided to the shift register of another stage and the first output signal provided to the pixel circuits are independent of each other and do not affect each other, thus the polarity of the first output signal provided to the pixel circuits can be flexibly controlled while the cascaded transmission and shifting of signals between the shift registers can be ensured. In this manner, the drive modes of the pixel circuits in different rows of the display panel can be the same or different, thereby enabling the display panel to meet multiple display requirements, and widening the application scenario of the display panel, for example, different regions of the display panel can have different refresh rates.
It is to be noted that since both the initial output unit and the first output unit receive at least the signals of the first output node and the second output node, the signals of the first output node and the second output node can control the initial output signal output by the initial output unit and control the first output signal output by the first output unit, and the initial output signal and the first output signal may be the same or different, which is related to the structures of the initial output unit and the first output unit, and the structures of the initial output unit and the first output unit are described for example below by typical examples.
In one or more embodiments,
The first initial output module 121 at least receives the initial output control signal CK0 and the signal of the first output node N1 so that the first initial output module 121 can output the initial output signal Vnext under the control of the initial output control signal CK0 and the signal of the first output node N1. The second initial output module 122 at least receives the first voltage signal VGH and the signal of the second output node N2 so that the second initial output module 122 can output the initial output signal Vnext under the control of the first voltage signal VGH and the signal of the second output node N2. In this case, the first output node N1, the second output node N2, the first voltage signal VGH and the initial output control signal CK0 can determine the polarity and amplitude of the initial output signal Vnext.
In an exemplary embodiment, when the signal of the first output node N1 is an active level, the first initial output module 121 may control the initial output signal Vnext to be consistent with the initial output control signal CK0, while when the signal of the second output node N2 is an active level, the second initial output module 122 may control the initial output signal Vnext to be consistent with the first voltage signal VGH.
Accordingly, with continued reference to
The initial output control signal CK0 may be a pulse signal at a frequency of Fc0 such that the initial output control signal CK0 includes a high level and a low level. The first voltage signal VGH is a fixed signal, for example, the first voltage signal VGH may be a high-level signal so that when it is required to output a high-level initial output signal Vnext, the first output node N1 controls the first initial output transistor M01 to be turned on when the initial output control signal CK0 is a high level, and/or, the second output node N2 controls the second initial output transistor M02 to be turned on, so that the initial output signal Vnext is consistent with the high-level initial output control signal CK0 and/or the first voltage signal VGH. When it is required to output a low-level initial output signal Vnext, the first output node N1 controls the first initial output transistor M01 to be turned on when the initial output control signal CK0 is a low level so that the initial output signal Vnext is consistent with the low-level initial output control signal CK0. With this arrangement, the initial output signal Vnext can be a pulse signal having a high level and a low level, thereby meeting the driving requirements of the shift registers G.
In another embodiment,
In one or more embodiments, the initial stabilization module 123 may include a third initial output transistor M03. A first electrode of the third initial output transistor M03 is connected to the first output node N1, a second electrode of the third initial output transistor M03 is connected to the third output node N3, and a gate of the third initial output transistor M03 receives a second voltage signal VGL.
The second voltage signal VGL may control the third initial output transistor M03 to remain the on state continuously, such that the signal of the first output node N1 remains substantially consistent with the signal of the third output node N3. However, since the turned-on third initial output transistor M03 has a certain resistance, when the signal of the third output node N3 electrically connected to the first initial output transistor M01 changes, the third initial output transistor M03 can reduce the change amount at which the signal of the first output node N1 changes with the signal of the third output node N3. Similarly, when the signal of the first output node N1 changes, the third initial output transistor M03 can also reduce the change amount at which the signal of the third output node N3 changes with the signal of the first output node N1. Thus, by providing the third initial output transistor M03 between the first output node N1 and the third output node N3, the stability of the signals at the first output node N1 and the third output node N3 can be ensured, thereby improving the stability of the initial output signal Vnext output by the first initial output transistor M01.
It may be appreciated that the first initial output transistor M01, the second initial output transistor M02, and the third initial output transistor M03 may each be an N-type transistor or a P-type transistor. For the N-type transistor, when the signal received by the gate of the transistor is a high level, the transistor is turned on, and when the signal received by the gate is a low level, the transistor is turned off. For the P-type transistor, when the signal received by the gate of the transistor is a low level, the transistor is turned on, and when the signal received by the gate is a high level, the transistor is turned off. The high level and low level of the signal at the gate of the transistor are defined relative to the signal at the source of the transistor, the amplitudes and polarities of the high level and low level of the signal are not limited in the embodiments of the present disclosure. Therefore, for transistors of different types, to realize the same technical principle, it is simply required to adaptively adjust the signal at the gate of the transistor according to the type of the transistor. For the convenience of the description, on the premise that no special limitations are imposed, each embodiment of the present disclosure takes the referred transistor being a P-type transistor as an example, to illustrate the technical solutions of the embodiments of the present disclosure.
In one or more embodiments, when the second voltage signal VGL is a low-level signal, the low-level second voltage signal VGL can control the third initial transistor M03 to be in the on state, such that the signal of the first output node N1 remains substantially consistent with the signal of the third output node N3.
On the basis of the above-described embodiments, the initial output unit 120 may further include an initial bootstrap capacitor C01, the initial bootstrap capacitor C01 may be electrically connected between the second electrode of the first initial output transistor M01 and the gate of the first initial output transistor M01, so that when the initial output signal Vnext at the second electrode of the first initial output transistor M01 hops from the high level to the low level or from the low level to the high level, the signal at the gate of the first initial output transistor M01 may be controlled to change with the initial output signal Vnext due to the coupling of the initial bootstrap capacitor C01, thereby ensuring that the signal at the gate of the first initial output transistor M01 has sufficiently high drive capability to drive the first initial output transistor M01 to be turned on or off.
Furthermore, the initial output unit 120 may further include a hold capacitor C02, a first plate of the hold capacitor C02 receives the first voltage signal VGH, a second plate of the hold capacitor C02 is electrically connected to the second output node N2, so that the hold capacitor C02 stores the signal of the second output node N2 to ensure that the signal of the second output node N2 can continuously control the second initial output transistor M02 to be turned on or off.
Alternatively,
The first output module 1311 at least receives the first output control signal CK1 and the signal of the first output node N1 so that the first output module 1311 outputs the first output signal Gout1 under the control of the first output control signal CK1 and the signal of the first output node N1. The second output module 1312 at least receives the first voltage signal VGH and the signal of the second output node N2 so that the second output module 1312 outputs the first output signal Gout1 under the control of the first voltage signal VGH and the signal of the second output node N2. In this case, the first output node N1, the second output node N2, the first voltage signal VGH and the first output control signal CK1 can determine the polarity and amplitude of the first output signal Gout1.
In an exemplary embodiment, when the signal of the first output node N1 is an active level, the first output module 1311 may control the first output signal Gout1 to be consistent with the first output control signal CK1, while when the signal of the second output node N2 is an active level, the second output module 1312 may control the first output signal Gout1 to be consistent with the first voltage signal VGH.
Alternatively,
Accordingly, with continued reference to any one of
The first output control signal CK1 may be a pulse signal with a pulse change frequency of Fc1 such that the first output control signal CK1 includes a high level and a low level. The first voltage signal VGH is a fixed signal, for example, the first voltage signal VGH may be a high-level signal, so that when it is required to output a high-level first output signal Gout1, the first output node N1 controls the first transistor M11 to be turned on when the first output control signal CK1 is a high level, and/or, the second output node N2 controls the second transistor M12 to be turned on, so that the first output signal Gout1 is kept consistent with the high-level first output control signal CK1 and/or the first voltage signal VGH. When it is required to output a low-level first output signal Gout1, the first output node N1 controls the first transistor M11 to be turned on when the first output control signal CK1 is a low level, to enable the first output signal Gout1 to be consistent with the low-level first output control signal CK1. With this arrangement, the first output signal Gout1 can be a pulse signal having a high level and a low level, thereby meeting the driving requirements of the shift registers G.
In another embodiment,
In one or more embodiments, with continued reference to
The second voltage signal VGL may control the third transistor M13 to remain the on state continuously, such that the signal of the first output node N1 is substantially consistent with the signal of the first node N11. However, since the turned-on third transistor M13 has a certain resistance, when the signal of the first node N11 electrically connected to the first transistor M11 changes, the third transistor M13 can reduce the change amount at which the signal of the first output node N1 changes with the signal of the first node N11; similarly, when the signal of the first output node N1 changes, the third transistor M13 can also reduce the change amount at which the signal of the first node N11 changes with the signal of the first output node N1. Thus, by arranging the third transistor M13 between the first output node N1 and the first node N11, the stability of the signals at the first output node N1 and the first node N11 can be ensured, thereby the stability of the first output signal Gout1 output by the first transistor M11 is improved.
In other embodiments, as shown in
On the basis of the above-described embodiments, with reference to any one of
On the basis of the above embodiment,
The first control module 111 may provide a signal for the first output node N1 under the control of the first voltage signal VGH, the first clock signal XCK0, the initial output control signal CK0 and the input signal Vin such that the first voltage signal VGH, the first clock signal XCK0, the initial output control signal CK0 and the input signal Vin can control the polarity and amplitude of the signal of the first output node N1. The second control module 112 may provide a signal for the second output node N2 under the control of the second voltage signal VGL and the first clock signal XCK0 such that the second voltage signal VGL and the first clock signal XCK0 can control the polarity and amplitude of the signal of the second output node N2.
In an exemplary embodiment, when the first clock signal XCK0 is an active level, the first control module 111 may transmit the input signal Vin to the first output node N1 so that the signal of the first output node N1 is consistent with the input signal Vin, and the second control module 112 may transmit the second voltage signal VGL to the second output node N2 so that the signal of the second output node N2 is consistent with the second voltage signal VGL.
In one or more embodiments, the first control module 111 may include a first control transistor M04, a second control transistor M07 and a third control transistor M08. A first electrode of the first control transistor M04 receives the input signal Vin, a second electrode of the first control transistor M04 is electrically connected to the first output node N1, and a gate of the first control transistor M04 receives the first clock signal XCK0. A first electrode of the second control transistor M07 receives the first voltage signal VGH, a second electrode of the second control transistor M07 is electrically connected to the first electrode of the third control transistor M08, a second electrode of the third control transistor M08 is electrically connected to the first output node N1, a gate of the second control transistor M07 is electrically connected to the second output node N2, and a gate of the third control transistor M08 receives the initial output control signal CK0. In this case, the first clock signal XCK0 can control the first control transistor M04 to be turned on or off, and when the first clock signal XCK0 controls the first control transistor M04 to be turned on, the first control transistor M04 can transmit the input signal Vin to the first output node N1 so that the signal of the first output node N1 is consistent with the input signal Vin. The signal of the second output node N2 can control the second control transistor M07 to be turned on or off, and the initial output control signal CK0 can control the third control transistor M08 to be turned on or off, and when the signal of the second output node N2 controls the second control transistor M07 to be turned on and the initial output control signal CK0 controls the third control transistor M08 to be turned on, the first voltage signal VGH is transmitted to the first output node N1 such that the signal of the first output node N1 keeps consistent with the first voltage signal VGH.
Accordingly, the second control module 112 may include a fourth control transistor M05 and a fifth control transistor M06. A first electrode of the fourth control transistor M05 receives the second voltage signal VGL, a second electrode of the fourth control transistor M05 is electrically connected to the second output node N2, and a gate of the fourth control transistor M05 receives the first clock signal XCK0. A first electrode of the fifth control transistor M06 receives the first clock signal XCK0, a second electrode of the fifth control transistor M06 is electrically connected to the second output node N2, and a gate of the fifth control transistor M06 is electrically connected to the first output node N1. In this case, the first clock signal XCK0 may control the fourth control transistor M05 to be turned on or off, and the signal of the first output node N1 controls the fifth control transistor M06 to be turned on or off. When the first clock signal XCK0 controls the fourth control transistor M05 to be turned on, the fourth control transistor M05 can transmit the second voltage signal VGL to the second output node N2, so that the signal of the second output node N2 keeps consistent with the second voltage signal VGL. When the signal of the first output node N1 controls the fifth control transistor M06 to be turned on, the signal of the second output node N2 keeps consistent with the first clock signal XCK0.
It may be appreciated that the first clock signal XCK0 may be a pulse signal such that the first clock signal XCK0 may include a high level and a low level. The input signal Vin is the initial output signal Vnext of the previous stage shift register G so that the input signal Vin may likewise include a high level and a low level. The first voltage signal VGH and the second voltage signal VGL are fixed signals, for example, the second voltage signal VGL may be a low-level signal, and the first voltage signal VGH may be a high-level signal. The pulse change frequency of the first clock signal XCK0 and the pulse change frequency of the initial output control signal CK0 may be the same, that is, the pulse change frequencies of the first clock signal XCK0 and the initial output control signal CK0 are both Fc0. In this case, the phase of the first clock signal XCK0 is different from the phase of the initial output control signal CK0, that is, when the first clock signal XCK0 is an active level, the initial output control signal CK0 is an inactive level; and in contrast, when the initial output control signal CK0 is an active level, the first clock signal XCK0 is an inactive level.
When the second output node N2 requires a low-level signal, the first clock signal XCK0 may be enabled to control the fourth control transistor M05 to be turned on, thus, the low-level first voltage signal VGL may be transmitted to the second output node N2 through the turned-on fourth control transistor M05, and/or, when the first clock signal XCK0 is a low level, the signal of the first output node N1 controls the fifth control transistor M06 to be turned on, so that the low-level first clock signal XCK0 is transmitted to the second output node N2. When the second output node N2 requires a high-level signal, the fifth control transistor M06 may be controlled to be turned on by the signal of the first output node N1 when the first clock signal XCK0 is a high level, so that the high-level first clock signal XCK0 is transmitted to the second output node N2, thereby, the signal of the second output node N2 may be set according to practical requirements.
Similarly, when the first output node N1 requires a high-level signal, the first clock signal XCK0 may control the first control transistor M04 to be turned on when the input signal Vin is a high level, and at this time, the signal of the first output node N1 can be consistent with the high-level input signal Vin, or while the signal of the second output node N2 controls the second control transistor M07 to be turned on, the initial output control signal CK0 controls the third control transistor M08 to be turned on, so that the high-level first voltage signal VGH is transmitted to the first output node N1. When the first output node N1 requires a low-level signal, the first clock signal XCK0 may be enabled to control the first control transistor M04 to be turned on when the input signal Vin is a low level, so that the first control transistor M04 can transmit the low-level input signal Vin to the first output node N1. With this arrangement, the signal of the first output node N1 can be controlled as required.
In an exemplary embodiment, the case that each transistor in the shift register is a p-type transistor is taken as an example.
At phase t1, when the input signal Vin is turned to a low level, the first clock signal XCK0 is a low level at the same time, and the initial output control signal CK0 and the first output control signal CK1 are both the high level. In this case, the first clock signal XCK0 controls both the first control transistor M04 and the fourth control transistor M05 to be turned on, and the low-level input signal Vin may be transmitted to the first output node N1 through the first control transistor M04, so that the signal of the first output node N1 is turned to a low level. This low-level signal can control both the first initial output transistor M01 and the first transistor M11 to be turned on, so that the initial output control signal CK0 is transmitted to the second electrode of the first initial output transistor M01, and the first output control signal CK1 is transmitted to the second electrode of the first transistor M11. Meanwhile, the second voltage signal VGL is also transmitted to the second output node N2 through the fourth control transistor M05 so that the second output node N2 is also a low level, and the low-level signal can control the second initial output transistor M02 and the second transistor M12 to be turned on at the same time, so that the high-level first voltage signal VGH is transmitted to the second electrode of the second initial output transistor M02, and the first voltage signal VGH may further be transmitted to the second electrode of the second transistor M12. In this case, the signal at the second electrode of the first initial output transistor M01 and the signal at the second electrode of the second initial output transistor M02 are both high-level signals so that the initial output signal Vnext is kept at the high level, and the signal at the second electrode of the first transistor M11 and the signal at the second electrode of the second transistor M12 are both the high-level signals so that the first output signal Gout1 is also kept at the high level. Furthermore, since the signal of the first output node N1 is the low level, the fifth control transistor M06 is in the on state, the low-level first clock signal XCK0 is transmitted to the second output node N2 through the fifth control transistor M06, so that the second output node N2 keeps a low level; at the same time, since the signal of the second output node N2 is a low level, the second control transistor M07 is in the on state, but because the initial output control signal CK0 is a high level, the third control transistor M08 is in the off state, the first voltage signal VGH cannot be transmitted to the first output node N1, and the signal of the first output node N1 is kept consistent only with the input signal Vin.
At phase t2, the input signal Vin is turned to a high level, and the first clock signal XCK0 is also the high level. The initial output control signal CK0 and the first output control signal CK1 are the low level. The first clock signal XCK0 controls both the first control transistor M04 and the second control transistor M07 to be turned off, and the first output node N1 remains the signal input in the phase t1, that is, the signal of the first output node N1 remains a low level. In this manner, the fifth control transistor M06 in the on state, and the high-level first clock signal XCK0 is transmitted to the second output node N2 through the fifth control transistor M06 so that the second output node N2 becomes a high level. The signal of the second output node N2 controls the second control transistor M07 to be turned off, and the second voltage signal VGH cannot be transmitted to the first output node N1 so that the signal of the first output node N1 is kept at a low level. At this time, the signal of the first output node N1 continues to control the first initial output transistor M01 and the first transistor M11 to be in the on state, while the second output node N2 controls both the second initial output transistor M02 and the second transistor M12 to be in the off state. In this way, the initial output signal Vnext is kept consistent with the low-level initial output control signal CK0, and the first output signal Gout1 is kept consistent with the low-level first output control signal CK1.
At phase t3, the input signal Vin is turned to the high level, the first clock signal XCK0 is turned to the low level, the initial output control signal CK0 and the first output control signal CK1 are both turned to the high level, thus, the first control transistor M04 and the fourth control transistor M05 are both turned on, the signal of the first output node N1 is consistent with the high-level input signal Vin, and signal of the second output node N2 is consistent with the low-level second voltage signal VGL, so that the signal of the first output node N1 controls the first initial output transistor M01 and the first transistor M11 to be both turned off, and the signal of the second output node N2 controls the second initial output transistor M02 and the second transistor M12 to be both turned on. At this time, the initial output signal Vnext and the first output signal Gout1 are both consistent with the high-level first voltage signal VGH.
After phase t3, the first output node N1 and the second output node N2 will continue to remain as the signals in phase t2 until the input signal Vin is turned to the low level again. Thus, when the initial output signal Vnext of an xth stage shift register Gx serves as the input signal Vin of a yth stage shift register Gy, the low-level signal of the initial output signal Vnext of the xth stage shift register Gx and the low-level signal of the initial output signal Vnext of the yth stage shift register Gy can sequentially shift, and meanwhile, the low-level signal of the first output signal Gout1 of the xth stage shift register Gx of and the low-level signal of the first output signal Gout1 of the yth stage shift register Gy can sequentially shift, so that the low-level signal of the initial output signals Vnext and the low-level signal of the first output signal Gout1 output by the shift register of each stage can shift sequentially. When the first output signals Gout1 output by the shift registers of all stages are used to control the signal refreshing time of the pixel circuits in each row, the pixel circuits in each row of the display panel can be scanned row by row.
It may be appreciated that when the low level of the initial output signal Vnext and the low level of the first output signal Gout1 output by the shift registers G of each stage shift sequentially, the low-level signal is just an active level capable of controlling the pixel circuits to perform signal refreshing. When the active level causing the pixel circuits to perform the signal refreshing is the high level, as shown in
Alternatively, referring to
In one or more embodiments, as shown in
In another embodiment, as shown in
It may be appreciated that the preset module of the pixel circuit may be any one of the modules in the pixel circuit and may be selected on the basis of practical requirements. The pixel circuit and its preset module mentioned in the embodiments of the present disclosure are described below as a typical example.
In one or more embodiments of the present disclosure,
In one or more embodiments, the light-emitting element 40 is typically a current-type drive element, and the data signal Vdata provided by the data writing module 220 is typically a voltage signal, therefore, a drive transistor T1 is provided in the drive module 210, the data signal Vdata provided by the data writing module 220 can be written into a gate of the drive transistor T1, and the drive transistor T1 can generate a corresponding drive current according to the signal of the gate thereof, and provide the corresponding drive current to the light-emitting element 40 to drive the light-emitting element 40 to emit light of the corresponding brightness. In this case, one of a source and a drain of the drive transistor MI receives a positive power signal PVDD, and the other one is coupled to the anode of the light-emitting element 40, and the cathode of the light-emitting element 40 may receive a negative power signal PVEE. In this way, a voltage difference exists between the positive power signal PVDD and the negative power signal PVEE to form a current path, thereby the drive transistor T1 can generate a drive current and supply the drive current to the light-emitting element 40 to drive the light-emitting element 40 to emit light.
It may be appreciated that, as shown in
Accordingly, the data writing module 220 may be connected to the first electrode of the drive transistor T1, for providing a data signal Vdata to the drive transistor T1. The compensation module 230 may be connected between the gate and the second electrode of the drive transistor T1, for compensating a threshold voltage of the drive transistor T1. The reset module 240 may be connected to the gate of the drive transistor T1, for providing a reset signal Vref to the gate of the drive transistor T1, to reset the gate of the drive transistor T.
The control terminal of the data writing module 220 may receive a first scan signal S1, and the first scan signal S1 controls the data writing module 220 to be turned on and off. The control terminal of the compensation module 230 may receive a second scan signal S2, and the second scan signal S2 controls the compensation module 230 to be turned on and off. The control terminal of the reset module 240 may receive a third scan signal S3, and the third scan signal S3 controls the reset module 240 to be turned on and off.
When the third scan signal S3 controls the reset module 240 to be turned on, the reset signal Vref may be transmitted to the gate of the drive transistor T1, to reset the gate of the drive transistor T1, so that the data signal Vdata provided to the gate of the drive transistor T1 in the previous drive cycle is cleared, and preparation for the writing of the subsequent data signal Vdata is made.
When the first scan signal S1 controls the data writing module 220 to be turned on, the data signal Vdata may be written into the first electrode of the drive transistor T1 through the data writing module 220 to refresh the signal of the first electrode of the drive transistor T1. At this time, if the drive transistor T1 is in the on state, and the second scan signal S2 controls the compensation module 230 to be turned on, the data signal Vdata may further be provided to the second electrode of the drive transistor T1 through the drive transistor T1, and provided to the gate of the drive transistor T1 through the compensation module 230, and the threshold voltage Vth of the drive transistor T1 is compensated to the gate of the drive transistor T1 so that the signals of the gate and the second electrode of the drive transistor T1 can be refreshed, to enable the drive current generated by the drive transistor T1 to be independent from the threshold voltage Vth of the drive transistor T1.
In an exemplary embodiment, the data writing module 220 may include a data writing transistor T2, a first electrode of the data writing transistor T2 receives the data signal Vdata, a second electrode of the data writing transistor T2 is electrically connected to the first electrode of the drive transistor T1, and a gate of the data writing transistor T2 receives the first scan signal S1 so that the first scan signal S1 controls the data writing transistor T2 to be turned on or off. The compensation module 230 includes a compensation transistor T3, a first electrode of the compensation transistor T3 is electrically connected to the second electrode of the drive transistor T1, a second electrode of the compensation transistor T3 is electrically connected to the gate of the drive transistor T1, and a gate of the compensation transistor T3 receives the second scan signal S2 so that the second scan signal S2 controls the compensation transistor T3 to be turned on or off. The reset module 240 may include a reset transistor T4, a first electrode of the reset transistor T4 receives a reset signal Vref, a second electrode of the reset transistor T4 is electrically connected to the gate of the drive transistor T1, and a gate of the reset transistor T4 receives the third scan signal S3 so that the third scan signal S3 to control the reset transistor T4 to be turned on or off.
On the basis of the above-described embodiments, the pixel circuit 20 may further include an initialization module 250, the initialization module 250 is connected to the anode of the light-emitting element 40, for providing an initialization signal Vini to the light-emitting element 40 to initialize the anode of the light-emitting element 40. The initialization module 250 may be turned on or off under the control of a fourth scan signal S4, when the fourth scan signal S4 controls the initialization module 250 to be turned on, the initialization signal Vini may be provided to the anode of the light-emitting element 40.
In an exemplary embodiment, the initialization module 250 may include an initialization transistor T5, a first electrode of the initialization transistor T5 receives the initialization signal Vini, a second electrode of the initialization transistor T5 is electrically connected to the anode of the light-emitting element 40, and a gate of the initialization transistor T5 receives the fourth scan signal S4 so that the fourth scan signal S4 controls the initialization transistor T5 to be turned on or off.
On the basis of the above-described embodiment, the pixel circuit 20 may further include a light emission control module. The light emission control module may include a first light emission control module 260 and a second light emission control module 270. The first light emission control module 260 and the second light emission control module 270 may control a current path between the positive power signal PVDD and the negative power signal PVEE, thereby controlling the time during which the drive transistor T1 provides the drive current for the light-emitting element 40. The first light emission control module 260 and the second light emission control module 270 may be turned on or off under the control of a light emission control signal EM, when the light emission control signal EM controls the first light emission control module 260 and the second light emission control module 270 to be turned on, the drive transistor T1 can generate the drive current and provide the drive current to the light-emitting element 40 to drive the light-emitting element 40 to emit light.
In an exemplary embodiment, the first light emission control module 260 may include a first light emission control transistor T6, and the second light emission control module 270 may include a second light emission control transistor T7. A first electrode of the first light emission control transistor T6 receives the positive power signal PVDD, a second electrode of the first light emission control transistor T6 is electrically connected to the first electrode of the drive transistor T1, a first electrode of the second light emission control transistor T7 is electrically connected to the second electrode of the drive transistor T1, a second electrode of the second light emission control transistor T7 is electrically connected to the anode of the light-emitting element 40, and both a gate of the first light emission control transistor T6 and a gate of the second light emission control transistor T7 receive the light emission control signal EM so that the light emission control signal EM can control both the first light emission control transistor T6 and the second light emission control transistor T7 to be turned on or off at the same time.
On the basis of the above-described embodiment, the pixel circuit 20 may further include a storage capacitor Cst, a first plate of the storage capacitor Cst receives a fixed signal (e.g., the positive power signal PVDD) and a second plate of the storage capacitor Cst is electrically connected to the gate of the drive transistor T1 to store the signal at the gate of the drive transistor T1.
In another embodiment of the present disclosure,
When the drive module 210 includes the drive transistor T1, the first electrode of the drive transistor T1 may be the first terminal of the drive module 210, and the second electrode of the drive transistor T1 may be the second terminal of the drive module 210, in this case, the bias adjustment module 280 may be electrically connected to the first electrode or the second electrode of the drive transistor T1, which is not limited in the embodiments of the present disclosure on the premise that the bias adjustment on the drive transistor T1 can be implemented.
In one or more embodiments, the bias adjustment module 280 may be turned on or off under the control of a bias adjustment control signal SV, when the bias adjustment control signal SV controls the bias adjustment module 280 to be turned on, the bias adjustment signal V0 may be provided to the first electrode and/or second electrode of the drive transistor T1 to perform the bias adjustment on the drive transistor T1.
In an exemplary embodiment, the bias adjustment module 280 may include a bias adjustment transistor T8, a first electrode of the bias adjustment transistor T8 receives the bias adjustment signal V0, a second electrode of the bias adjustment transistor T8 is electrically connected to the first electrode or the second electrode of the drive transistor T1, and a gate of the bias adjustment transistor T8 receives the bias adjustment control signal SV so that the bias adjustment control signal SV controls the bias adjustment transistor T8 to be turned on or off.
It is to be noted that
Based on the above-described pixel circuits, the drive circuit in the embodiments of the present disclosure may correspondingly provide the control signal to any one of the data writing module 220, the compensation module 230, the reset module 240, the initialization module 250, the light emission control module (the first light emission control module 260 and the second light emission control module 270), and the bias adjustment module 280, so that the preset module of the pixel circuit 200 may be any one of the data writing module 220, the compensation module 230, the reset module 240, the initialization module 250, the light emission control module (the first light emission control module 260 and the second light emission control module 270), and the bias adjustment module 280, that is, the first output signal of the drive circuit may be any one of the first scan signal S1, the second scan signal S2, the third scan signal S3, the fourth scan signal S4, the light emission control signal EM, and the bias adjustment control signal SV. The driving principle of the pixel circuit 20 is described hereinafter by taking it as an example that the first output signal of the drive circuit is the first scan signal S1 for controlling the data writing module 220 to be turned on or off.
With reference to
For the cases where the first output signal Gout1 output by the drive circuit 10 is the control signal of other modules in the pixel circuit 20, they are similar to the case described above, and the embodiments of the present disclosure will not repeat here.
It may be appreciated that the above description illustrates the working process of the shift register G and the driving process of the preset module in the pixel circuit 20 by the first output signal Gout1 output by the shift register by taking an example that the pulse change frequency Fc0 of the initial output control signal CK0 is the same as the pulse change frequency Fc1 of the first output control signal CK1. However, in other embodiments of the present disclosure, within at least a part of the time period of the working process of the display panel, the pulse change frequency Fc0 of the initial output control signal CK0 may be different from the pulse change frequency Fc1 of the first output control signal CK1, that is, Fc0 #Fc1.
In one or more embodiments,
The shift register shown in
In another embodiment,
As such, the pulse change frequency of the initial output control signal CK0 in the first time period t10 may be the same as the pulse change frequency of the first output control signal CK1, while in the second time period t20, the pulse change frequency of the initial output control signal CK0 may be greater than the pulse change frequency of the first output control signal CK1, such that in the first time period t10, the effective pulse time of the initial output signal Vnext is kept consistent with the effective pulse time of the first output signal Gout1, while in the second time period t20, the initial output signal Vnext may include an active level and the first output signal Gout1 may remain an inactive level. In this manner, the first output signal Gout1 and the initial output signal Vnext may be adjusted adaptively in different time periods, such that the display panel meets the diversified functional requirements.
In another embodiment,
It may be appreciated that in the working process of the display panel, the display panel may have different working modes, e.g., the display panel may include a first mode and a second mode, and the refresh rate and/or display brightness of the display panel in the first mode may be different from the refresh rate and/or display brightness of the display panel in the second mode, thereby enabling the display panel to meet different display requirements.
The refresh rate of the display panel is just the writing frequency for writing the data signal to the gate of the drive transistor of the pixel circuit in the display panel, and typically, the time of one frame image may include a data writing frame and a retention frame, that is, the working process of the pixel circuit may include a data writing frame and a retention frame. In the data writing frame, the signal of the gate of the drive transistor in the pixel circuit may be refreshed to clear the data signal written into the gate of the drive transistor in the pixel circuit in the time of the previous frame, and write a data signal corresponding to the current frame to the gate of the drive transistor in the pixel circuit. While in the retention frame, the signal at the gate of the drive transistor in the pixel circuit remains unchanged until entering the data writing frame of the next frame.
Illustratively, when the display panel maintains the same display content within a relatively long time period, for example, when the display panel is in standby mode, it is possible to make the display panel have a relatively low refresh rate, that is, the duration of the retention frame in the working process of the pixel circuit is relatively long, so that in a relatively long time, it is not necessary to refresh the signal at the gate of the drive transistor in the pixel circuit to reduce the power consumption caused by the data refresh, thereby facilitating the low power consumption of the display panel. When the image displayed by the display panel is switched in real time, for example, the display panel may be configured to have a relatively high refresh rate when the display panel is in a video display mode, that is, the duration of the retention frame in the working process of the pixel circuit is relatively short. Therefore, it is necessary to refresh the signal at the gate of the drive transistor in real time so that when the drive transistor generates the drive current according to the signal at the gate of the drive current to drive the light-emitting element to emit light, the accurate light emission of the light-emitting element can be ensured, thereby facilitating the improvement of the image flicker generated when the display panel performs image display, and improving the smoothness of the displayed image.
Since the pulse change frequency of the first output control signal CK1 can control the pulse change frequency of the effective pulse of the first output signal Gout1 output by the shift register, and the first output signal Gout1 can control the signal refresh rate at the corresponding node in the pixel circuit, when the first output control signal CK1 has different pulse change frequencies in different modes, the first output signal Gout1 may also have different pulse change frequencies in different modes so that the signal refresh rates at the corresponding node in the pixel circuit are different in different modes to meet different display requirements of the display panel.
In one or more embodiments, when in the first mode, the pulse change frequency of the first output control signal CK1-1 is Fc1l and the pulse change frequency of the first output signal Gout1-1 is Fs1; in the second mode, the pulse change frequency of the first output control signal CK1-2 is Fc12 and the pulse change frequency of the first output signal Gout1-2 is Fs12, and Fc11≠Fc12 and Fs11≠Fs12, there may be (Fc11−Fc12)×(Fs11−Fs12)>0, so that the pulse change frequency of the first output signal Gout1 increases as the pulse change frequency of the first output control signal CK1 increases, and conversely, the pulse change frequency of the first output signal Gout1 may also decrease as the pulse change frequency of the first output control signal CK1 decreases, thus, the pulse change frequency of the first output signal Gout1 can be kept consistent with the pulse change frequency of the first output control signal CK1.
In one or more embodiments, in a case where the first output signal Gout1 is the signal that controls the preset module in the pixel circuit to be turned on or turned off, and the working process of the pixel circuit includes a data writing frame and a retention frame, the preset module may be turned on in the data writing frame and turned off in the retention frame.
Illustratively, the pixel circuit 20 shown in
In one or more embodiments, the data refresh rate of the pixel circuit in the first mode is Fp1, the data refresh rate of the pixel circuit in the second mode is Fp2, and Fp1≠Fp2.
Illustratively, the pixel circuit 20 shown in
It may be appreciated that the data refresh rate of the pixel circuit 20 is positively correlated with the pulse change frequency of the first output control signal. In one or more embodiments, in a case where the display panel includes the first mode and the second mode, in the first mode, the data refresh rate of the pixel circuit is Fp1 and the pulse change frequency of the first output control signal CK1 is Fc11, and in the second mode, the data refresh rate of the pixel circuit is Fp2 and the pulse change frequency of the first output control signal CK1 is Fc12. If Fc11 is greater than Fc12, Fp1 is greater than Fp2, or if Fc1l is less than Fc12, Fp1 is less than Fp2, namely, (Fp1−Fp2) is positively correlated with (Fc11−Fc12), resulting in (Fp1−Fp2)×(Fc11−Fc12)>0.
It may be appreciated that the pulse change frequency of the first output signal Gout1 output by the shift register is correlated with the pulse change frequency of the first output control signal CK1 received by the shift register, and generally, the pulse change frequency of the first output signal Gout1 may be the same as the pulse change frequency of the first output control signal CK1, so that when the pulse change frequency Fct1 of the first output control signal CK11 received by the first shift register G10 is different from the pulse change frequency Fct2 of the first output control signal CK12 received by the second shift register G20, the pulse change frequency of the first output signal Gout1 output by the first shift register G10 is different from the pulse change frequency of the first output signal Gout1 output by the second shift register G20, that is, when the pulse change frequency of the first output signal Gout1 received by the preset module of the first pixel circuit 21 is Fs11, and the pulse change frequency of the first output signal Gout1 received by the preset module of the second pixel circuit 22 is Fs22, Fs11≠Fs22.
In one or more embodiments, when the preset module of the pixel circuit 20 is turned on to enable the pixel circuit 20 to perform data refresh, the first output control signal CK11 received by the first shift register G10 and the first output control signal CK12 received by the second shift register G20 are configured to have different pulse change frequencies, so that the preset module in the first pixel circuit 21 and the preset module in the second pixel circuit 22 can have different turning on cycles, and further the first pixel circuit 21 and the second pixel circuit 22 can have different data refresh rates, that is, when the data refresh rate of the first pixel circuit 21 is Fp11, and the data refresh rate of the second pixel circuit 22 is Fp22, Fp11≠Fp22.
Correspondingly, since the pulse change frequency of the first output signal Gout1 of the shift register is consistent with the pulse change frequency of the first output control signal CK1 received by the shift register, and the first output signal Gout1 is used to control the turning on and off of the preset module in the pixel circuit 20, so that the turning-on frequency of the preset module in the pixel circuit 20 keeps consistent with the pulse change frequency of the first output signal Gout1. Therefore, the turning-on frequency of the preset module in the pixel circuit 20 is consistent with the pulse change frequency of the first output control signal CK1 so that the refresh rate of the pixel circuit 20 is consistent with the pulse change frequency of the first output control signal CK1, that is, the refresh rate of the pixel circuit 20 increases as the pulse change frequency of the first output control signal CK1 increases. In this way, when (Fct1−Fct2) is a positive value, (Fp11−Fp22) is also a positive value, or when (Fct1−Fct2) is a negative value, (Fp11−Fp22) is also a negative value, that is, (Fp11−Fp22)×(Fct1−Fct2)>0.
In an exemplary embodiment, with reference to
In one or more embodiments, in a case where the display panel 100 includes the first display region A1 and the second display region A2, the first pixel circuit 21 may be located in the first display region A1, and the second pixel circuit 22 may be located in the second display region A2. In this case, the pulse change frequency of the first output control signal CK11 received by the first shift register G10 for controlling the preset module in the first pixel circuit 21 to be turned on or off is Fct1, and the pulse change frequency of the first output control signal CK12 received by the second shift register G20 for controlling the preset module in the second pixel circuit 22 to be turned on or off is Fct2, so that the first pixel circuit 21 and the second pixel circuit 22 have different data refresh rates, that is, the data refresh rate of the first pixel circuit 21 in the first display region A1 is different from the data refresh rate of the second pixel circuit 22 in the second display region A2, thereby meeting the normal display requirements of the display panel 100, and also enabling the display panel 100 to have lower power consumption, so that the display panel 100 can meet diversified display requirements.
It is to be noted that in
In one or more embodiments,
In time period t1′, the first clock signal XCK01 received by the first stage shift register G1 is turned to the inactive level, the start signal STV is also turned to the inactive level, and the signal of the first output node N1 maintains the signal in time period t0′, so that the first initial output module 121 of the first stage shift register G1 continues to output the initial output control signal CK01 received by the first initial output module 121 as the initial output signal Vnext1, and the first output unit 1311 of the first stage shift register G1 continues to output the first output control signal CK111 received by the first output unit 1311 as the first output signal Gout11. At this time, since the initial output control signal CK01 and the first output control signal CK111 received by the first stage shift register G1 are both turned to the active level, the initial output signal Vnext1 and the first output signal Gout11 output by the first stage shift register G1 are both turned to the active level. Furthermore, since the initial output signal Vnext1 of the first stage shift register G1 is the input signal Vin of the second stage shift register G2, the first clock signal XCK02 received by the second stage shift register G2 should be the active level, so that the signal of the first output node N1 in the second stage shift register G2 in this time period is kept consistent with the initial output signal Vnext1 of the first stage shift register G1, the initial output signal Vnext2 output by the second stage shift register G2 is kept consistent with the initial output control signal CK02 received by the second stage shift register G2, and the first output signal Gout12 output by the second stage shift register G2 is kept consistent with the first output control signal CK112 received by the second stage shift register G2. In addition, to ensure that the initial output signals Vnext and the first output signals Gout1 output by the first shift register G1 and the second shift register G2 can shift sequentially, in this time period, the initial output control signal CK02 and the first output control signal CK112 may be the inactive level. In this way, during this time period, the initial output control signal CK01 received by the first stage shift register G1 is different from the initial output control signal CK02 received by the second stage shift register G2, and the first output control signal CK111 received by the first stage shift register G1 is different from the first output control signal CK112 received by the second stage shift register G2, while the initial output control signal CK01 received by the first stage shift register G1 is the same as the first clock signal XCK02 received by the second stage shift register G2, and the first clock signal XCK01 received by the first stage shift register G1 is the same as the initial output control signal CK02 received by the second stage shift register G2.
In time period t2′, the initial output control signal CK01 and the first output control signal CK111 received by the first stage shift register G1 are each the inactive level, while the first clock signal XCK01 received by the first stage shift register G1 is turned to the active level, so that the initial output control signal CK02 and the first output control signal CK112 received by the second stage shift register G2 are all turned to the active level, and the initial output signal Vnext2 and the first output signal Gout12 of the second stage shift register G2 are each the active level. During this time period, the initial output control signal CK01 received by the first stage shift register G1 is different from the initial output control signal CK02 received by the second stage shift register G2, and the first output control signal CK111 received by the first stage shift register G1 is different from the first output control signal CK112 received by the second stage shift register G2, while the initial output control signal CK01 received by the first stage shift register G1 is the same as the first clock signal XCK02 received by the second stage shift register G2, and the first clock signal XCK01 received by the first stage shift register G1 is the same as the initial output control signal CK02 received by the second stage shift register G2. In this manner, the initial output control signal CK01 of the first stage shift register G1 can be used as the first clock signal XCK02 of the second stage shift register G2, and the initial output control signal CK02 of the second stage shift register G2 can be used as the first clock signal XCK01 of the first stage shift register G1, thereby reducing the number of signals provided to the shift registers of all stages, and reducing pins of a driving chip for providing signals to the shift registers of all stages, and further facilitating the simplification of the structure of the driving chip and facilitating the low cost of the driving chip. Moreover, the non-display region 102 of the display panel 100 may further be provided with signal lines (37, 36, 32, 33, 34 and 35) for transmitting the first clock signal XCK0, the initial output control signal CK0 and the first output control signals CK111, CK112, CK121 and CK122. When the first clock signals XCK0 are used as the initial output control signals CK0 of different stages, the number of signal lines set in the non-display region 102 can be reduced, thereby facilitating the realization of the narrow bezel of the display panel 100.
Correspondingly, in time period ti′, the state of an ith stage shift register Gi is similar to the state of the first stage shift register G1 in time period t1′, and the state of an (i+1)th stage shift register Gi+1 is similar to the state of the second stage shift register G2 in time period t1′. In time period ti+1′, the state of the ith stage shift register Gi is similar to the state of the first stage shift register G1 in time period t2′, and the state of the (i+1)th stage shift register Gi+1 is similar to the state of the second stage shift register G2 in time period t2′. Therefore, the initial output control signal CK01 of the ith stage shift register Gi is used as the first clock signal XCK02 of the (i+1)th stage shift register Gi+1, and the initial output control signal CK02 of the (i+1)th stage shift register Gi+1 is used as the first clock signal XCK01 of the ith stage shift register Gi. The initial output control signals CK01 of shift registers of odd-numbered stages are used as the first clock signals XCK02 of shift registers of even-numbered stages, and the initial output control signals CK02 of the shift registers of even-numbered stages are used as the first clock signals XCK01 of the shift registers of odd-numbered stages.
Furthermore, on the premise that the normal outputting of the initial output signals and the first output signals by the shift registers of all stages can be ensured, it may further allow the shift registers of odd-numbered stages to receive the same first output control signal and the shift registers of even-numbered stages to receive the same first output control signal.
In an exemplary embodiment, reference is made to
It is to be noted that the setting methods of the first output control signal, the initial output control signal, and the first clock signal described above are all exemplary description of the embodiments of the present disclosure, which is not specifically limited in the embodiments of the present disclosure provided that the core inventive point of the embodiments of the present disclosure can be realized.
In one or more embodiments,
The initial output unit 120, the first output unit 131 and the second output unit 132 each receive the signals of the first output node N1 and the second output node N2, so that the signal of the first output node N1 and the signal of the second output node N2 may separately control the initial output signal Vnext output by the initial output unit 120, the first output signal Gout1 output by the first output unit 131, and the second output signal Gout2 output by the second output unit 132. In this case, the initial output signal Vnext output by the initial output unit 120 serves as the input signal Vin of another stage shift register, and the first output signal Gout1 and the second output signal Gout2 may each be used as a control signal of the preset module in the pixel circuit. At this time, the second output signal Gout2 may be different from the first output signal Gout1 so that the first output signal Gout1 and the second output signal Gout2 may respectively be the control signals for controlling the preset modules of the pixel circuits in different rows, or so that the first output signal Gout1 and the second output signal Gout2 may respectively be the control signals for controlling different preset modules in the same pixel circuit. In this manner, it facilitates the reduction in the number of shift registers in the drive circuit, thereby facilitating a reduction in the area occupied by the drive circuit, so that when the drive circuit is set in the non-display region of the display panel, it facilitates the realization of the narrow bezel of the display panel. The structure of the second output unit 132 may be the same as or different from the structure of the first output unit 131, which is not limited in the embodiments of the present disclosure.
In one or more embodiments,
The third output module 1321 at least receives the second output control signal CK2 and the signal of the first output node N1 so that the third output module 1321 may output the second output signal Gout2 under the control of the second output control signal CK2 and the signal of the first output node N1. The fourth output module 1322 at least receives the first voltage signal VGH and the signal of the second output node N2 so that the fourth output module 1322 may output the second output signal Gout2 under the control of the first voltage signal VGH and the signal of the second output node N2. At this time, the first output node N1, the second output node N2, the first voltage signal VGH, and the second output control signal CK2 can determine the polarity and amplitude of the second output signal Gout2.
In an exemplary embodiment, when the signal of the first output node N1 is an active level, the third output module 1321 may control the second output signal Gout2 to be consistent with the second output control signal CK2, and when the signal of the second output node N2 is an active level, the fourth output module 1322 may control the second output signal Gout2 to be consistent with the first voltage signal VGH.
In another embodiment,
With continued reference to
The second voltage signal VGL may control the sixth transistor M23 to maintain the on state continuously, so that the signal of the first output node N1 is substantially consistent with the signal of the second node N12. However, the turned-on sixth transistor M23 has a certain resistance, so that when the signal of the second node N12 electrically connected to the fourth transistor M21 changes, the sixth transistor M23 can reduce the change amount at which the signal of the first output node N1 changes with the signal of the second node N12. Similarly, when the signal of the first output node N1 changes, the sixth transistor M23 can also reduce the change amount at which the signal of the second node N12 changes with the signal of the first output node N1. Thus, by providing the sixth transistor M23 between the first output node N1 and the second node N12, the stability of the signals at the first output node N1 and the second node N12 can be ensured, thereby improving the stability of the second output signal Gout2 output by the fourth transistor M21.
On the basis of the above embodiments, with continued reference to
Furthermore, with reference to
The second output control signal CK2 may be a pulse signal with a pulse change frequency of Fc2 such that the second output control signal CK2 includes a high level and a low level. In this manner, when a high-level second output signal Gout2 is required to be output, the first output node N1 controls the fourth transistor M21 to be turned on when the second output control signal CK2 is a high level, and/or the second output node N2 controls the fifth transistor M22 to be turned on, so that the second output signal Gout2 is consistent with the high level of the second output control signal CK2 and/or the first voltage signal VGH. When it is required to output a low-level second output signal Gout2, the first output node N1 controls the fourth transistor M21 to be turned on when the second output control signal CK2 is a low level, so that the second output signal Gout2 is consistent with the low level of the second output control signal CK2. With this arrangement, the second output signal Gout2 may be a pulse signal having a high level and a low level, thereby meeting the driving requirements of the shift register G.
It may be appreciated that the pulse change frequency Fc2 of the second output control signal CK2 may be the same or different from the pulse change frequency Fc1 of the first output control signal CK1, so that the pulse change frequency of the first output signal Gout1 may be the same as or different from the pulse change frequency of the second output signal Gout2, which is not limited in the embodiments of the present disclosure.
Illustratively, the case that each transistor of the shift register shown in
In the time from instant T2′ to instant T8′, although the input signal Vin is turned to a high level, the first clock signal XCK0 is kept at the high level, so that the high level of the input signal Vin cannot be transmitted to the first output node N1, and the signal of the first output node N1 remains as an active level.
At instant T3′, the initial output control signal CK0 hops to a low level so that the initial output signal Vnext is turned to a low level with the initial output control signal CK0, and at the same time the first output control signal CK1 hops to a low level so that the first output signal Gout1 also hops to a low level with the first output control signal CK1. At instant T4′, the first output control signal CK1 hops to a high level so that the first output signal Gout1 also hops to a high level with the first output control signal CK1. At instant T5′, the second output control signal CK2 hops to a low level so that the second output signal Gout2 also hops to a low level with the second output control signal CK2. At instant T6′, the initial output control signal CK0 hops to a high level, causing the initial output signal Vnext to hop to a high level with the initial output control signal CK0. At instant T7′, the second output control signal CK2 hops to a high level, causing the second output signal Gout2 to also hop to a high level with the second output control signal CK2. At instant T8′, the first clock signal XCK0 hops to a low level again so that the high-level input signal Vin is transmitted to the first output node N1, the signal of the first output node N1 controls the first initial output transistor M01, the first transistor M11 and the fourth transistor M21 to be turned off, so that the initial output signal Vnext no longer changes with the change of the initial output control signal CK0, the first output signal Gout1 no longer changes with the change of the first output control signal CK1, and the second output signal Gout2 no longer changes with the change of the second output control signal CK2, until the input signal Vin is turned to the low level again. In this way, the low-level time of the initial output signal Vnext may overlap the low-level time of the first output signal Gout1 and the low-level time of the second output signal Gout2, and the low level of the first output signal Gout1 and the low level of the second output signal Gout2 shift sequentially, so that the first output signal Gout1 and the second output signal Gout2 respectively controls signal refreshing of pixel circuits in different rows. Therefore, there is no need for providing a shift register G for pixel circuits in each row, the number of shift registers G in the drive circuit can be reduced, the structure of the drive circuit can be simplified, the dimension of the drive circuit can be reduced, and the realization of the narrow bezel of the display panel can be facilitated.
In one or more embodiments, the duration from an instant at which an effective pulse of the initial output control signal of an xth stage shift register starts to an instant at which an effective pulse of the initial output control signal of a yth stage shift register starts is W0, the duration of an effective pulse of the first output control signal of the xth stage shift register is W1, the duration of an effective pulse of the second output control signal of the xth stage shift register is W2, and W0≥(W1+W2).
The case that the shift register shown in
It is to be noted that the above description illustrates simply by taking the case that the pulse change frequency of the first output control signal CK1 is the same as the pulse change frequency of the second output control signal CK2 as an example. However, in the embodiments of the present disclosure, the pulse change frequency of the first output control signal CK1 and the pulse change frequency of the second output control signal CK2 may be set according to practical requirements, which is not limited in the embodiments of the present disclosure.
In one or more embodiments, when the pulse change frequency of the first output control signal CK1 is Fc1 and the pulse change frequency of the second output control signal CK2 is Fc2, within at least a part of the time period of the working process of the display panel, Fc1=Fc2; and/or, within at least another part of the time period of the working process of the display panel, Fc1≠Fc2.
Illustratively,
In another embodiment, when the pulse change frequency of the initial output control signal is Fc0, the pulse change frequency of the first output control signal is Fc1 and the pulse change frequency of the second output control signal is Fc2, within at least a part of the time period of the working process of the display panel, Fc0≥Fc1, and/or Fc0≥Fc2.
For example, with continued reference to
It may be appreciated that the above illustrates simply by taking the case that within at least a part of the time period of the working process of the display panel, the pulse change frequency of the first output control signal CK1 is greater than the pulse change frequency of the second output control signal CK2 as an example. However, in the embodiments of the present disclosure, it may also set the pulse change frequency of the first output control signal CK1 to less than the pulse change frequency of the second output control signal CK2. Moreover, in the above description, it is simply taken as an example that within at least a part of the time period of the working process of the display panel, the pulse change frequency of the initial output control signal CK0 is the same as the pulse change frequency of the first output control signal CK1 and is different from the pulse change frequency of the second output control signal CK2. However, In one or more embodiments of the present disclosure, the pulse change frequency of the initial output control signal CK0 may be different from the pulse change frequency of the first output control signal CK1 and the pulse change frequency of the second output control signal CK2, or the pulse change frequency of the initial output control signal CK0 may be the same only as the pulse change frequency of the second output control signal CK2, which may be designed according to practical requirements and not limited in the embodiments of the present disclosure.
It may further be appreciated that the above illustrates simply by taking the case that when the initial output control signal CK0 has the same pulse change frequency as the first output control signal CK1 and the second output control signal CK2, the time of the active level of the first output signal Gout1 and the time of the active level of the second output signal Gout2 both overlap with the time of the active level of the initial output signal Vnext as an example. However, in other embodiments of the present disclosure, when the initial output control signal CK0 has the same pulse change frequency as the first output control signal CK1 and the second output control signal CK2, the time of the active level of the first output signal Gout1 and the time of the active level of the second output signal Gout2 may also be after the time of the active level of the initial output signal Vnext, which may have the same effect as that in the above embodiments, the reference may be made to the above description for the same parts, which is not repeatedly described here.
In other embodiments,
In one or more embodiments, with continued reference to
The (2m−1)th output module 13m1 may include a (3m−2)th transistor Mm1, a first electrode of the (3m−2)th transistor Mm1 is configured to receive the mth output control signal CKm, a second electrode of the (3m−2)th transistor Mm1 is configured to output the mth output signal Goutm, and a gate of the (3m−2)th transistor Mm1 is connected to the first output node N1 or an mth node N1m. The first output node N1 is directly connected to the mth node N1m, or the first output node N1 is connected to the mth node N1m through an mth stabilization module 13m3, and the mth stabilization module 13m3 may stabilize the signal of the first output node N1 and the signal of the mth node N1m so that the signal of the first output node N1 is substantially the same as the signal of the mth node N1m. In this way, the (3m−2)th transistor Mm1 may be turned on or off under the control of the signal of the first output node N1, and when the signal of the first output node N1 controls the (3m−2)th transistor Mm1 to be turned on, the (3m−2)th transistor Mm1 may output the mth output control signal CKm as the mth output signal Goutm.
Correspondingly, the 2mth output module 13m2 may include a (3m−1)th transistor Mm2, a first electrode of the (3m−1)th transistor Mm2 receives the first voltage signal VGH, a second electrode of the (3m−1)th transistor Mm2 is configured to output the mth output signal Goutm, and a gate of the (3m−1)th transistor Mm2 is connected to the second output node N2. In this way, the (3m−1)th transistor Mm2 may be turned on or off under the control of the second output node N2, and when the signal of the second output node N2 controls the (3m−1)th transistor Mm2 to be turned on, the (3m−1)th transistor Mm2 may output the first voltage signal VGH as the mth output signal Goutm.
In one or more embodiments, when the mth output unit includes the mth stabilization module 13m3, the mth stabilization module 13m3 may include a 3mth transistor Mm3, a first electrode of the 3mth transistor Mm3 is connected to the first output node N1, a second electrode of the 3mth transistor Mm3 is connected to the mth node Nm, and a gate of the 3mth transistor Mm3 receives the second voltage signal VGL.
Furthermore, the mth output unit may further include an mth bootstrap capacitor Cm, the mth bootstrap capacitor Cm may be electrically connected between the second electrode of the (3m−2)th transistor Mm1 and the gate of the (3m−2)th transistor Mm1 so that a sufficiently high driving capacity of the signal at the gate of the (3m−2)th transistor Mm1 for driving the (3m−2)th transistor Mm1 to be turned or off can be ensured.
In one or more embodiments, the duration from the instant at which the effective pulse of the initial output control signal of the xth stage shift register starts to the instant at which the effective pulse of the initial output control signal of the yth stage shift register starts is W0, the duration of the effective pulse of the first output control signal of the xth stage shift register is W1, the duration of the effective pulse of the second output control signal of the xth stage shift register is W2, the duration of the effective pulse of the mth output control signal of the xth stage shift register is Wm, and W0≥Σi=1m Wi.
Illustratively, it is taken as an example that the shift register shown in
In one or more embodiments, within at least a part of the time period of the working process of the display panel, the pulse change frequency Fc1 of the first output control signal CK1 to the pulse change frequency Fcm of the mth output control signal CKm are all equal to each other; or at least two among the pulse change frequency of the first output control signal CK1 to the pulse change frequency of the mth output control signal CKm are not equal.
Illustratively, m equal to 4 is taken as an example. As shown in
When the pulse change frequency of the initial output control signal CK1 is Fc0, and the pulse change frequency of the mth output control signal CKm is FcM, within at least a part of the time period of the working process of the display panel, Fc0≥Fcm.
m equal to 4 is taken as an example. With continued reference to
It may be appreciated that the above description simply takes as an example that the pulse change frequency of the initial output control signal CK0 is greater than the pulse change frequency of the third output control signal CK3 and the pulse change frequency of the fourth output control signal CK4 for illustration. However, in some embodiments of the present disclosure, the pulse change frequency of the initial output control signal CK0 may be greater than any one of the pulse change frequency of the first output control signal CK1, the pulse change frequency of the second output control signal CK2, the pulse change frequency of the third output control signal CK3 and the pulse change frequency of the fourth output control signal CK4, which may be designed according to practical requirements, and is not limited in the embodiments of the present disclosure.
It is to be noted that
Based on the same inventive concept, a display device is further provided according to the embodiments of the present disclosure. The display device includes the display panel according to the embodiments of the present disclosure. Therefore, the display device has technical features of the display panel and the driving method according to the embodiments of the present disclosure, and may achieve beneficial effects of the display panel according to the embodiments of the present disclosure. For the similarities, reference may be made to the foregoing description of the display panel according to the embodiments of the present disclosure, and those similarities are not described herein again.
It should be appreciated that operation processes of the various forms of pixel circuits shown above may be used with the stages reordered, some added, or deleted. For example, the stages in the operation processes of the pixel circuits recorded in the present disclosure may be performed in parallel, may be performed in sequence, or may be performed in different sequences, which is not limited herein as long as the expected result of the technical solutions of the present disclosure can be realized.
The above-mentioned embodiments do not constitute a limitation on the protection scope of the present disclosure. It is to be appreciated by the person skilled in the art that various modifications, combinations, sub-combinations, and substitutions may be made according to design requirements and other factors. Any modifications, equivalent substitutions, improvements and the like within the spirit and principle of the present disclosure shall fall within the protection scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310942643.7 | Jul 2023 | CN | national |
