Patent Grant
12039920
The present disclosure generally relates to the field of display technology and, more particularly, relates to a display panel and a display device.
The frame region of the existing display device includes a peripheral drive circuit for providing drive signals for pixel units in the display region. In the display device, a plurality of pixel units is arranged in the display region, and each pixel unit includes a pixel circuit. All pixel circuits are electrically connected to the peripheral drive circuit at the frame region respectively, and the peripheral drive circuit provides the pixel circuits with scan control signals and light-emitting control signals, thereby controlling the pixel circuits to provide drive currents for light-emitting elements. However, the existing drive circuit may occupy a relatively large space, such that it is difficult to reduce the frame width of the display device.
One aspect of the present disclosure provides a display panel. The display panel includes a base substrate, drive circuits, pixel circuits, and line groups. The drive circuits and the pixel circuits are arranged on the base substrate. The drive circuits provide control signals for the pixel circuits. The pixel circuits provide drive currents for light-emitting elements of the display panel. The drive circuits include a first drive circuit and a second drive circuit. The signal line groups include a first signal line group and a second signal line group. The first signal line group includes M signal lines that provide signals for the first drive circuit. The second signal line group includes N signal lines that provide signals for the second drive circuit, M≥1, and N≥1. In a direction perpendicular to a surface of the display panel, M0 signal lines of the first signal line group overlap with the first drive circuit and are located on a side of the first drive circuit away from the base substrate. N0 signal lines of the second signal line group overlap with the second drive circuit and are located on a side of the second drive circuit away from the base substrate, 1≤M0≤M, and 1≤N0≤N. The first drive circuit includes S1 level shift registers extending along a first direction, and/or the second drive circuit includes S2 level shift registers extending along the first direction, a second direction is in parallel with a plane of the surface of the display panel and perpendicular to the first direction, S1≥2, and S2≥2. The first drive circuit provides a light-emitting control signal for a light-emitting control transistor of the pixel circuit. The second drive circuit provides a control signal for a PMOS transistor of the pixel circuit, or the second drive circuit provides a control signal for an NMOS transistor of the pixel circuit. The M0 signal lines or the N0 signal lines include a first clock signal line that transmits a first clock signal and a second clock signal line that transmits a second clock signal, and a first voltage signal line that transmits a first voltage signal; and a distance between the first clock signal line and the second clock signal line is greater than a distance between the first voltage signal line and the second clock signal line. In some other embodiments, the M0 signal lines or the N0 signal lines include a first voltage signal line that transmits a first voltage signal and a second voltage signal line that transmits a second voltage signal, and a first clock signal line that transmits a first clock signal; and a distance between the first voltage signal line and the second voltage signal line is greater than a distance between the first clock signal line and the second voltage signal line.
Another aspect of the present disclosure provides a display panel. The display panel includes a base substrate, drive circuits, pixel circuits, and signal line groups. The drive circuits and the pixel circuits are arranged on the base substrate. The drive circuits provide control signals for the pixel circuits. The pixel circuits provide drive currents for light-emitting elements of the display panel. The drive circuits include a first drive circuit and a second drive circuit. The signal line groups include a first signal line group and a second signal line group. The first signal line group includes M signal lines that provide signals for the first drive circuit. The second signal line group includes N signal lines that provide signals for the second drive circuit, M≥1, and N≥1. In a direction perpendicular to a surface of the display panel, M0 signal lines of the first signal line group overlap with the first drive circuit and are located on a side of the first drive circuit away from the base substrate. N0 signal lines of the second signal line group overlap with the second drive circuit and are located on a side of the second drive circuit away from the base substrate, 1≤M0≤M, and 1≤N0≤N. The first drive circuit includes S1 level shift registers extending along a first direction. The second drive circuit includes S2 level shift registers extending along the first direction, a second direction is in parallel with a plane of the surface of the display panel and perpendicular to the first direction, S1≥2, and S2≥2. The M0 signal lines or the N0 signal lines include a first clock signal line that transmits a first clock signal and a second clock signal line that transmits a second clock signal, and a first voltage signal line that transmits a first voltage signal; and a distance between the first clock signal line and the second clock signal line is greater than a distance between the first voltage signal line and the second clock signal line. In some other embodiments, the M0 signal lines or the N0 signal lines include a first voltage signal line that transmits a first voltage signal and a second voltage signal line that transmits a second voltage signal, and a first clock signal line that transmits a first clock signal; and a distance between the first voltage signal line and the second voltage signal line is greater than a distance between the first clock signal line and the second voltage signal line.
Another aspect of the present disclosure provides a display device, including a display panel. The display panel includes a base substrate, drive circuits, pixel circuits, and signal line groups. The drive circuits and the pixel circuits are arranged on the base substrate. The drive circuits provide control signals for the pixel circuits. The pixel circuits provide drive currents for light-emitting elements of the display panel. The drive circuits include a first drive circuit and a second drive circuit. The signal line groups include a first signal line group and a second signal line group. The first signal line group includes M signal lines that provide signals for the first drive circuit. The second signal line group includes N signal lines that provide signals for the second drive circuit, M≥1, and N≥1. In a direction perpendicular to a surface of the display panel, M0 signal lines of the first signal line group overlap with the first drive circuit and are located on a side of the first drive circuit away from the base substrate. N0 signal lines of the second signal line group overlap with the second drive circuit and are located on a side of the second drive circuit away from the base substrate, 1≤M0≤M, and 1≤N0≤N. The first drive circuit includes S1 level shift registers extending along a first direction, and/or the second drive circuit includes S2 level shift registers extending along the first direction, a second direction is in parallel with a plane of the surface of the display panel and perpendicular to the first direction, S1≥2, and S2≥2. The first drive circuit provides a light-emitting control signal for a light-emitting control transistor of the pixel circuit. The second drive circuit provides a control signal for a PMOS transistor of the pixel circuit, or the second drive circuit provides a control signal for an NMOS transistor of the pixel circuit. The M0 signal lines or the N0 signal lines include a first clock signal line that transmits a first clock signal and a second clock signal line that transmits a second clock signal, and a first voltage signal line that transmits a first voltage signal; and a distance between the first clock signal line and the second clock signal line is greater than a distance between the first voltage signal line and the second clock signal line. In some other embodiments, the M0 signal lines or the N0 signal lines include a first voltage signal line that transmits a first voltage signal and a second voltage signal line that transmits a second voltage signal, and a first clock signal line that transmits a first clock signal; and a distance between the first voltage signal line and the second voltage signal line is greater than a distance between the first clock signal line and the second voltage signal line.
Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
Compared with the existing technology, the display panel and the display device provided by the present disclosure may achieve at least the following beneficial effects.
In order to more clearly explain various embodiments of the present disclosure, the drawings required for describing the embodiments or the existing technology are briefly introduced hereinafter. Obviously, the drawings in the following description are merely some embodiments of the present disclosure. Other drawings may also be obtained by those skilled in the art without any creative work according to provided drawings.
Various embodiments of the present disclosure are described clearly and completely in conjunction with the drawings in various embodiments of the present disclosure. Obviously, described embodiments are only a part of various embodiments of the present disclosure, rather than all embodiments. Based on various embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of the present disclosure.
As described above, the frame region of the existing display device includes a peripheral drive circuit for providing drive signals for pixel units in the display region. In the display device, a plurality of pixel units is arranged in the display region, and each pixel unit includes a pixel circuit. All pixel circuits are electrically connected to the peripheral drive circuit at the frame region respectively, and the peripheral drive circuit provides the pixel circuits with scan control signals and light-emitting control signals, thereby controlling the pixel circuits to provide drive currents for light-emitting elements. However, the existing drive circuit may occupy a relatively large space, such that it is difficult to reduce the frame width of the display device.
Various embodiments of the present disclosure provide a display panel and a display device, which may effectively solve the technical problems existing in the existing technology and ensure that the frame width of the display device is relatively small.
In order to achieve the above-mentioned objectives, the technical solutions provided by various embodiments of the present disclosure are described in detail with reference to
Referring to
The display panel may include a display region AA and a frame region NA. The pixel circuits 20 and the light-emitting elements 30 may be disposed in the display region AA, and the drive circuits may be disposed in the frame region NA. The drive circuits may include the first drive circuit 11 and the second drive circuit 12.
The drive circuits may be at the frame region NA. The display panel may include signal line groups, and the signal line groups may include the first signal line group and the second signal line group. The first signal line group may include M signal lines that provide signals for the first drive circuit 11, the second signal line group may include N signal lines that provide signals for the second drive circuit 12, M≥1, and N≥1. In addition, along the direction perpendicular to the surface of the display panel (i.e., along the direction perpendicular to the light-exiting direction of the display panel), M0 signal lines 110 in the first signal line group may overlap the first drive circuit 11, N0 signal lines 120 in the second signal line group may overlap the second drive circuit 12, 1≤M0≤M, and 1≤N0≤N.
The first drive circuit 11 may include S1 level shift registers extending along the first direction Y, the second drive circuit 12 may include S2 level shift registers extending along the first direction Y, and the first drive circuit 11 and the second drive circuit 12 may be arranged along the second direction X. The second direction X may be in parallel with the plane of the surface of the display panel and perpendicular to the first direction Y, S1≥2, and S2≥2.
Along the second direction X, the width of the first drive circuit 11 is W1, the width of the second drive circuit 12 is W2, the total width of the M0 signal lines 110 in the first signal line group is D1, the total width of the N0 signal lines 120 in the second signal line group is D2, W2>W1, D2>D1, and D2/W2>D1/W1.
It can be understood that the M0 signal lines may overlap the first drive circuit and the N0 signal lines may overlap the second drive circuit, where the extension direction of the M0 signal lines and the extension direction of the N0 signal lines may be the first direction, which may reduce the area occupied by a part of the signal lines and reduce the frame width of the display device.
Along the second direction, when the widths of the drive circuits and the widths of the signal lines are wider, the frame of the display panel becomes larger. In order to reduce the frame, the signal lines and the drive circuits may normally be configured to be overlapped with each other to reduce the frame. When there are more than one set of drive circuits in the frame, how to configure the frame to sufficiently reduce the frame may be a problem. In order to solve the above-mentioned problem, the inventor of the present application found that when W2>W1, D2>D1, by setting D2/W2>D1/W1, the width of the signal line overlapped by the drive circuit with a relatively large width may also be relatively large. In such way, the width occupied by the drive circuit with a relatively large width and its connected signal line on the display panel may be sufficiently reduced, and the drive circuit with a relatively large width and the drive circuit with a relatively small width may achieve a desirable overlapping relationship with their respective signal lines to sufficiently reduce the frame. Therefore, in various embodiments of the present disclosure, the relationship between the width W1 of the first drive circuit, the width W2 of the second drive circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines may be configured as W2>W1, D2>D1, and D2/W2>D1/W1. The overlapping configuration of each of the shift register with a relatively large width and the shift register with a relatively small width and the total width of the respective corresponding signal line may be further optimized, the occupied area of the drive circuit and the signal lines may be sufficiently reduced, and the frame width of the display device may be further reduced.
In one embodiment of the present disclosure, the display panel provided by the present disclosure may be a single-sided drive panel structure. As shown in
As shown in
It can be understood that the first drive circuits on different sides of the display region (defined as the first drive circuit on the first side and the first drive circuit on the second side) may each include a plurality of cascaded shift registers; the level one shift register of the first drive circuit on the first side and the level one shift register of the first drive circuit on the second side may be both electrically connected to the pixel circuits of the first row; the level two shift register of the first drive circuit on the first side and the level two shift register of the first drive circuit on the second side may be both electrically connected to the pixel circuits of the second row, and so on; and the last level shift register of the first drive circuit on the first side and the last level shift register of the first drive circuit on the second side may be both electrically connected to the pixel circuits of the last row. Similarly, the second drive circuits on different sides of the display region (defined as the second drive circuit on the first side and the second drive circuit on the second side) may each include a plurality of cascaded shift registers; the level one shift register of the second drive circuit on the first side and the level one shift register of the second drive circuit on the second side may be both electrically connected to the pixel circuits of the first row; the level two shift register of the second drive circuit on the first side and the level two shift register of the second drive circuit on the second side may be both electrically connected to the pixel circuits of the second row, and so on; and the last level shift register of the second drive circuit on the first side and the last level shift register of the second drive circuit on the second side may be both electrically connected to the pixel circuits of the last row.
Or, as shown in
It can be understood that the first drive circuits at odd-numbered levels in the first drive circuits may be located on the first side of the display region, and the first drive circuits at even-numbered levels in the first drive circuits may be located on the second side of the display region, where the first drive circuits at odd-numbered levels may be correspondingly electrically connected to the pixel circuits at odd-numbered rows, and the first drive circuits at even-numbered levels may be correspondingly electrically connected to the pixel circuits at even-numbered rows. Similarly, the second drive circuits at odd-numbered levels in the second drive circuits may be located on the first side of the display region, and the second drive circuits at even-numbered levels in the second drive circuits may be located on the second side of the display region, where the second drive circuits at odd-numbered levels may be correspondingly electrically connected to the pixel circuits at odd-numbered rows, and the second drive circuits at even-numbered levels may be correspondingly electrically connected to the pixel circuits at even-numbered rows.
In one embodiment of the present disclosure, the display panel provided by the present disclosure may include a base substrate, and the drive circuits and the pixel circuits may be located on the base substrate; the M0 signal lines may be located on the side of the first drive circuits away from the base substrate; the N0 signal lines may be located on the side of the second drive circuits away from the base substrate; the M0 signal lines may be located on a same layer, and/or the N0 signal lines may be located on a same layer. As shown in
As shown in
In one embodiment of the present disclosure, the widths of the signal lines and the drive circuits may be further optimized, and the width of the frame region of the display panel may be further optimized to realize the narrow frame. Along the second direction, the total width of the M signal lines is D11, and the total width of the N signal lines is D22, where [(W1−D11)−(W2−D22)]×[(D11−D1)−(D22−D2)]≤0.
It can be understood that, for the width of the first drive circuit W1, the width of the second drive circuit W2, the total width of the M signal lines D11, the total width of the M0 signal lines D1, the total width of the N signal lines D22, and the total width of the N0 signal lines D2 which are provided in various embodiments of the present disclosure, the relatively large value between (W1−D11) and (W2−D22) may indicate that the difference between the total width of the signal lines and the width of the corresponding drive circuit may be relatively large, and the total width of the signal lines may be smaller compared with the width of the corresponding drive circuit; and at this point, the region where the drive circuit is located may have more space for arranging signal lines that overlap the drive circuit. Furthermore, since the region of the corresponding drive circuit (the first drive circuit or second drive circuit) can overlap more signal lines, the drive circuit may correspond to the relatively small value of (D11−D1) and (D22−D2). Such configuration may fully save the frame region of the display panel, avoid unnecessary waste of space, and be beneficial for the narrow frame design. Optionally, (D11−D1)=(D22−D2)=0 may be provided in various embodiments of the present disclosure, that is, the M signal lines may all overlap the first drive circuit, and the N signal lines may all overlap the second drive circuit, which may reduce the width of the frame region of the display panel to the greatest extent and ensure narrower frame of the display panel.
As shown in
It can be understood that, in various embodiments of the present disclosure, the relationship between the width W1 of the first drive circuit, the width W2 of the second drive circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines may be W2>W1, D2>D1, and D2/W2>D1/W1. Therefore, the quantity of overlapping N0 signal lines with the second drive circuit may be more by configuring the relationship between the quantity of N0 signal lines and the quantity of M0 signal lines to be N0−M0≥1, which may achieve the objective of reducing the frame region width.
As shown in
It should be noted that each of the signal line i and the signal line j provided in various embodiments of the present disclosure may be a single signal line, or a combination of multiple signal lines, which may not be limited in the present disclosure. When each of the signal line i and the signal line j is a combination of multiple signal lines, the width of each of the signal line i and the signal line j may be the total width of included signal lines.
It can be understood that the width W2 of the second drive circuit may be greater than the width W1 of the first drive circuit; compared with the transistors in the shift register of the first drive circuit, the transistors in the shift register of the second drive circuit may occupy a relatively large area; and the output requirement of the shift register in the second drive circuit may be higher in most cases. Therefore, in order to ensure the accuracy and stability of the transmission signal and output signal of the second drive circuit, the second drive circuit may need to be connected to wider signal lines to reduce the voltage drop on the signal lines, thereby avoiding large fluctuation in the signals transmitted on the signal lines. In the technical solutions provided by various embodiments of the present disclosure, the width W2 of the second drive circuit may be relatively large, and the signal line j with the relatively large width and the second drive circuit may be designed to be overlapped with each other along the light-exiting direction of the display panel, which, under the premise of ensuring normal output of the second drive circuit, may prevent the signal line j from affecting the width of the frame region of the display panel and ensure the relatively small width of the display panel.
In one embodiment of the present disclosure, the signal line i (i.e., 11i) and the signal line j (i.e., 12j) provided by the present disclosure may be both clock signal lines; the first drive circuit 11 may provide light-emitting control signals for the light-emitting control transistors of the pixel circuits 20; and the second drive circuit 12 may provide control signals for the p-channel metal-oxide semiconductor (PMOS)-type transistors in the pixel circuits 20, where Dj/W2>Di/W1.
Referring to
Referring to
Referring to
It can be understood that the signal line j provided by various embodiments of the present disclosure may be related to the output control and other related control processes of the second drive circuit. Therefore, the signal line j may be substantially configured as a combination of the signal line j1 and the signal line j2; and the signal line j2 may be configured on the side of the signal line j1 facing the display region. Moreover, the output terminal of the drive circuit may be normally configured on the side facing the display region, thereby being electrically connected to the pixel circuit in the display region; and the signal line j2 may be connected to the output module of the shift register. Therefore, the width of the signal line j2 may be designed to be relatively large to ensure the transmission stability of the signal accessed to the output module, and Dj2 may be designed to be greater than Dj1. In addition, based on above-mentioned configuration, the width relationship may also be configured as Dj1≥Di and/or Dj2≥Di, and furthermore, it may satisfy that the transmission stability of the signal accessed by the shift register of the second drive circuit with a relatively large width is high. Meanwhile, the width W2 of the second drive circuit provided by various embodiments of the present disclosure is larger, such that the wider signal line j may be configured to be overlapped with the second drive circuit, thereby achieving the narrow frame design.
In one embodiment of the present disclosure, the signal line i and the signal line j provided by the present disclosure may also be other types of signal lines. That is, the signal line i (11i) and the signal line j provided by the present disclosure may also be both high-level voltage signal lines or low-level voltage signal lines. The first drive circuit 11 may provide light-emitting control signals for the light-emitting control transistors of the pixel circuit 20. Optionally, the second drive circuit 12 may provide control signals for the n-channel metal-oxide semiconductor (NMOS)-type transistors in the pixel circuit 20, and the NMOS-type transistors may be connected to the gate electrodes of the drive transistors, where Dj/W2>Di/W1. The drive transistor may be a transistor used to provide a drive current in the pixel circuit 20, and the light-emitting element in the pixel circuit 20 may emit light in response to the drive current.
The shift register of the first drive circuit provided by various embodiments of the present disclosure may have the circuit structure of the shift register as shown in
Referring to
As shown in
It can be understood that the signal line j provided by various embodiments of the present disclosure may be related to the output and other related control processes of the second drive circuit. Therefore, the signal line j may be substantially configured as a combination of the signal line j1 and the signal line j2; and the signal line j2 may be configured on the side of the signal line j1 facing the display region. Moreover, the output terminal of the drive circuit may be on the side of the drive circuit facing the display region, thereby being electrically connected to the pixel circuit in the display region, and the signal line j2 may be connected to the output module of the shift register. Therefore, the width of the signal line j2 may be designed to be relatively large to ensure the transmission stability of the signal accessed by the output module, and Dj2 may be designed to be greater than Dj1. In addition, based on above-mentioned configuration, the width relationship may also be configured as Dj1≥Di and/or Dj2≥Di, and furthermore, it may satisfy that the transmission stability of the signal accessed by the shift register of the second drive circuit with relatively large width is high. Meanwhile, the width W2 of the second drive circuit provided by various embodiments of the present disclosure is larger, such that the wider signal line j may be configured to be overlapped with the second drive circuit, thereby achieving the narrow frame design.
In one embodiment of the present disclosure, the level one shift register of the first drive circuit provided by the present disclosure may include x1 transistors and y1 capacitors, x1≥1, and y1≥1; the level one shift register of the second drive circuit may include x2 transistors and y2 capacitors, x1≥1, and y2≥1; at least one of the M0 signal lines may overlap at least one of the x1 transistors, and may not overlap any one of the y1 capacitors; and/or at least one of the N0 signal lines may overlap at least one of the x2 transistors, and may not overlap any one of the y2 capacitors.
It can be understood that the signal line may be configured to transmit signals. When the signal line overlaps the capacitor, it is equivalent to connecting a new capacitor to the original capacitor which in turn causes the capacitance value to change. It may not only affect the capacitor, but also affect the signal transmission stability on the signal line. Therefore, the shift register in the first drive circuit and the shift register in the second drive circuit provided by various embodiments of the present disclosure may both include a plurality of transistors and at least one capacitor; and in the signal lines that overlap the drive circuits (the first drive circuit and/or the second drive circuit), at least one signal line may only overlap the transistor and may not overlap the capacitor, which may ensure both the signal transmission stability on the signal line and the capacitor reliability in the drive circuit.
Referring to
In addition, the N0 signal lines in the shift register of the second drive circuit may include the start signal line STV2, the clock signal line CK2, the clock signal line XCK2, the low-level voltage signal line VGL, and the high-level voltage signal line VGH. The start signal line STV2, the clock signal line CK2, the clock signal line XCK2, the low-level voltage signal line VGL, and the high-level voltage signal line VGH may all overlap the transistors included in the shift register; and the start signal line STV2, the clock signal line CK2, the low-level voltage signal line VGL, and the clock signal line XCK2 may not overlap the capacitor included in the shift register, which may both improve the capacitance value change of the capacitor in the shift register and ensure high transmission signal stability on the signal line.
Furthermore, in the M0 signal lines provided by various embodiments of the present disclosure, at least one clock signal line may not overlap any one of the y1 capacitors; and/or in the N0 signal lines, at least one clock signal line may not overlap any one of the y2 capacitors. It can be understood that the clock signal line may transmit a pulse signal; and the pulse signal may not only be easily affected by the capacitor, but the pulse signal may also affect the charging and discharging process of the capacitor. Therefore, in the present disclosure, the clock signal line and the capacitor may be designed to be not overlapped with each other, which may effectively ensure high stability of pulse signal transmission on the clock signal line and high reliability of the capacitor. As shown in
In one embodiment of the present disclosure, in the M0 signal lines provided by the present disclosure, the signal line with the largest width along the second direction may not overlap any one of the y1 capacitors; and/or in the N0 signal lines, the signal line with the largest width along the second direction may not overlap any one of the y2 capacitors. The size of the capacitor is proportional to the relative area of the plate. Therefore, the signal line with a relatively large width and the capacitor may be configured to be not overlapped with each other, which may avoid large capacitance value change of the capacitor in the drive circuit and ensure high signal transmission stability of the signal line and high reliability of the capacitor.
As shown in
It can be understood that the pulse signals transmitted by the clock signal line CKL and the clock signal line XCKL may be out of phase. Therefore, the distance between the clock signal line CKL and the clock signal line XCKL may need set to be relatively large, which may avoid that the electric fields generated between each other may have relatively large influence on the respective pulse signals when the signals on the clock signal line CKL and the clock signal line XCKL jump. However, the first voltage signal line VG1 may transmit a constant voltage signal, which does not have rising and falling edges. Therefore, the influence may be relatively small when the distance between the first voltage signal line VG1 and the clock signal line is small; and the distance L2 between the first voltage signal line VG1 and the second clock signal line XCKL may be set to be less than the distance L1 between the first clock signal line CKL and the second clock signal line XCKL, thereby optimizing the wire layout space.
As shown in
It can be understood that the first voltage signal line VG1 and the second voltage signal line VG2 provided in various embodiments of the present disclosure may transmit voltage signals of different levels. That is, when the first voltage signal line VG1 is a high-level voltage signal line, the second voltage signal line VG2 may be a low-level voltage signal line; and when the first voltage signal line VG1 is a low-level voltage signal line, the second voltage signal line VG2 may be a high-level voltage signal line. Therefore, in order to have high signal transmission stability for the voltage signal line VG1 and the second voltage signal line VG2, the distance between the first voltage signal line VG1 and the second voltage signal line VG2 may be configured to be relatively large in the present disclosure to avoid the mutual influence between the two signal lines which may make respective transmission signal stability relatively poor and result in unstable output signal of the drive circuit.
As shown in
It can be understood that the drive circuits provided by various embodiments of the present disclosure may include the first drive circuit, the second drive circuit, and the third drive circuit. The width W2 of the second drive circuit may be greater than the width W3 of the third drive circuit; and the width W3 of the third drive circuit provided by various embodiments of the present disclosure may be between the width W1 of the first drive circuit and the width W2 of the second drive circuit, where the total width D3 of the P0 signal lines 130 provided by various embodiments of the present disclosure may be relatively large, such that D3/W3>D2/W2>D1/W1.
When the width W3 of the third drive circuit is less than the width of the second drive circuit W2 and the output requirement of the third drive circuit is relatively high, the widths of a part of signal lines in the corresponding P signal lines may be relatively wide. In order not to affect the frame space, the second drive circuit may need to be configured to overlap the third drive circuit as possible. The situation at this point may be that W3 is not excessively large, but D3 is relatively large, such that D3/W3>D2/W2>D1/W1. At this point, since D3 is relatively large, that is, the P0 signal lines of the P signal lines may be configured to overlap the third drive circuit, thereby without increasing the frame region.
As shown in
It should be noted that the pixel circuit provided by various embodiments of the present disclosure may include the drive transistor, the light-emitting control transistor, and other NMOS-type transistors and PMOS-type transistors. The drive transistor may be configured to generate a drive current, and the light-emitting element in the pixel circuit may emit light in response to the drive circuit. The light-emitting control transistor may be configured to transmit the drive current to the light-emitting element according to the control of the light-emitting control signal. The other NMOS-type transistors and PMOS-type transistors may be configured for the control including resetting the pixel circuit, obtaining the threshold value of the drive transistor, and the like, which may be same as the existing technology and may not be described in detail in the present disclosure.
In one embodiment of the present disclosure, the display panel provided by the present disclosure may be a single-sided drive panel structure. As shown in
As shown in
Or, as shown in
In one embodiment of the present disclosure, along the second direction X, the width of the output transistor of the first drive circuit 11 may be less than the width of the output transistor of the third drive circuit 13; and the width of the output transistor of the third drive circuit 13 may be less than the width of the output transistor of the second drive circuit 12. The output transistor may be a transistor connected to the output terminal of the shift register and may be configured to output related control signals to the output terminal of the shift register. Referring to
It should be noted that the shift registers shown in the first drive circuit, the second drive circuit, and the third drive circuit provided by various embodiments of the present disclosure may not be limited to the shift registers shown in
In one embodiment of the present disclosure, the relationship, provided by the present disclosure, of the width of the first drive circuit W1, the width of the second drive circuit W2, the width of the third drive circuit W3, the total width of the M0 signal lines D1, the total width of the N0 signal lines D2, and the total width of the P0 signal lines D3 may be (D3/W3−D2/W2)<(D2/W2−D1/W1). The shift registers in the second drive circuit and the third drive circuit may have relatively high requirement for output signals, while the shift register in the first drive circuit may have relatively low requirement for output signals. Therefore, in the present disclosure, the values of D3/W3 and D2/W2 may be designed to be relatively close with each other to fully avoid increased frame region problem caused by corresponding signal lines having relatively wide widths.
In one embodiment of the present disclosure, the relationship between the M0 signal lines, the N0 signal lines, and the P0 signal lines provided by the present disclosure may be set as M0<P0<N0. In various embodiments of the present disclosure, the width of the second drive circuit may be greater than the width of the third drive circuit, the width of the third drive circuit may be greater than the width of the first drive circuit, and the number of signal lines may be further configured as M0<P0<N0. The number of signal lines corresponding to the second drive circuit are relatively large, or the widths of the signal lines corresponding to the second drive circuit are relatively wide; therefore, N0 may be configured to be relatively large to effectively prevent the second drive circuit and its corresponding signal lines from occupying excessive frame region. The width of the third drive circuit is less than the width of the second drive circuit. If the output requirement of the third drive circuit is relatively high, the number of corresponding signal lines may also be relatively large, or the widths of the signal lines may be relatively large. Therefore, P0 may be configured to be relatively large to effectively prevent the second drive circuit and its corresponding signal lines from occupying excessive frame region. The first drive circuit itself has a small width, and there may not be excessive space to overlap the corresponding signal lines. Therefore, M0 may be configured to be relatively small; and such configuration may ensure the optimization of the overlapping between the signal lines and the drive circuit and may reduce the frame width of the display panel.
In one embodiment of the present disclosure, the M0 signal lines provided by the present disclosure may include the third clock signal line for transmitting the third clock signal; the N0 signal lines may include the fourth clock signal line for transmitting the fourth clock signal; and the P0 signal lines may include the fifth clock signal line for transmitting the fifth clock signal. The width of the third clock signal line may be less than the width of the fifth clock signal line, and the width of the fifth clock signal line may be less than the width of the fourth clock signal line. The width of the second drive circuit provided by various embodiments of the present disclosure may be greater than the width of the third drive circuit, and the width of the third drive circuit may be greater than the width of the first drive circuit. Furthermore, the width of the third clock signal line may be designed to be less than the width of the fifth clock signal line, and the width of the fifth clock signal line may be designed to be less than the width of the fourth clock signal line, which may ensure the match of the corresponding clock signal lines of different drive circuits and improve the stability and reliability of signals transmitted by different clock signal lines.
In one embodiment of the present disclosure, the M0 signal lines provided by the present disclosure may include the third voltage signal line for transmitting the third voltage signal; the N0 signal lines may include the fourth voltage signal line for transmitting the fourth voltage signal; and the P0 signal lines may include the fifth voltage signal line for transmitting the fifth voltage signal. The width of the third voltage signal line may be less than the width of the fourth voltage signal line, and the width of the fourth voltage signal line may be less than the width of the fifth voltage signal line. The width of the second drive circuit provided by various embodiment of the present disclosure may be greater than the width of the third drive circuit, and the width of the third drive circuit may be greater than the width of the first drive circuit. Furthermore, the width of the third voltage signal line may be designed to be less than the width of the fourth voltage signal line, and the width of the fourth voltage signal line may be designed to be less than the width of the fifth voltage signal line, which may ensure the match of the corresponding clock signal lines of different drive circuits and improve the stability and reliability of signals transmitted by different clock signal lines.
Correspondingly, various embodiments of the present disclosure also provide a display device, including the display panel provided in any one of the above-mentioned embodiments.
As shown in
In other embodiments of the present disclosure, the display device provided by the present disclosure may also be an electronic display device such as a mobile phone, a computer, a vehicle-mounted terminal, and the like, which may not be limited by the present disclosure.
Various embodiments of the present disclosure provide the display panel and the display device. The M0 signal lines may be overlapped with the first drive circuit, and the N0 signal lines may be overlapped with the second drive circuit, which may reduce the area occupied by a part of the signal lines and reduce the frame width of the display device. Furthermore, in various embodiments of the present disclosure, the relationship between the width W1 of the first drive circuit, the width W2 of the second drive circuit, the total width D1 of the M0 signal lines, and the total width D2 of the N0 signal lines may be configured as W2>W1, D2>D1, and D2/W2>D1/W1. The overlapping configuration of each of the shift register with a relatively large width and the shift register with a relatively small width and the total width of the respective corresponding signal line may be further optimized, the occupied area of the drive circuit and the signal lines may be sufficiently reduced, and the frame width of the display device may be further reduced.
The above-mentioned description of disclosed embodiments may make those skilled in the art implement or use the present disclosure. Various modifications to such embodiments may be obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure may not be limited to various embodiments shown in the present disclosure but should conform to the widest scope consistent with the principles and novel features disclosed in the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202111063932.7 | Sep 2021 | CN | national |
This application is a continuation of application Ser. No. 17/646,584, filed on Dec. 30, 2021, which claims the priority of Chinese patent application No. 202111063932.7, filed on Sep. 10, 2021, the entirety of all of which is incorporated herein by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 9276017 | Lee | Mar 2016 | B2 |
| 10177172 | Wu | Jan 2019 | B2 |
| 10586495 | Kobayashi | Mar 2020 | B2 |
| 11164532 | Kwon | Nov 2021 | B2 |
| 11194414 | Lee | Dec 2021 | B2 |
| 11314349 | Lee | Apr 2022 | B2 |
| 20150187810 | Lee | Jul 2015 | A1 |
| 20170345845 | Wu | Nov 2017 | A1 |
| 20180026218 | Kobayashi | Jan 2018 | A1 |
| 20210026477 | Lee | Jan 2021 | A1 |
| 20210026478 | Lee | Jan 2021 | A1 |
| 20210193764 | Cho | Jun 2021 | A1 |
| 20210202683 | Lee | Jul 2021 | A1 |
| 20210225980 | Xu | Jul 2021 | A1 |
| 20210295780 | Ikeda | Sep 2021 | A1 |
| 20210335754 | Zhu | Oct 2021 | A1 |
| 20220057912 | Yang | Feb 2022 | A1 |
| 20220077273 | Qing | Mar 2022 | A1 |
| 20220122546 | Long | Apr 2022 | A1 |
| 20220123087 | Yu | Apr 2022 | A1 |
| 20220165202 | Chen | May 2022 | A1 |
| 20230162658 | Zou | May 2023 | A1 |
| Number | Date | Country |
|---|---|---|
| 108630144 | Oct 2018 | CN |
| 111091776 | May 2020 | CN |
| Number | Date | Country | |
|---|---|---|---|
| 20230169912 A1 | Jun 2023 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17646584 | Dec 2021 | US |
| Child | 18158698 | US |
