Patent Grant
12175922
Embodiments of the present disclosure relate to a display technology and, in particular, to a display panel and a display device.
In a display panel, a pixel circuit provides a displaying-required drive current for a light-emitting element of the display panel and controls whether the light-emitting element enters a light emission stage. A pixel circuit is an indispensable element in most self-luminous display panels.
However, in an existing display panel, the internal characteristics of a drive transistor in a pixel circuit change slowly as the service time increases, causing the threshold voltage of the drive transistor to drift, thereby affecting the overall characteristics of the drive transistor and thus affecting the display uniformity.
Embodiments of the present disclosure provide a display panel and a display device.
One aspect of embodiments of the present disclosure provides a display panel.
The display panel includes a pixel circuit and a light-emitting element.
The pixel circuit includes a data write module, a drive module and a compensation module.
The drive module includes a drive transistor.
The data write module is connected to an input terminal of the drive module.
A first electrode of the compensation module is connected to an output terminal of the drive module, and a second electrode of the compensation module is connected to a control terminal of the drive module.
The data write module includes a data write transistor and a bias transistor, the data write transistor is connected to a data signal input terminal and configured to transmit a data signal, and the bias transistor is connected to a bias signal input terminal and configured to transmit a bias signal.
An operation of the pixel circuit includes a bias stage, during the bias stage, the data write module and the drive module are on, the compensation module is off, and the data write module provides the bias signal;
Within a duration of one frame of the display panel, the operation process of the pixel circuit includes a pre-stage and a light emission stage, and with a duration of at least one frame, the pre-stage includes the bias stage.
The pre-stage includes a reset stage and the bias stage, and in the reset stage, a reset module provides a reset signal for a gate of the drive transistor; or the pre-stage includes the bias stage and a data write stage, and in the data write stage, the data write module provides a data signal for a gate of the drive transistor.
Based on the same inventive concept, embodiments of the present disclosure further provide a display device. The display device includes the preceding display panel.
In order that technical solutions in embodiments of the present disclosure or the related art are described more clearly, drawings to be used in the description of the embodiments or the related art are briefly described hereinafter. Apparently, while the drawings in the description are some embodiments of the present disclosure, for those skilled in the art, these drawings may be expanded and extended to other structures and drawings according to the basic concepts of the device structure, driving method and manufacturing method disclosed and indicated in embodiments of the present disclosure. These are undoubtedly all within the scope of the claims of the present disclosure.
In order that the objects, technical solutions and advantages of the present disclosure are clearer, the technical solutions of the present disclosure are described more clearly and completely hereinafter with reference to drawings of embodiments of the present disclosure and in conjunction with implementations. Apparently, the embodiments described herein are some embodiments, not all embodiments, of the present disclosure. All other embodiments obtained by those skilled in the art based on the basic concepts disclosed and indicated in embodiments of the present disclosure are within the scope of the present disclosure.
As shown in
It is to be noted that
In this embodiment, the pixel circuit 10 includes the data write module 11. The input terminal of the data write module 11 receives the data signal Vdata. The control terminal of the data write module 11 receives a scan signal S1. The output terminal of the data write module 11 is electrically connected to the input terminal of the drive module 12. The scan signal S1 received by the pixel circuit 10 is a pulse signal. The active pulse of the scan signal S1 controls the transmission path of the input terminal and the output terminal of the data write module 11 to turn on so that the data signal is provided for the drive module 12. The inactive pulse of the scan signal S1 controls the transmission path of the input terminal and the output terminal of the data write module 11 to turn off. Thus, under the control of the scan signal S1, the data write module 11 selectively provides the data signal for the drive module 12.
The pixel circuit 10 includes the drive module 12. The output terminal of the drive module 12 is coupled to the light-emitting element 20. The drive module 12 includes the drive transistor T0. After the drive transistor T0 is turned on, the drive module 12 provides the drive current for the light-emitting element 20. The source of the drive transistor T0 is electrically connected to the input terminal of the drive module 12. The drain of the drive transistor T0 is electrically connected to the output terminal of the drive module 12. In this embodiment, the data write module 11 is connected to the source of the drive transistor T0. In other embodiments, the drain of the drive transistor is electrically connected to the input terminal of the drive module, and the source of the drive transistor is electrically connected to the output terminal of the drive module. It is to be understood that the source and the drain of the transistor are not constant, but vary with the drive state of the transistor.
The pixel circuit 10 includes the compensation module 13. The compensation module 13 is configured to compensate for the threshold voltage of the drive transistor T0. The first electrode of the compensation module 13 is electrically connected to the output terminal of the drive module 12. The control terminal of the compensation module 13 receives a scan signal S2. The second electrode of the compensation module 13 is electrically connected to the control terminal of the drive module 12. The scan signal S2 received by the pixel circuit 10 is a pulse signal. The active pulse of the scan signal S2 controls the transmission path of the first electrode and the second electrode of the compensation module 13 to turn on to adjust the voltage between the control terminal of the drive module 12 and the output terminal of the drive module 12 and to compensate for the threshold voltage of the drive transistor T0. The inactive pulse of the scan signal S2 controls the transmission path of the first electrode and the second electrode of the compensation module 13 to turn off. Thus, under the control of the scan signal S2, the compensation module 13 selectively compensates for the threshold voltage of the drive module 12.
In an embodiment, the data write module 11 includes a first transistor T1 whose source is configured to receive the data signal Vdata and whose drain is connected to the source of the drive transistor T0; the compensation module 13 includes a second transistor T2 whose source is connected to the drain of the drive transistor T0 and whose drain is connected to the gate of the drive transistor T0. The gate of the first transistor T1 is configured to receive a scan signal S1. The gate of the second transistor T2 is configured to receive a scan signal S2.
In a non-bias stage such as a light emission stage, the gate potential of the drive transistor may be greater than the drain potential of the drive transistor. This setting, if maintained for a long time, may result in the polarization of ions inside the drive transistor and the formation of a built-in electric field inside the drive transistor, causing the threshold voltage of the drive transistor to continuously increase.
In this embodiment, the bias stage is added to the operation of the pixel circuit 10. During the bias stage, as shown in
In some embodiments, the potential difference between of the drive transistor T0 the gate potential and the drain potential of the drive transistor T0 may be adjusted during the bias stage so that the effect on the internal characteristics of the drive transistor T0 can balance the effect on the internal characteristics of the drive transistor in the non-bias stage in which the gate potential of the drive transistor T0 is greater than the drain potential of the drive transistor, that is, the decrease in the threshold voltage of the drive transistor T0 during the bias stage can balance the increase in the threshold voltage of the drive transistor in the non-bias stage, ensuring that the Id-Vg curve does not drift, thereby ensuring the display uniformity of the display panel.
In embodiments of the present disclosure, the operation of the pixel circuit includes the bias stage. During the bias stage, the data write module and the drive module are on, the compensation module is off, and the data signal is written to the drain of the drive transistor through the turned-on data write module and drive module to adjust the drain potential of the drive transistor so as to ameliorate the potential difference between the gate potential of the drive transistor and the drain potential of the drive transistor. It is known that the pixel circuit includes at least one non-bias stage. When the drive current is generated in the drive transistor, the gate potential of the drive transistor may be greater than the drain potential of the drive transistor, causing the I-V curve of the drive transistor to drift, which in turn, causes the threshold voltage of the drive transistor to drift. During the bias stage, the gate potential and the drain potential of the drive transistor are adjusted so that the drift of the I-V curve of the drive transistor in the non-bias stage can be balanced, the threshold voltage drift of the drive transistor can be reduced, and the display uniformity of the display panel can be ensured.
Referring to
In an embodiment, the light emission control module 14 includes a third transistor T3. The third transistor T3 is connected between the drive transistor T0 and the light-emitting element 20. As shown in
In this embodiment, the gate of the third transistor T3 receives a light emission control signal EM. Under the control of the light emission control signal EM, the third transistor T3 is turned on or off. The operation of the pixel circuit 10 includes the light emission stage. During the light emission stage, the light emission control signal EM outputs an active pulse so that the third transistor T3 is on, and the drive current provided by the drive transistor T0 flows into the light-emitting element 20 to cause the light-emitting element 20 to emit light. In the non-light emission stage, the light emission control signal EM outputs an inactive pulse so that the third transistor T3 is off, and the light-emitting element 20 does not emit light. The non-light emission stage of the pixel circuit 10 includes the bias stage. During the bias stage, the compensation module 13 and the third transistor T3 are off, and the data signal is written to the drain of the drive transistor T0 to adjust the drain potential of the drive transistor T0, to change the potential difference between the drain potential of the drive transistor T0 and the gate potential of the drive transistor T0, and to bias the drive transistor T0.
In an embodiment, the pixel circuit 10 further includes an initialization module 15. The initialization module 15 is configured to selectively provide an initialization signal Vini for the light-emitting element 20. In some embodiments, during the bias stage, the initialization module 15 is not on. In some other embodiments, in at least part of the time period of the bias stage, the initialization module 15 is on.
In this embodiment, the input terminal of the initialization module 15 receives the initialization signal Vini, the output terminal of the initialization module 15 is electrically connected to the light-emitting element 20, and the control terminal of the initialization module 15 receives a scan signal S4. In an initialization stage, the scan signal S4 provides an active pulse for the pixel circuit 10 so that the initialization module 15 is on, the initialization signal Vini is written to the light-emitting element 20 of the pixel circuit 10, and the initialization signal Vini is initialized. The initialization signal Vini is generally a negative voltage signal, so the anode of the light-emitting element 20 has a negative initial voltage in the initialization stage. In at least part of the time period of the bias stage, the initialization module 15 is on, and the anode of the light-emitting element 20 has an initial voltage.
During the bias stage, the initialization module 15 is on so that the light-emitting element 20 receives the initialization signal. During the bias stage, the data signal is written to the drain of the drive transistor T0, and the transistor may have a certain leakage current although T3 is off. Therefore, if the light-emitting element 20 does not receive the initialization signal, the light-emitting element 20 may run the risk of emitting light covertly. Nevertheless, the light-emitting element 20 is initialized during the bias stage so that it is further ensured that the light-emitting element does not emit light.
In the pixel circuit 10 of this embodiment, an initialization module 15 includes a fourth transistor T4 whose source is configured to receive an initialization signal Vini, whose drain is connected to the anode of a light-emitting element 20 and whose gate is configured to receive a scan signal S4.
The reset module 16 includes a fifth transistor T5. As shown in
The light emission control module 14 further includes a sixth transistor T6 connected between the drive transistor T0 and a supply voltage terminal PVDD. During the bias stage, the third transistor T3 and the sixth transistor T6 are off. The gate of the sixth transistor T6 receives a light emission control signal EM, the source of the sixth transistor T6 receives a PVDD signal, and the drain of the sixth transistor T6 is connected to the source of the drive transistor T0.
In one embodiment, each of transistors T0, T1, T3, T4 and T6 is a PMOS formed using polysilicon as the active layer, and each of transistors T2 is an NMOS formed using an oxide semiconductor as the active layer. It is understood that the active pulse of the scan signal of the NMOS transistor is a high-level signal, and the active pulse of the scan signal of the PMOS transistor is a low-level signal. It is to also be understood that the pixel circuits shown in
In this embodiment, the width-to-length ratio of the channel region of the NMOS transistor is greater than the width-to-length ratio of the channel region of the PMOS transistor. In the present application, the NMOS transistor mainly functions as a switching transistor and requires a rapid response capability. A transistor having a larger width-to-length ratio has a channel region of a shorter length and thus has a better response capability.
Additionally, in the present application, the four scan signals S1, S2, S3 and S4 may be different signals. In some particular cases, if the timing satisfies certain conditions, at least two of the four signals S1, S2, S3 and S4 may be the same signal. For example, when T4 and T5 are transistors of the same type, such as PMOS or NMOS, S3 and S4 may be the same signal. The particular situation depends on the specific circuit structure and timing and is not limited in this embodiment.
Based on any one of the preceding exemplary embodiments, the display panel includes k rows of light-emitting elements. During the operation of a pixel circuit corresponding to the ith row of light-emitting elements, during the bias stage, the data write module is on, and the data signal written to the drain of the drive transistor is a current data signal on a data signal line to which the pixel circuit is connected; and the current data signal is a data signal written by a pixel circuit corresponding to the jth row of light-emitting elements in a data write stage.
k≥1, 1≤i≤k, and 1≤j≤k.
The values of i and j depend on a data writing process of the display panel. In one case, data signals are written line by line in the display panel. In this case, j=i−1, or j=i+1. In another case, the same data write stage of the display panel relates to multiple rows of light-emitting elements 20. For example, from the a-th row of light-emitting elements to the b-th row of light-emitting elements, the data signal is written in the same data write stage. 1≤a≤k, and 1≤b≤k. In this case, the values of j and i may depend on the particular situation, i may be equal to j or may be not equal to j, and this is not limited in this embodiment. It is to be noted that here the data signal written in the data write stage refers to a data signal written to the gate of the drive transistor T0 in the data write stage.
Optionally, in this embodiment, during the bias stage, the drain voltage of the drive transistor T0 is greater than the gate voltage of the drive transistor T0. In the non-bias stage such as the light emission stage, the drain voltage of the drive transistor T0 may be less than the gate voltage of the drive transistor T0, causing the threshold voltage of the drive transistor T0 to drift. Nevertheless, the threshold voltage drift in the non-bias stage can be balanced if the drain voltage of the drive transistor T0 is set greater than the gate voltage of the drive transistor T0 during the bias stage.
The operation of the pixel circuit further includes at least a non-bias stage; during the bias stage, the drive transistor has a gate voltage of Vg1, a source voltage of Vs1 and a drain voltage of Vd1; and in the non-bias stage, the drive transistor has a gate voltage of Vg2, a source voltage of Vs2 and a drain voltage of Vd2.
|Vg1−Vd1|<|Vg2−Vd2|.
In this case, a reduction in the potential difference between the gate potential of the drive transistor T0 and the drain potential of the drive transistor T0 can alleviate the threshold voltage drift caused by the potential difference between the gate potential of the drive transistor T0 and the drain potential of the drive transistor T0 in the non-bias stage.
Additionally, in some implementations of this embodiment, (Vg1−Vs1)×(Vg2−Vs2)<0, or (Vg1−Vd1)×(Vg2−Vd2)<0.
During the operation of the pixel circuit, if the data signal is written to the drain of the drive transistor through the source of the drive transistor, then the gate voltage and the drain voltage of the drive transistor satisfy (Vg1−Vd1)×(Vg2−Vd2)<0. In the non-bias stage, the gate voltage of the drive transistor in the pixel circuit is greater than the drain voltage of the drive transistor, that is, Vg2>Vd2, then Vg2−Vd2>0. During the bias stage, the data signal is written to the drain of the drive transistor so that the gate voltage of the drive transistor is less than the drain voltage of the drive transistor, that is, Vg1<Vd1, then Vg1−Vd1<0, and (Vg1−Vd1)×(Vg2−Vd2)<0.
In other embodiments, during the operation of the pixel circuit, if the data signal is written to the source of the drive transistor through the drain of the drive transistor, the gate voltage and the source voltage of the drive transistor satisfy (Vg1−Vs1)×(Vg2−Vs2)<0. In the non-bias stage, the gate voltage of the drive transistor in the pixel circuit is greater than the source voltage of the drive transistor, that is, Vg2>Vs2, then Vg2−Vs2>0. During the bias stage, the data signal is written to the source of the drive transistor so that the gate voltage of the drive transistor is less than the source voltage of the drive transistor, that is, Vg1<Vs1, then Vg1−Vs1<0, and (Vg1−Vs1)×(Vg2−Vs2)<0.
In this embodiment, the duration of the non-bias stage such as the light emission stage of the display panel is relatively long; therefore, in order that the threshold voltage drift in the non-bias stage is sufficiently balanced during the bias stage and in order that the bias stage is prevented from consuming too much time, the following setting may be performed: Vd1−Vg1>Vg2−Vd2>0. In this manner, Vd1−Vg1 during the bias stage is sufficiently large so that the desired bias effect can be achieved during the bias stage as soon as possible. In other embodiments, if the source and the drain of the drive transistor are switched, the following setting may be performed: Vs1−Vg1>Vg2−Vs2>0, depending on the particular situation of the circuit.
In some embodiment, the bias stage has a duration of t1, and the non-bias stage has a duration of t2.
(|Vg1−Vs1|−|Vg2−Vs2|)×(t1−t2)<0, or (|Vg1−Vd1|−|Vg2−Vd2|)×(t1−t2)<0
In this embodiment, during the bias stage, the data signal is written to the drain of the drive transistor through the source of the drive transistor so that the drain voltage of the drive transistor is greater than the gate voltage of the drive transistor, that is, Vg1−Vd1<0; in the non-bias stage, the gate voltage of the drive transistor is greater than the drain voltage of the drive transistor, that is, Vg2−Vd2>0. In the process of biasing the drive transistor, if the bias voltage is relatively large, the bias duration may be appropriately reduced; if the bias voltage is relatively small, the bias duration may be appropriately prolonged.
Based on this, if |Vg1−Vd1|−|Vg2−Vd2|>0, then the bias voltage is relatively large. In this case, the duration of the bias stage may be appropriately reduced that is, t1<t2, so that the difference between the threshold voltage during the bias stage and the threshold voltage in the non-bias stage is reduced. If |Vg1−Vd1|−|Vg2−Vd2|<0, then the bias voltage is relatively small. In this case, the duration of the bias stage may be appropriately prolonged, that is, t1>t2, so that the difference between the threshold voltage during the bias stage and the threshold voltage in the non-bias stage is reduced.
In other embodiments, during the bias stage, the data signal is written to the source of the drive transistor through the drain of the drive transistor, and the gate and the drain of the drive transistor during the bias stage and the non-bias stage satisfy (|Vg1−Vs1|−|Vg2−Vs2|)×(t1−t2)<0, thereby reducing the threshold voltage drift in the non-bias stage.
It is to be noted that a contrast between the bias stage and the non-bias stage in the preceding embodiments, especially a contrast related to durations, generally refers to a contrast between a continuous bias stage and a continuous non-bias stage.
In this embodiment, the duration of the bias stage is greater than 5 microseconds and, in particular, may be greater than 20 microseconds. The inventors of the present application have verified that when the duration of the bias stage is greater than 5 microseconds, especially greater than 20 microseconds, the threshold voltage drift can be effectively alleviated; when the duration of the bias stage is less than 5 microseconds, the duration of the bias stage is so short that the bias state of the drive transistor T0 is not adjusted sufficiently, so the threshold voltage drift cannot be effectively alleviated.
The non-bias stage is the light emission stage of the display panel. Exemplarily, in one light emission stage, the drive transistor T0 has a source voltage of 4.6 V, a gate voltage of 3 V and a drain voltage of 1 V. The gate voltage of the drive transistor is greater than the drain voltage of the drive transistor. The drive transistor is biased during the bias stage so that the threshold voltage drift of the drive transistor during the light emission stage can be compensated.
In this embodiment, for the duration of one frame of the display panel, the operation of the pixel circuit includes the pre-stage and the light emission stage. In some cases, the pre-stage and the light emission stage may be performed sequentially. In the duration of one frame of at least one frame, the pre-stage of the pixel circuit includes the bias stage. During the bias stage, the data signal is written to the drain of the drive transistor through the source of the drive transistor, and the potential difference between the gate potential of the drive transistor and the drain potential of the drive transistor is adjusted. In some cases, the drain voltage of the drive transistor may be set greater than the gate voltage of the drive transistor so that the drive transistor is biased. In the non-bias stage, the gate voltage of the drive transistor is greater than the drain voltage of the drive transistor, resulting in an increase in the threshold voltage of the drive transistor. Thus, the non-bias stage is added to the pixel circuit in the duration of one frame of at least one frame to at least partially balance the increase in the threshold voltage of the drive transistor in the non-bias stage, thereby improving the display uniformity of the display panel.
As shown in
With reference to the pixel circuit 10 shown in
During the bias stage, the scan signal S1 outputs a low-level active pulse, and the first transistor T1 is on. In this embodiment, the second transistor is an oxide semiconductor and is an NMOS transistor, the scan signal S2 outputs a low-level active pulse, the second transistor T2 is off, the drive transistor T0 is on, the data signal is written to the drain of the drive transistor T0, and the drain potential of the drive transistor T0 is adjusted.
The bias stage has a duration of t1, and the reset stage has a duration of t3. t1>t3.
During the reset stage, only the reset signal is written to the gate of the drive transistor so that the gate of the drive transistor is reset to a negative potential of less than 0 V; therefore, the duration t3 of the reset stage can be relatively small. During the bias stage, the data signal is written to the drain of the drive transistor so that the potential difference between the gate potential of the drive transistor and the drain potential of the drive transistor can be adjusted so that the drive transistor can be biased, and the threshold voltage drift of the drive transistor during the light emission stage can be reduced. Because the duration of the non-bias stage such as the light emission stage is relatively long, the duration t1 of the bias stage is relatively long so that the threshold voltage drift in the non-bias stage is sufficiently reduced. Based on this, the following setting is performed: t1>t3.
In an embodiment, as shown in
As shown in
The bias stage has a duration of t1, the reset stage has a duration of t3, and the first interval stage has a duration of t4, where t1>t4, or t3>t4. It is to be understood that the reset stage is used only for reset of the gate voltage of the drive transistor, and the first interval stage is used for stabilization of the drive transistor, so the duration t3 of the reset stage and the duration t4 of the first interval stage can be as short as a reaction duration; therefore, the following setting is performed: t1>t4, or t3>t4. In one embodiment, t4≤t½, so the duration t4 of the first interval stage can be short enough to ensure the duration of the pre-stage not to be too long.
As shown in
In the pixel circuit shown in
During the reset stage, the second transistor T2 is off, the fifth transistor T5 is on, and the reset signal Vref is written to the gate of the drive transistor T0. During the overlapping stage in which the bias stage overlaps the reset signal, the second transistor T2 is off, the first transistor T1 is on, and the data signal Vdata is written to the drain of the drive transistor T0; meanwhile, the fifth transistor T5 is on, and the reset signal Vref is continuously written to the gate of the drive transistor T0 so that the gate voltage of the drive transistor T0 can be stabilized. During the non-overlapping stage in which the bias stage does not overlap the reset signal, the fifth transistor T5 is off, the first transistor T1 is on, and the data signal Vdata is written to the drain of the drive transistor T0.
During the bias stage, if the gate of the drive transistor T0 receives a low-level reset signal, and the data signal Vdata is written to the drain of the drive transistor T0, then both the gate potential and the drain potential can be adjusted so that the threshold voltage drift caused by the setting in which the gate potential is greater than the drain potential in the non-bias stage can be better alleviated.
As shown in
As shown in
As shown in
As shown in
As shown in
The first reset signal and the second reset signal have the same potential. In other embodiments, the first reset signal and the second reset signal have different potentials. In some optional embodiments, the first reset signal lowers the gate potential of the drive transistor, so the first reset signal is less than 0V; the second reset signal stabilizes the gate potential of the drive transistor during the bias stage to increase the bias effect. Based on this, the second reset signal may be the same as or different from the first reset signal. Related practitioners may flexibly design the pixel circuit to satisfy different design requirements.
In an embodiment, the absolute value of the potential of the first reset signal is greater than the absolute value of the potential of the second reset signal; and the drive transistor is a PMOS transistor, and the potential of the first reset signal is lower than the potential of the second reset signal; or the drive transistor is an NMOS transistor, and the potential of the first reset signal is higher than the potential of the second reset signal. Optionally, the absolute value of the potential of the first reset signal is greater than the absolute value of the potential of the second reset signal so that on the basis that the second reset signal plays a biasing role during the bias stage, the power consumption of the pixel circuit can be reduced by using the second reset signal having a lower potential absolute value.
In another embodiment, the absolute value of the potential of the first reset signal is less than the absolute value of the potential of the second reset signal; and the drive transistor is a PMOS transistor, and the potential of the second reset signal is lower than the potential of the first reset signal; or the drive transistor is an NMOS transistor, and the potential of the second reset signal is higher than the potential of the first reset signal. The absolute value of the potential of the first reset signal is less than the absolute value of the potential of the second reset signal. In a particular case of the display panel, for example, in the case of high-frequency driving, during the reset stage, the level of the first reset signal is a negative potential whose absolute value is relatively small so that the time of the data write stage can be shortened, thereby facilitating high-frequency driving.
As shown in
As shown in
In this embodiment, in the data write stage, the scan signal S1 outputs an active pulse signal so that the data write module is on, and the drive module is on; the scan signal S2 outputs an active pulse signal so that the compensation module is on. Then, the data signal is written to the control terminal of the drive module, that is, the gate of the drive transistor, through the turned-on data write module, drive module and compensation module.
The bias stage has a duration of t1, and the data write stage has a duration of t5, where t1>t5. It is to be understood that the data write stage is used only for writing the data signal to the gate of the drive transistor and thus can be as short as a reaction duration; during the bias stage, the data signal is written to the drain of the drive transistor, the drive transistor is biased, and the threshold voltage drift of the drive transistor during the light emission stage is reduced, and the duration of the light emission stage is relatively long, so the duration t1 of the bias stage is relatively long, so that the threshold voltage drift in the non-bias stage is sufficiently reduced. Based on this, the following setting is performed: t1>t5.
As shown in
As shown in
The bias stage has a duration of t1, the data write stage has a duration of t5, and the second interval stage has a duration of t6, where t1>t6, or t5>t6. It is to be understood that the data write stage is used only for writing the data signal to the gate of the drive transistor, and the second interval stage is a transition stage used for stabilization of the drive transistor, so the duration t5 of the data write stage and the duration t6 of the second interval stage can be as short as a reaction duration; therefore, the following setting is performed: t1>t6, or t5>t6. In one embodiment, t6≤t½, so the duration t6 of the second interval stage can be short enough to ensure the duration of the pre-stage not to be too long.
As shown in
In this embodiment, in the pre-stage of the pixel circuit, first the gate of the drive transistor is reset so that the gate voltage of the drive transistor is pulled down to a negative voltage lower than 0 V, thereby facilitating subsequent biasing of the drive transistor; then, the data signal is written to the drain of the drive transistor, the drive transistor is biased, and the threshold voltage drift of the drive transistor in the non-bias stage is reduced; finally, in the data write stage, the data write module, the drive module and the compensation module are all on, and the data signal is written to the gate of the drive transistor.
The bias stage has a duration of t1, the reset stage has a duration of t3, and the data write stage has a duration of t4, where t1>t3, and t1>t4. For the duration of one frame, the threshold voltage of the drive transistor is caused to drift in the non-bias stage, but the duration of the non-bias stage is relatively long, so in order that the threshold voltage drift of the drive transistor in the non-bias stage is reduced, the duration of the bias stage is set to be relatively long; the data write stage is used only for writing the data signal to the gate of the drive transistor, so the duration of the data write stage is set to be relatively short; the reset stage is used only for writing the reset signal to the gate of the drive transistor, so the duration of the reset stage is set to be relatively short. Based on this, the following settings are performed: t1>t3, and t1>t4.
Referring to
As shown in
In other embodiments, as shown in
As shown in
One third interval stage is a transition stage between sub-bias stages, so the duration of the third interval stage can be less than the duration of one sub-bias stage. In particular, the duration of any third interval stage is less than the duration of any sub-bias stage. It is to be understood that the durations of the multiple third interval stages may be the same or different, or the durations of the multiple third interval stages satisfy rules such as progressive increase or progressive decrease. In embodiments of the present disclosure, the design of the bias stage of the pixel circuit is not limited to the preceding situation and is flexible according to the bias requirements of the pixel circuit in different cases.
As shown in
In the case where the duration of the first sub-bias stage is greater than the duration of each of others of the m sub-bias stages, during the bias stage, the drive transistor is biased in the first sub-bias stage so that the threshold voltage drift of the drive transistor in the non-bias stage can be effectively reduced; subsequently, the drive transistor is biased supplementally and adjusted dynamically according to the bias situation in other sub-bias stages of a shorter duration so that the threshold voltage drift of the drive transistor in the non-bias stage can be sufficiently reduced in the multiple sub-bias stages, thereby ensuring that the duration of the bias stage is not too long.
In an embodiment, in connection with
In accordance with any of the exemplary embodiments, one data write cycle of the display panel includes S refreshed frames that include a data write frame and a retention frame, where S>0. The data write frame includes a data write stage in which the data write module writes the data signal to the gate of the drive transistor. The retention frame includes no data write stage. At least the data write frame includes the bias stage. In the data write frame, new display data is written to the pixel circuit. In the retention frame, the pixel circuit is normally refreshed, but the display data of the previous frame is retained, and no new display data is written. In the duration of the data write frame, during the bias stage, the data write module and the drive module are on, the compensation module is off, the data signal is written to the drain of the drive transistor from the source of the drive transistor, and the voltage between the gate of the drive transistor and the drain of the drive transistor is biased.
Referring to
Referring to
The display panel includes multiple second data write frames. In one second data write frame, the duration of the bias stage is t8; and during the bias stage, the voltage between the gate of the drive transistor and the drain of the drive transistor is biased, and thus the threshold voltage drift of the drive transistor can be reduced. In practical application, the threshold voltage drift of the drive transistor cannot be reduced to zero during the bias stage of one second data write frame, so the internal characteristics of the drive transistor may be changed after the display panel displays multiple second data write frames for a long time. Based on this, the duration of the bias stage in one first data write frame is set to t7. The duration of the bias stage in one first data write frame is increased so that the threshold voltage drift of the drive transistor accumulated until the current frame is reduced. In this manner, the display effect is improved, and thus the display uniformity is improved.
In some embodiments, the second data write frame may not include the bias stage, that is, t8=0. In this case, not all data write frames require the bias stage, and the bias stage may be set in only the first data write frame, thereby simplifying the driving process of the display panel.
Referring to
Referring to
It is understood that in this embodiment, it is feasible to configure only the pre-stage of the data write frame to include the bias stage and configure the pre-stage of the retention frame not to include the bias stage. In this case, if the bias problem can be solved by using only the data write frame, the bias stage is not required in the retention frame. Alternatively, it is feasible to configure only the pre-stage of the retention frame to include the bias stage and configure the pre-stage of the data write frame not to include the bias stage. The data write frame also assumes the work of the reset stage and the data write stage, so if the retention frame can fully assume the work of the bias stage, it is not needed to configure the bias stage in the data write frame, thereby simplifying the timing of the data write frame.
Additionally, it is understood that in the preceding drawings, the description is given using an example in which the initialization stage of the light-emitting element at least partially overlaps the reset stage or the bias stage, but this embodiment is not limited to the preceding situation. In some other embodiments, it is feasible that the initialization stage may not overlap the bias stage; or the initialization stage may be performed throughout the bias stage and still performed when the bias stage ends. The design may be flexible depending on the particular situation of the circuit.
Another aspect of embodiments of the present disclosure provides a display panel. As shown in
Here the bias signal Vbias may be a data signal Vdata provided on a data signal line connected to the pixel circuit 10 or may be an additional bias signal provided by a driver chip. Any bias signal that can be written to the drain of the drive transistor to adjust the bias state of the drive transistor when the data write module and the drive module are on and the compensation module is off is within the scope of this embodiment.
Shown in
In an embodiment, during the bias stage, the potential of the bias signal Vbias is greater than the potential of the gate of the drive transistor T0 so that the potential of the drain of the drive transistor T0 is raised, and the threshold voltage drift caused by the potential difference between the gate potential of the drive transistor T0 and the drain potential of the drive transistor T0 is alleviated.
It is understood that
For the driving mode in the driving process of other embodiments, reference may be made to the driving mode of any one of the preceding embodiments as long as the data signal during the bias stage is replaced with a bias signal. All these are within the scope of the embodiments. Based on this, referring to
Embodiments of the present disclosure further provide a driving method of a display panel. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module and a compensation module. The data write module is configured to selectively provide a data signal for the drive module. The drive module is configured to provide a drive current for the light-emitting element and includes a drive transistor. The compensation module is configured to compensate for the threshold voltage of the drive transistor.
as Also as shown in
For the driving method of other embodiments, reference may be made to the driving method used in the driving process of any one of the preceding embodiments. The same content is not repeated in this embodiment. All these are within the scope of the driving method of this embodiment.
In embodiments of the present disclosure, the operation of the pixel circuit includes a bias stage. During the bias stage, the data write module and the drive module are on, the compensation module is off, and the data signal is written to the drain of the drive transistor through the turned-on data write module and drive module to adjust the drain potential of the drive transistor so as to ameliorate the potential difference between the gate potential of the drive transistor and the drain potential of the drive transistor. It is known that the pixel circuit includes at least one non-bias stage. When a drive current is generated in the drive transistor, the gate potential of the drive transistor may be greater than the drain potential of the drive transistor, leading the I-V curve of the drive transistor to shift, causing the threshold voltage of the drive transistor to drift. During the bias stage, the gate potential and the drain potential of the drive transistor are adjusted so that the shift of the I-V curve of the drive transistor in the non-bias stage can be balanced, the threshold voltage drift of the drive transistor can be reduced, and the display uniformity of the display panel can be ensured.
Embodiments of the present disclosure further provide a display device. The display device includes the display panel of any one of the preceding embodiments. Optionally, the display panel is an organic light-emitting display panel or a microLED display panel.
As shown in
In an embodiment, the control terminal of the data write module 11 is connected to a first scan signal terminal and configured to receive a first scan signal S1. The first scan signal S1 is configured to control the data write module 11 to turn on and off. Further, the data write module 11 includes a first transistor T1 whose gate is connected to the first scan signal terminal, whose source is connected to the data signal input terminal and whose drain is connected to the source of the drive transistor T0. The control terminal of the compensation module 13 is connected to a second scan signal terminal and configured to receive a second scan signal S2. The second scan signal S2 is configured to control the compensation module 13 to turn on and off. Further, the compensation module 13 includes a second transistor T2 whose gate is connected to the second scan signal terminal, whose source is connected to the drain of the drive transistor T0 and whose drain is connected to the gate of the drive transistor T0. The control terminal of the reset module 16 is connected to a third scan signal terminal and configured to receive a third scan signal S3. The third scan signal S3 is configured to control the reset module 16 to turn on and off. Further, the reset module 16 includes a fifth transistor T5 whose gate is connected to the third scan signal S3, whose source is connected to the reset signal terminal and whose drain is connected to the drain of the drive transistor T0.
In this embodiment, the reset module also serves as the bias module. On the one hand, the reset module can provide a reset signal for the gate of the drive transistor during the reset stage. On the other hand, the reset module can provide a bias signal for the drain of the drive transistor during the bias stage. The display panel includes the non-bias stage such as the light emission stage, so when the drive transistor is on, the gate potential of the drive transistor may be higher than the drain potential of the drive transistor. This may cause the Id-Vg curve of the drive transistor to drift, as shown in
Referring to
Optionally, the control terminal of the first light emission control module 141 is connected to a light emission control signal terminal and configured to receive a light emission control signal EM for controlling the first light emission control module 141 to turn on and off. Further, the first light emission control module 141 includes a sixth transistor T6 whose gate is connected to the light emission control signal terminal, whose source is connected to the first power signal terminal and whose drain is connected to the source of the drive transistor T0; the control terminal of the second light emission control module 142 is connected to the light emission control signal terminal and configured to receive a light emission control signal EM for controlling the second light emission control module 142 to turn on and off. Further, the second light emission control module 142 includes a third transistor T3 whose gate is connected to the light emission control signal terminal, whose source is connected to the drain of the drive transistor T0 and whose drain is connected to the light-emitting element 20.
As shown in
In an embodiment, the control terminal of the initialization module 15 is connected to a fourth scan signal terminal and configured to receive a fourth scan signal S4 for controlling the initialization module 15 to turn on and off. Further, the initialization module 15 includes a fourth transistor T4 whose gate is connected to the fourth scan signal terminal, whose source is connected to the initialization signal terminal and whose drain is connected to the light-emitting element 20.
In an embodiment, he drive transistor T0 is a PMOS transistor, and the voltage of the bias signal Vbias is higher than the voltage of the reset signal Vref. During the reset stage, the gate voltage of the drive transistor T0 needs to be reset sufficiently to ensure that the drive transistor T0 is on. Therefore, the reset signal Vref is generally a low-level signal. During the bias stage, the drain voltage of the drive transistor T0 needs to be appropriately raised to slow down the threshold voltage drift of the drive transistor T0. Therefore, generally, the voltage of the bias signal Vbias is set higher than the voltage of the reset signal Vref. Based on this, the signal received by the reset signal terminal is switched between the reset signal Vref and the bias signal Vbias. For ease of description, the signal received by the reset signal terminal is collectively referred to as V0.
In an embodiment, the operation of the pixel circuit 10 further includes at least a non-bias stage; during the bias stage, the drive transistor 10 has a gate voltage of Vg1, a source voltage of Vs1 and a drain voltage of Vd1; and in the non-bias stage, the drive transistor has a gate voltage of Vg2, a source voltage of Vs2 and a drain voltage of Vd2.
In some embodiments, |Vg1−Vd1|<|Vg2−Vd2| so that the difference between the gate voltage of the drive transistor T0 and the drain voltage of drive transistor T0 during the bias stage is less than the difference between the gate voltage of the drive transistor T0 and the drain voltage of the drive transistor T0 in the non-bias stage, thereby alleviating the threshold voltage drift of the drive transistor T0.
In some other embodiments, (Vg1−Vd1)×(Vg2−Vd2)<0 so that the potential difference between the gate potential of the drive transistor and the drain potential of the drive transistor T0 in the non-bias stage is reversed during the bias stage, thereby effectively balancing the problem of threshold voltage drift of the drive transistor T0 caused in the non-bias stage.
Further, optionally, Vd1−Vg1>Vg2−Vd2>0. Here the difference Vd1−Vg1 is set larger, the potential difference between the gate potential of the drive transistor and the drain potential of the drive transistor T0 in the non-bias stage is balanced by a larger reverse potential difference during the bias stage, thereby shortening the time of the bias stage.
In an embodiment, if the bias stage has a duration of t1, and the non-bias stage has a duration of t2, then (|Vg1−Vd1|−|Vg2−Vd2|)×(t1−t2)<0. Here, if |Vg1−Vd1| is greater than |Vg2−Vd2|, that is, the reverse potential difference used for biasing is larger, then the time of the bias stage may be set less than the non-bias stage; if |Vg1−Vd1| is less than |Vg2−Vd2|, that is, the reverse potential difference used for biasing is smaller, then the time of the bias stage may be set longer than the non-bias stage. The purpose of the preceding design is to sufficiently counteract, during the bias stage, the problem of threshold voltage drift of the drive transistor caused in the non-bias stage and to prevent other problems caused by the excessive progress of the bias stage.
In the preceding embodiments, the non-bias stage is the light emission stage of the display panel. During the light emission stage, the drive transistor T0 provides the drive current for the light-emitting element 20. In the pixel circuit shown in
In an embodiment, for the duration of one frame of the display panel, the operation of the pixel circuit includes a pre-stage and a light emission stage; and in the duration of one frame of at least one frame, the pre-stage of the pixel circuit includes the bias stage.
When the reset stage ends, the compensation module 13 is turned off. Here, when the compensation module 13 is turned off, that is, at the falling edge of the second scan signal S2, the VO signal at the reset signal terminal rises from the low-level Vref to a relatively-high-level signal Vbias. At this time, the reset module 16 is turned on, the pixel circuit 10 enters the bias stage, and the reset signal terminal provides the bias signal Vbias for the drain of the drive transistor T0. Here, the bias stage is performed at the end of the reset stage so that the duration of the pre-stage is shortened.
In an embodiment, as shown in
In an embodiment, as shown in
In an embodiment, as shown in
In an embodiment, the duration of the reset stage is less than the duration of the bias stage. This setting is performed for the following reason: The reset stage is set such that the reset signal is written to the gate of the drive transistor, not requiring too long a time; the bias stage is set such that the threshold voltage drift in the non-bias stage is counteracted, requiring a certain duration in which the desired effect can be achieved. Additionally, in the case as shown in
In the preceding embodiments, the reset stage is set before the bias stage; the gate potential of the drive transistor T0 is reset to a relatively-low-level signal through the reset signal Vref, and then the drain potential of the drive transistor T0 is raised to a relatively-high-level signal through the bias signal Vbias. In this manner, during the bias stage, the purpose of lowering the gate potential of the drive transistor T0 on the one hand and raising the drain potential of the drive transistor T0 on the other hand is achieved. The adjustment is made from two aspects, thereby improving the potential difference between the gate of the drive transistor T0 and the drain of the drive transistor T0, increasing the effect of the bias stage and sufficiently counteracting the threshold voltage drift of the drive transistor T0 in the non-bias stage.
Referring to
Two bias stages are shown in exemplary
In an embodiment, one data write cycle of the display panel includes S refreshed frames that include a data write frame and a retention frame, where S>0. The data write frame includes a data write stage in which the data write module writes the data signal to the gate of the drive transistor. The retention frame includes no data write stage.
In one implementation, the pre-stage of at least one data write frame includes the bias stage. In this case, as shown in
In an embodiment, if the duration of the pre-stage is T11, and the sum of the durations of all the bias stages in the pre-stage is T22, as verified by the inventors, when T22≤⅔×T11, the following problem can be avoided: The bias stage occupies too long a time of the pre-stage, resulting in an increase in the duration of the pre-stage and a decrease in the refresh rate of the display panel, thereby affecting the display effect.
In another embodiment, the pre-stage of at least one retention frame includes the bias stage. In this case, the pre-stage may include the bias stage and does not include the data write stage. The pre-stage may further include a reset stage, as shown in
It is to be understood that in such embodiment, it is feasible to configure only the pre-stage of the data write frame to include the bias stage and configure the pre-stage of the retention frame not to include the bias stage. In this case, if the bias problem can be solved by using only the data write frame, the bias stage is not required in the retention frame. Alternatively, it is feasible to configure only the pre-stage of the retention frame to include the bias stage and configure the pre-stage of the data write frame not to include the bias stage. The data write frame also assumes the work of the reset stage and the data write stage, so if the retention frame can fully assume the work of the bias stage, it is not needed to configure the bias stage in the data write frame, thereby simplifying the timing of the data write frame.
In another embodiment, it is also feasible to configure that both the pre-stage of at least one retention frame and the pre-stage of at least one data write frame include the bias stage so that the work of the bias stage can be performed by both the retention frame and the data write frame, and thus the effect of the bias stage can be ensured. in an embodiment, the duration of one bias stage in the retention frame may be greater than the duration of any one of at least one bias stage in the data write frame; as described above, the pre-stage of the retention frame does not include the data write stage. In this case, the timing is relatively simple, and the time of the bias stage in the retention frame may be set longer, and the time of at least one bias stage in the data write frame may be set shorter, thereby preventing the pre-stage of the data write frame from being too long. Based on this, it is also feasible to set the sum of the durations of the bias stages in the retention frame greater than or equal to the sum of the durations of the bias stages in the data write frame. Further, in an embodiment, the duration of one bias stage in the retention frame is greater than the duration of any one of the bias stages in the data write frame, thereby sufficiently preventing the pre-stage of the data write frame from being too long.
Additionally, in such embodiments, as shown in
Additionally, in such embodiments, the display panel may further include an integrated chip for providing required drive signals such as the data signal Vdata, the reset signal Vref and the bias signal Vbias for the pixel circuit. Based on the same inventive concept, the integrated chip of this embodiment provides the reset signal Vref for the reset signal terminal during the reset stage of the pixel circuit and provides the bias signal Vbias for the reset signal terminal during the bias stage of the pixel circuit, thereby providing a guarantee for the operation of the pixel circuit of this embodiment. For information about the reset signal Vref and the bias signal Vbias, reference may be made to the description in the preceding embodiments.
Based on the above, for the pixel circuit shown in
The driving method of a display panel includes that in a reset stage, the reset module 16 and the compensation module 13 are on, the reset signal terminal provides the reset signal for the gate of the drive transistor T0, and the gate of the drive transistor T0 is reset; in a bias stage, the reset module 16 is on, the compensation module 13 is off, the reset signal terminal provides a bias signal Vbias to the drain of the drive transistor T0, and the bias state of the drive transistor T0 is adjusted.
In other embodiments, the driving method may include the driving method used during the operation of the pixel circuit of any one of the preceding implementations. The same content is not repeated in this embodiment. All these are within the scope of the driving method of this embodiment.
Embodiments of the present disclosure further provide a display device. The display device includes the preceding display panel. For the content of the display device, reference may be made to
In this embodiment, the reset module also serves as the bias module. On the one hand, the reset module can provide a reset signal for the gate of the drive transistor during the reset stage. On the other hand, the reset module can provide a bias signal for the drain of the drive transistor during the bias stage. The display panel includes the non-bias stage such as the light emission stage, so when the drive transistor is on, the gate potential of the drive transistor may be higher than the drain potential of the drive transistor. This may cause the Id-Vg curve of the drive transistor to drift and thereby cause the threshold voltage Vth of the drive transistor to drift. In order for this phenomenon to be ameliorated, the bias stage is configured so that the potential difference between the gate potential of the drive transistor and the source potential of the drive transistor is adjusted, the drift of the Id-Vg curve is reduced, and thereby the drift of the threshold voltage Vth of the drive transistor is reduced.
It is understood the preceding are only exemplary embodiments of the present disclosure and the technical principles used therein. It will be appreciated by those skilled in the art that the present disclosure is not limited to the embodiments described herein. For those skilled in the art, various apparent modifications, adaptations, combinations and substitutions can be made without departing from the scope of the present disclosure. Therefore, while the present disclosure has been described in detail via the preceding embodiments, the present disclosure is not limited to the preceding embodiments and may include equivalent embodiments without departing from the concept of the present disclosure. The scope of the present disclosure is determined by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202011104404.7 | Oct 2020 | CN | national |
This is a continuation of U.S. patent application Ser. No. 17/405,993, filed Aug. 18, 2021, which claims priority to Chinese Patent Application No. 202011104404.7 filed Oct. 15, 2020, the disclosures of which are incorporated herein by reference in their entireties.
| Number | Name | Date | Kind |
|---|---|---|---|
| 20200175913 | Kang | Jun 2020 | A1 |
| 20200226978 | Lin | Jul 2020 | A1 |
| 20210118368 | In | Apr 2021 | A1 |
| 20210134210 | In | May 2021 | A1 |
| 20220059030 | Sang | Feb 2022 | A1 |
| Number | Date | Country |
|---|---|---|
| 111435587 | Jul 2020 | CN |
| 111710299 | Sep 2020 | CN |
| Number | Date | Country | |
|---|---|---|---|
| 20230089631 A1 | Mar 2023 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17405993 | Aug 2021 | US |
| Child | 17994572 | US |
