Patent Application
20230146078
This application claims priority to Chinese Patent Application No. 202211153729.3 filed Sep. 21, 2022, the disclosure of which is incorporated herein by reference in its entirety.
Embodiments of the present disclosure relate to display technology and, in particular, to a display panel and a driving method thereof, an array substrate, a display panel, and a display device.
With the development of display technology, an organic light-emitting diode (OLED) display is increasingly widely used in the display field and gradually replaces a conventional liquid crystal display (LCD) due to its advantages such as self-light emitting, a wide viewing angle, high contrast, low power consumption, and a fast response speed.
To improve the display stability of an OLED, a pixel circuit that drives the OLED to emit light includes multiple transistors. Since a metal oxide (for example, indium gallium zinc oxide (IGZO)) transistor has the advantages of a high transmittance, low electron mobility, a great switch ratio, and low power consumption compared with a low-temperature polycrystalline silicon (LTPS) transistor. In the design of the existing pixel circuit, IGZO transistors are used to replace part of LTPS transistors to reduce the leakage current of the circuit. However, since there are two different types of transistors in the pixel circuit, LTPS p-type transistors and IGZO n-type transistors, three sets of different scanning circuits are required for driving in the pixel circuit, and a narrower bezel cannot be obtained.
Embodiments of the present disclosure provide a display panel and a driving method thereof, an array substrate, a display panel, and a display device. The pixel circuit needs only two sets of scanning circuits to implement driving. A perimeter driver circuit is simplified, and a narrower bezel of the display panel is implemented.
In a first aspect, an embodiment of the present disclosure provides a pixel circuit. The pixel circuit includes a drive circuit, a first initialization circuit, a data write circuit, and a threshold compensation circuit.
The control terminal of the drive circuit is electrically connected to a first node. A first terminal of the drive circuit is electrically connected to a second node, and a second terminal of the drive circuit is electrically connected to a third node.
A first terminal of the first initialization circuit is electrically connected to a first reference signal terminal, and a second terminal of the first initialization circuit is electrically connected to the third node.
The control terminal of the data write circuit is electrically connected to a scanning signal terminal. A first terminal of the data write circuit is electrically connected to a data signal terminal, and a second terminal of the data write circuit is electrically connected to the second node.
The control terminal of the threshold compensation circuit is electrically connected to an enable signal terminal. A first terminal of the threshold compensation circuit is electrically connected to the third node, and a second terminal of the threshold compensation circuit is electrically connected to the first node.
In a second aspect, an embodiment of the present disclosure provides a driving method of a pixel circuit. The method is used for driving the preceding pixel circuit and includes the steps below.
In an initialization stage, the first initialization circuit and the threshold compensation circuit are controlled to turn on. The data write circuit and the drive circuit are controlled to turn off. The first initialization circuit initializes the potential of the first node.
In a data write stage, the data write circuit, the drive circuit, and the threshold compensation circuit are controlled to turn on. The first initialization circuit is controlled to turn off. The data write circuit writes a data signal to the first node.
In a light emission stage, the drive circuit is controlled to turn on. The data write circuit, the first initialization circuit, and the threshold compensation circuit are controlled to turn off. The drive circuit provides a drive current to a light-emitting element. The light-emitting element emits light in response to the drive current.
In a third aspect, an embodiment of the present disclosure provides an array substrate. The array substrate includes a display region. The display region includes multiple pixel circuits arranged in an array.
In a fourth aspect, an embodiment of the present disclosure provides a display panel. The display panel includes the preceding array substrate.
In a fifth aspect, an embodiment of the present disclosure provides a display device. The display device includes the preceding display panel.
The pixel circuit provided by the embodiments of the present disclosure includes a drive circuit, a first initialization circuit, a data write circuit, and a threshold compensation circuit. The control terminal of the drive circuit is electrically connected to the first node. The first terminal of the drive circuit is electrically connected to the second node, and the second terminal of the drive circuit is electrically connected to the third node. The first terminal of the first initialization circuit is electrically connected to the first reference signal terminal, and the second terminal of the first initialization circuit is electrically connected to the third node. The control terminal of the data write circuit is electrically connected to the scanning signal terminal. The first terminal of the data write circuit is electrically connected to the data signal terminal, and the second terminal of the data write circuit is electrically connected to the second node. The control terminal of the threshold compensation circuit is electrically connected to the enable signal terminal. The first terminal of the threshold compensation circuit is electrically connected to the third node, and the second terminal of the threshold compensation circuit is electrically connected to the first node. Compared with the related art, the pixel circuit provided by the embodiments of the present disclosure needs to be provided with only one scanning signal terminal and one enable signal terminal and needs to be provided with only two sets of scanning circuits to implement driving. In this manner, the perimeter driver circuit is simplified, and the narrower bezel of the display panel is implemented.
Hereinafter the present disclosure is further described in detail in conjunction with the drawings and embodiments. It is to be understood that the specific embodiments set forth below are intended to illustrate and not to limit the present disclosure. Additionally, it is to be noted that, for ease of description, only part, not all, of structures related to the present disclosure are illustrated in the drawings.
Terms used in the embodiments of the present disclosure are merely used to describe the specific embodiments and not intended to limit the present disclosure. It is to be noted that nouns of locality, including “on”, “below”, “left” and “right”, used in the embodiments of the present disclosure, are described from the angles illustrated in the drawings and are not to be construed as a limitation to the embodiments of the present disclosure. Additionally, in the context, it is to be understood that when an element is formed “on” or “below” another element, the element may be directly formed “on” or “below” another element, or may be indirectly formed “on” or “below” another element via an intermediate element. The terms “first”, “second” and the like are merely used for description and used to distinguish between different components rather than indicate any order, quantity, or importance. For those of ordinary skill in the art, the preceding terms can be construed according to specific situations in the present disclosure.
To solve the preceding problems,
The drive circuit 10 is configured to drive the light-emitting element LED to emit light according to a data signal. The drive circuit 10 may include a drive transistor formed of an n-type transistor or a p-type transistor. During specific implementation, the electrical connection between the first terminal of the drive circuit 10 and the first power voltage terminal PVDD may be a direct electrical connection, or an indirect electrical connection through another component disposed in the middle, or a coupled connection. The data write circuit 30 is configured to write a data signal to the first node N1 under the control of the corresponding scanning signal terminal S. The data signal is used to control the magnitude of the drive current output by the drive circuit 10 to control the brightness of the light-emitting element. The data write circuit 30 may include a p-type transistor. The first initialization circuit 20 is configured to initialize the voltage of the first node N1. The control signal output by the scanning signal terminal S and the control signal output by the enable signal terminal Emit control the first n-type transistor 21 and the second n-type transistor 22 to turn on and off separately. The control terminal of the first n-type transistor 21 and the control terminal of the data write circuit 30 are connected to the same scanning signal terminal S. In this manner, compared with the related art, the effect of reducing a set of scanning circuits is implemented. The threshold compensation circuit 40 is configured to implement the threshold compensation of the gate of the drive transistor in the drive circuit 10. During specific implementation, when the data write circuit 30 writes the data signal to the first node N1, the third n-type transistor 41 is controlled to turn on through the control signal of the enable signal terminal Emit. The data voltage VData provided by the data signal terminal Data is written to the first node N1 through the drive circuit 10 and the third n-type transistor 41. The voltage of the second node N2 is VData. The voltage of the first node N1 is VData−Vth. Vth is the threshold voltage of the drive transistor in the drive circuit. A voltage related to Vth is pre-stored at the first node N1, and then the amount related to Vth in the current formula of the light-emitting element may be eliminated. Thus, the current flowing through the light-emitting element has nothing to do with Vth, and threshold compensation is implemented.
The pixel circuit provided by this embodiment of the present disclosure needs to be provided with only one scanning signal terminal and one enable signal terminal and needs to be provided with only two sets of scanning circuits to implement driving. In this manner, a perimeter driver circuit is simplified, and a narrower bezel of a display panel is implemented.
Optionally, in an embodiment, each of the first n-type transistor 21, the second n-type transistor 22, and the third n-type transistor 41 is a transistor including an oxide semiconductor, for example, an IGZO transistor. In other embodiments, the first n-type transistor 21, the second n-type transistor 22, and the third n-type transistor 41 may also be other types of oxide semiconductor transistors and may be selected according to actual situations during the specific implementation.
The storage circuit 50 is configured to maintain the potential of the first node N1 when the light-emitting element LED is in a light emission stage. The second initialization circuit 60 is configured to reset the first electrode (for example, the anode) of the light-emitting element LED before the light-emitting element LED emits light to prevent the brightness from being affected by the last light emission. The first light emission control circuit 70 and/or the second light emission control circuit 80 is configured to be on in the light emission stage, so that the light-emitting element LED emits light after the drive current flows through the light-emitting element LED. In an embodiment, the first electrode of the light-emitting element LED is an anode, and the second electrode of the light-emitting element LED is a cathode. The first power voltage terminal PVDD supplies an anode voltage, and the second power voltage terminal PVEE supplies a cathode voltage.
It is to be understood that since the first initialization circuit 20 and the second initialization circuit 60 may work in different time periods, two initialization signals may also be provided by the same signal line at different times. For example, in this embodiment, the first reference signal terminal Vref1 and the second reference signal terminal Vref2 are the same signal terminal. In this manner, the number of wires can be reduced, and the structure of the pixel circuit can be simplified.
Optionally, in an embodiment, the drive transistor M3, the fourth transistor M2, the fifth transistor M1, the sixth transistor M6, and the seventh transistor M7 are each a p-type transistor. Further, the p-type transistor is a transistor including a low-temperature polycrystalline silicon (LTPS) semiconductor. A transistor formed by an LTPS technique has the advantages of high mobility and fast charging.
In the preceding embodiment, the specific structure of the pixel circuit provided by this embodiment of the present disclosure is introduced. Since the pixel circuit provided by this embodiment of the present disclosure reduces the number of scanning circuits compared with the existing pixel circuit, and the driving method thereof is also different from the related art, the working principle of the pixel circuit is described below in combination with the driving method of the pixel circuit.
In step 110, in an initialization stage, the first initialization circuit and the threshold compensation circuit are controlled to turn on. The data write circuit and the drive circuit are controlled to turn off. The first initialization circuit initializes the potential of the first node.
The initialization stage is the first stage controlled by the pixel circuit and is used for initializing the potential of the first node. When the reference voltage provided from the first reference signal terminal is written to the first node through the first initialization circuit. For example, when the drive transistor in the drive circuit is a P-type transistor, the reference voltage is a logic low level signal. Specifically, the voltage of the logic low level signal may be selected according to actual situations.
In step 120, in a data write stage, the data write circuit, the drive circuit, and the threshold compensation circuit are controlled to turn on. The first initialization circuit is controlled to turn off. The data write circuit writes the data signal to the first node.
The data write stage is the second stage controlled by the pixel circuit and is used for writing the data signal to the first node. At the same time, the threshold compensation of the drive transistor in the drive circuit is implemented. The voltage value of the data signal is different, and the turn-on degree of the drive circuit in the drive circuit is different in the subsequent light emission stage. Thus, the magnitude of the drive current is controlled, thereby controlling the light-emitting element to implement display of different brightness.
In step 130, in the light emission stage, the drive circuit is controlled to turn on. The data write circuit, the first initialization circuit, and the threshold compensation circuit are controlled to turn off. The drive circuit provides the drive current to the light-emitting element. The light-emitting element emits light in response to the drive current.
The light emission stage is the third stage controlled by the pixel circuit. The display of different brightness of the light-emitting element may be implemented according to different data voltages input in the previous stage. For the entire display panel, all pixel circuits are scanned row by row to implement image display.
Optionally, the first initialization circuit includes a first n-type transistor and a second n-type transistor. The control terminal of the first n-type transistor is electrically connected to the scanning signal terminal S. The control terminal of the second n-type transistor is electrically connected to the enable signal terminal Emit. The pixel circuit also includes the threshold compensation circuit. The threshold compensation circuit includes a third n-type transistor. The drive circuit includes a drive transistor M3. The data write circuit includes a fourth transistor M2. The first light emission control circuit includes a fifth transistor M1. The second light emission control circuit includes a sixth transistor M6. The second initialization circuit includes a seventh transistor M7. The storage circuit includes a first capacitor Cst.
Referring to
It is to be understood that an n-type transistor is turned on when a gate voltage is at a logic high level, and a p-type transistor is turned on when a gate voltage is at a logic low level. In the initialization stage T1, the scanning signal terminal S outputs a logic high level, and the logic high level controls the first n-type transistor M5 to turn on. The enable signal terminal Emit outputs a logic high level, and the logic high level controls the second n-type transistor M8 and the third n-type transistor M4 to turn on. The reference voltage (a logic low level voltage) provided by the first reference signal terminal Vref1 is input to the first node N1 through the first n-type transistor M5, the second n-type transistor M8, and the third n-type transistor M4 to implement the initialization of the first node N1. In this stage, the fifth transistor M1 and the sixth transistor M6 are turned off under the control of the logic high level provided by the enable signal terminal Emit, and the fourth transistor M2 and the seventh transistor M7 are turned off under the control of the logic high level provided by the scanning signal terminal S.
Referring to
In the data write stage T2, the scanning signal terminal S outputs a logic low level, and the enable signal terminal Emit outputs a logic high level. The fourth transistor M2 is turned on under the control of the logic low level provided by the scanning signal terminal S. The third n-type transistor M4 is turned on under the control of the logic high level provided by the enable signal terminal Emit. Since a logic low level is written to the first node N1 in the initialization stage T1, at this time, the drive transistor M3 is also in an on state. The data voltage provided by the data signal terminal Data is written to the first node N1 after passing through the fourth transistor M2, the drive transistor M3, and the third n-type transistor M4. At the same time, the threshold compensation of the gate of the drive transistor M3 is implemented. In this stage, the fifth transistor M1 and the sixth transistor M6 are turned off under the control of the logic high level provided by the enable signal terminal Emit. Although the second n-type transistor M8 is in an on state, the first n-type transistor M5 is turned off under the control of the logic low level provided by the scanning signal terminal S. Thus, the first initialization circuit is in an off state. In the data write stage T2, the seventh transistor M7 is turned on under the control of the logic low level provided by the scanning signal terminal S. The reference voltage provided by the second reference signal terminal Vref2 resets the first electrode of the light-emitting element LED.
Referring to
In the light emission stage T3, the scanning signal terminal S outputs a logic high level, and the enable signal terminal Emit outputs a logic low level. The fifth transistor M1 and the sixth transistor M6 are turned on under the control of the logic low level provided by the enable signal terminal Emit. The third n-type transistor M4 is turned off under the control of the logic low level provided by the enable signal terminal Emit. The current provided by the first power voltage terminal PVDD flows into the light-emitting element LED after sequentially passing through the fifth transistor M1, the drive transistor M3, and the sixth transistor M6 to implement the display of the light-emitting element. In this stage, although the first n-type transistor M5 is turned on, the second n-type transistor M8 is turned off. Thus, the first initialization circuit is turned off. The seventh transistor M7 is turned off under the control of the logic high level provided by the scanning signal terminal S.
In conclusion, in the technical solutions provided by this embodiment of the present disclosure, only one scanning signal terminal and one enable signal terminal need to be configured to drive the corresponding pixel circuit. In this manner, the narrower bezel of the display panel is implemented.
An embodiment of the present disclosure provides an array substrate. The array substrate includes a display region. The display region includes multiple pixel circuits arranged in an array according to the preceding embodiments. Since the array substrate provided by this embodiment of the present disclosure includes any pixel circuit provided by the preceding embodiments, the array substrate has a technical effect of a narrow bezel.
Further referring to
The first scanning signal line S1 and the second scanning signal line S1′ may be connected to the same scanning signal terminal (not shown in
Further referring to
It is to be understood that the region where the scanning signal line or the enable signal line overlaps a corresponding semiconductor active layer forms the gate of a transistor, and that two sides of the gate are doped with other elements to form the source and drain of the transistor. For the connection between transistors formed by the same type of active layer, an active layer is heavily doped so that a conductive function is implemented. The connection between transistors formed by different types of active layers may be implemented by a cross-layer metal wire. A design may be performed according to an actual circuit structure layout during the specific implementation.
The first semiconductor active layer 100 includes a low-temperature polycrystalline silicon active layer. The second semiconductor active layer 200 includes an oxide semiconductor active layer, for example, an IGZO active layer.
Further referring to
A signal line and an active layer are located on different layers. A through hole may be formed at a corresponding position when a connection is required. For example, the circular (elliptical) region in
Optionally, the first semiconductor active layer is electrically connected to the second semiconductor active layer through a metal wire. The metal wire is on the same layer as the data signal line or the first power voltage signal line.
Since the material of the first semiconductor layer and the material of the second semiconductor layer are different, and the first semiconductor layer and the second semiconductor layer are generally disposed on different layers, the first semiconductor layer cannot be directly electrically connected to the second semiconductor layer. Thus, a connection wire needs to be disposed.
In this embodiment, the type of the first n-type transistor M5 and the type of the seventh transistor M7 are different. To avoid the direct connection between the active layers of the two, a first reference signal line ref1 and a second reference signal line ref2 are provided. The first reference signal line ref1 and the second reference signal line ref2 are connected to the first reference signal terminal Vref1 and the second reference signal terminal Vref2 (not shown in
The first pixel circuit A1 and the second pixel circuit A2 are configured to be symmetrically disposed about the power voltage signal line VDD, so that it is advantageous to reduce the number of power voltage signal lines VDD and simplify the circuit structure. Moreover, the width of the power voltage signal line VDD may be configured to be wider, so that a resistance is reduced, and a voltage drop is reduced.
Each of the first shift register 511 and the second shift register 512 is a shift register including multiple transistors and capacitors. The first shift register 511 and the second shift register 512 are configured to provide the control signal required by the gates of the transistors in the pixel circuit to control the corresponding transistors to turn on or off. The specific circuit structure may be selected according to actual situations. This is not limited in this embodiment of the present disclosure. It is merely schematic that the first shift register 511 is located on the side of the second shift register 512 adjacent to the display region 400. The order of the two is not limited in this embodiment of the present disclosure. In this embodiment, it is schematically shown that the shift register circuit 510 is located at the left and right bezels of the array substrate. In other embodiments, the shift register circuit 510 may also be disposed in only one bezel, or the first shift register 511 and the second shift register 512 may be located in different bezels respectively.
In this embodiment of the present disclosure, the provided pixel circuit includes two scanning signal lines (such as the first scanning signal line S1 and the second scanning signal line S1′ in
Optionally, the array substrate includes n rows of pixel circuits. Pixel circuits in each row are connected through a first scanning signal line and a second scanning signal line. The output terminal of the first shift register at the i-th stage is connected to each of the first scanning signal line and the second scanning signal line in the pixel circuits in the i-th row. 0<i≤n, n≥2, and i and n are the integers.
Optionally, the array substrate includes n rows of pixel circuits. Pixel circuits in each row are connected through a first scanning signal line and a second scanning signal line. The output terminal of the first shift register at the i-th stage is connected to each of the second scanning signal line in the pixel circuits in the i-th row and the first scanning signal line in the pixel circuits in the (i+j)-th row. 0<i≤n, 0<j≤n−i, n≥3, and i, j, and n are integers.
Optionally, pixel circuits in each row are connected through a first enable signal line and a second enable signal line. The output terminal of the second shift register at the i-th stage is connected to each of the first enable signal line and the second enable signal line in the pixel circuits in the i-th row. 0<i≤n, n≥2, and i and n are integers.
Optionally, pixel circuits in each row are connected through a first enable signal line and a second enable signal line. The output terminal of the second shift register at the i-th stage is connected to each of the first enable signal line in the pixel circuits in the i-th row and the second enable signal line in the pixel circuits in the (i+j)-th row. 0<i≤n, 0<j≤n−i, n≥3, and i, j, and n are integers.
For example,
Referring to
Referring to
Referring to
It is to be noted that the array substrate provided by this embodiment of the present disclosure may adopt a single-sided driving method or a double-sided driving method when driving the pixel circuit. For example, when scanning signal lines are driven, a first sub-shift register and a second sub-shift register provide signals to the corresponding scanning signal lines from two sides at the same time, which is the double-sided drive. The first sub-shift register provides a signal to one of the scanning signal lines from the left side while the second sub-shift register provides a signal to the other scanning signal line from the right side, which is the single-sided drive. The method for driving a signal is not limited in this embodiment of the present disclosure.
An embodiment of the present disclosure provides a display panel. The display panel includes any array substrate provided by the preceding embodiments. The display panel has the technical effect of a narrow bezel.
It is to be noted that the preceding are only preferred embodiments of the present disclosure and the technical principles used therein. It is to be understood by those skilled in the art that the present disclosure is not limited to the embodiments described herein. For those skilled in the art, various apparent modifications, adaptations, combinations, and substitutions can be made without departing from the scope of the present disclosure. Therefore, while the present disclosure is described in detail in connection with the preceding embodiments, the present disclosure is not limited to the preceding embodiments and may include equivalent embodiments without departing from the concept of the present disclosure. The scope of the present disclosure is determined by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211153729.3 | Sep 2022 | CN | national |
