Patent Grant
10665176
This application claims the benefit of Korean Patent Application No. 10-2017-0083271 filed on Jun. 30, 2017, the entire contents of which is incorporated herein by reference for all purposes as if fully set forth herein.
The present disclosure relates to a display panel, in which a demultiplexer is disposed between a data driving circuit and data lines, and an electroluminescent display using the same.
Examples of flat panel displays include a liquid crystal display (LCD), an electroluminescent display, a field emission display (FED), and a plasma display panel (PDP).
An electroluminescent display can be classified into an inorganic electroluminescent display and an organic electroluminescent display depending on the material of an emission layer. An active matrix organic light emitting diode (OLED) display includes a plurality of OLEDs capable of emitting light by themselves and has many advantages of fast response time, high emission efficiency, high luminance, wide viewing angle, and the like.
A driving circuit of a flat panel display includes a data driving circuit for supplying data signals to data lines, a gate driving circuit for supplying gate signals (or referred to as “scan signals”) to gate lines (or referred to as “scan lines”), and the like. The gate driving circuit may be directly formed on the same substrate together with a thin film transistor (TFT) array of an active area constituting the screen.
Each pixel of an OLED display includes a driving element for controlling a current flowing in a light emitting element (i.e., an OLED). The driving element may be implemented as a transistor. The driving elements of all the pixels have to have the same electrical characteristics including a threshold voltage, mobility, etc. However, there is a variation in electrical characteristics between the driving elements due to process conditions, a driving environment, and the like. As a driving time of the driving element increases, a stress applied to the driving element increases. Further, the stress of the driving element varies depending on data of an input image. The electrical characteristics of the driving element can be influenced by such stress. Thus, as driving time passes, electrical characteristics of the driving elements inevitably vary.
To improve image quality and lifespan of OLED displays, a compensation circuit for compensating for driving characteristics of pixels in real time has been applied to a pixel circuit. Further, a method for distributing an output of a data driving circuit to data lines using a demultiplexer and reducing the number of output terminals of the data driving circuit has been attempted in the OLED displays. However, the method has not been adopted on the present products because a threshold voltage of driving elements of some pixels is not sensed and there is a luminance difference among the pixels.
Accordingly, the present disclosure is directed to a display panel and an electroluminescent display using the same that substantially obviate one or more of problems due to limitations and disadvantages of the prior art.
More specifically, the present disclosure provides a display panel and an electroluminescent display using the same capable of compensating for a threshold voltage of a driving element in all of pixels and achieving a uniform luminance of the pixels in the electroluminescent display connecting output terminals of a data driving circuit to data lines through a demultiplexer.
Additional features and advantages of the disclosure will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. Other advantages of the present disclosure will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In one aspect, there is provided a display panel connected to a data driver sequentially outputting a first data signal and a second data signal through an output terminal, the display panel comprising a first data line charged with the first data signal, a second data line charged with the second data signal, a first subpixel connected to the first data line, a second subpixel connected to the second data line, a gate line commonly connected to the first and second subpixels and configured to simultaneously supply a gate signal to the first and second subpixels, a demultiplexer configured to connect the output terminal of the data driver to the first data line using a plurality of MUX switch elements and then connect the output terminal to the second data line using the plurality of MUX switch elements, and a switch array configured to supply a predetermined reference voltage to the second data line when the output terminal of the data driver is connected to the first data line by the demultiplexer using a plurality of REF switch elements.
In another one aspect, there is provided an electroluminescent display comprising a data driver configured to sequentially output a first data signal and a second data signal through an output terminal, a first data line charged with the first data signal, a second data line charged with the second data signal, a first subpixel connected to the first data line, a second subpixel connected to the second data line, a gate line commonly connected to the first and second subpixels and configured to simultaneously supply a gate signal to the first and second subpixels, a demultiplexer configured to connect the output terminal of the data driver to the first data line using a plurality of MUX switch elements and then connect the output terminal to the second data line using the plurality of MUX switch elements, and a switch array configured to supply a predetermined reference voltage to the second data line when the output terminal of the data driver is connected to the first data line by the demultiplexer using a plurality of REF switch elements, wherein each of the first and second subpixels includes a pixel circuit, wherein the pixel circuit includes a driving element for driving a light emitting element and a plurality of switch elements, wherein the pixel circuit is initialized in an initialization operation, senses a threshold voltage of the driving element in a sensing operation, and emits light in an emission operation.
The accompanying drawings, that may be included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate aspects of the disclosure and together with the description serve to explain various principles of the disclosure.
In the drawings:
Reference will now be made in detail to aspects of the disclosure, examples of which are illustrated in the accompanying drawings. However, the present disclosure is not limited to aspects disclosed below, and may be implemented in various forms. These aspects are provided so that the present disclosure will be described more completely, and will fully convey the scope of the present disclosure to those skilled in the art to which the present disclosure pertains. Particular features of the present disclosure can be defined by the scope of the claims.
Shapes, sizes, ratios, angles, number, and the like illustrated in the drawings for describing aspects of the disclosure are merely exemplary, and the present disclosure is not limited thereto unless specified as such. Like reference numerals designate like elements throughout. In the following description, when a detailed description of certain functions or configurations related to this document that may unnecessarily cloud the gist of the disclosure have been omitted.
In the present disclosure, when the terms “include”, “have”, “comprised of”, etc. are used, other components may be added unless “˜only” is used. A singular expression can include a plural expression as long as it does not have an apparently different meaning in context.
In the explanation of components, even if there is no separate description, it is interpreted as including margins of error or an error range.
In the description of positional relationships, when a structure is described as being positioned “on or above”, “under or below”, “next to” another structure, this description should be construed as including a case in which the structures directly contact each other as well as a case in which a third structure is disposed therebetween.
The terms “first”, “second”, etc. may be used to distinguish various components. However, functions or structures of the components are not limited by names of the components and ordinal numbers prefixed to the component names.
The features of aspects of the disclosure can be partially combined or entirely combined with each other, and can be technically interlocking-driven in various ways. The aspects can be independently implemented, or can be implemented in conjunction with each other.
A pixel circuit included in an electroluminescent display according to aspects of the disclosure may include at least one of an n-type thin film transistor (TFT) (or n-type metal oxide semiconductor field effect transistor (MOSFET) (NMOS)) and a p-type TFT (or p-type MOSFET (PMOS)). The TFT is a three-electrode element including a gate, a source, and a drain. The source is an electrode for supplying carriers to the TFT. The carriers inside the TFT begin to flow from the source. The drain is an electrode from which carriers exit the TFT. Namely, carriers in the TFT flow from the source to the drain. In case of the n-type TFT, because carriers are electrons, a source voltage is less than a drain voltage so that electrons can flow from a source to a drain. In the n-type TFT, because electrons flow from the source to the drain, a current flows from the drain to the source. In case of the p-type TFT, because carriers are holes, a source voltage is greater than a drain voltage so that holes can flow from a source to a drain. In the p-type TFT, because holes flow from the source to the drain, a current flows from the source to the drain. In aspects disclosed herein, the source and the drain of the TFT are not fixed. For example, the source and the drain of the TFT may be changed depending on an applied voltage. Thus, the present disclosure is limited by the source and the drain of the TFT. In the following description, the source and the drain of the TFT are referred to as a first electrode and a second electrode, respectively.
A gate signal applied to the pixel circuit swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage greater than a threshold voltage of the TFT, and the gate-off voltage is set to a voltage less than the threshold voltage of the TFT. The TFT is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage. In case of an n-type TFT, the gate-on voltage may be a gate high voltage VGH, and the gate-off voltage may be a gate low voltage VGL. In case of a p-type TFT, the gate-on voltage may be the gate low voltage VGL, and the gate-off voltage may be the gate high voltage VGH.
In the following aspects, an electroluminescent display will be described focusing on an organic light emitting diode (OLED) display including an organic light emitting material. However, the technical idea of the present disclosure is not limited to the OLED display. For example, the present disclosure may be applied to an inorganic electroluminescent display including an inorganic electroluminescent material.
Aspects of the disclosure supply a data voltage output from a data driver through one channel to N data lines using a demultiplexer (or referred to as “DEMUX”) in a time division manner, where N is an even number equal to or greater than 2. In the following description, a demultiplexer having a 1:2 MUX structure, in which one output terminal of a data driver is connected to two data lines, is described as an example. However, aspects are not limited thereto.
Referring to
The display panel 100 includes an active area AA where an input image is displayed on a screen. A pixel array is disposed in the active area AA. The pixel array includes signal lines and pixels arranged in a matrix form. The signal lines include data lines 102 and gate lines 103 intersecting the data lines 102. Power lines may be disposed on the pixel array. In
Each pixel may include a red subpixel, a green subpixel, and a blue subpixel for color representation. Each pixel may further include a white subpixel. Each subpixel 101 includes a pixel circuit. The pixel circuit includes a light emitting element, a driving element, one or more switch elements, a capacitor, and the like. The driving element and the switch elements may be implemented as TFTs.
The display panel 100 may further include VDD lines for supplying a pixel driving voltage VDD to the subpixels 101, Vini lines for supplying an initialization voltage Vini for initializing the pixel circuit to the subpixels 101, VSS electrodes for supplying a low potential power voltage VSS to the subpixels 101, VGH lines supplied with a gate high voltage VGH, VGL lines supplied with a gate low voltage VGL, and the like. Power voltages including the VDD, the Vini, the VSS, etc. are generated from a power circuit (not shown). For example, the power voltages may be set as follows: VDD=4.5V, VSS=−2.5V, Vini=−3.5V, VGH=7.0V, VGL=−5.5V. However, aspects are not limited thereto. The power voltages may vary depending on driving characteristics or models of the display panel 100.
Touch sensors may be disposed on the display panel 100. A touch input may be sensed using separate touch sensors or sensed through the pixels. The touch sensors may be implemented as on-cell touch sensors or add-on touch sensors and disposed on the screen of the display panel 100. Alternatively, the touch sensors may be implemented as in-cell touch sensors that are embedded in the pixel array.
The display panel driving circuit includes a data driver 110 and a gate driver 120. The display panel driving circuit further includes a demultiplexer 112 between the data driver 110 and the data lines 102 and a switch array 114 for supplying the initialization voltage Vini to at least some of the data lines 102.
The display panel driving circuit writes data of an input image to the pixels of the display panel 100 under the control of a timing controller 130. The display panel driving circuit may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is omitted in
The display panel driving circuit may operate in a low refresh driving mode. The low refresh driving mode is set to reduce power consumption of a display device when there is no change in an input image for a predetermined time as a result of the analysis of the input image. In other words, the low refresh driving mode can increase a data writing cycle of pixels by reducing a refresh rate (or referred to as “frame rate”) of the pixels when a still image is input for a predetermined time or more, thereby reducing the power consumption of the display device. The low refresh driving mode is not limited to when the still image is input. For example, the display panel driving circuit can operate in the low refresh driving mode when the display device operates in a standby mode or when a user command or an input image is not input to the display panel driving circuit for a predetermined time or more.
The data driver 110 converts digital data of an input image received from the timing controller 130 into a gamma compensation voltage and generates a data signal in each frame period. The data driver 110 outputs a voltage (hereinafter referred to as “data voltage”) of the data signal in each output terminal through an output buffer AMP.
The demultiplexer 112 is disposed between the data driver 110 and the data lines 102. The demultiplexer 112 distributes the data voltage output from the data driver 110 to the data lines 102 using a plurality of switch elements M1 and M2. As shown in
The switch array 114 includes a plurality of switch elements S1 and S2 for supplying the initialization voltage Vini to the subpixels 101 before the data voltage is applied. More specifically, the switch array 114 includes a plurality of first switch elements S1 connecting the first data line group including the data lines D1 and D3 to initialization voltage lines and a plurality of second switch elements S2 connecting the second data line group including the data lines D2 and D4 to initialization voltage lines. The demultiplexer 112, the switch array 114, and the gate driver 120 may be disposed on the display panel 100 together with the pixel array.
As shown in
The pixel circuits of the subpixels 101, the demultiplexer 112, the switch array 114, and the gate driver 120 may be formed directly on a substrate of the display panel 100 in the same manufacturing process. Transistors of the pixel circuits, the demultiplexer 112, the switch array 114, and the gate driver 120 may be implemented as NMOS or PMOS transistors and may be implemented as transistors of the same type.
The gate driver 120 outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 shifts the gate signals using a shift register and can sequentially supply the gate signals to the gate lines 103. The gate signals include scan signals SCAN0 to SCANn for selecting pixels of a pixel line on which data is to be written, and emission switching signals (hereinafter referred to as “EM signals”) EM1 to EMn defining an emission time of pixels charged with the data voltage.
The timing controller 130 receives digital video data DATA of an input image and timing signals synchronized with the digital video data DATA from a host system (not shown). The timing signals include a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE, a clock signal DCLK, and the like. The host system may be one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and other systems that include or operate in conjunction with a display device.
The timing controller 130 multiplies an input frame frequency by “i” and can control operation timing of the display panel driving circuits (110, 112, 114, and 120) at a frame frequency of (i.e., input frame frequency×i) Hz, where “i” is a positive integer greater than zero. The input frame frequency is 50 Hz in a phase alternate line (PAL) scheme and is 60 Hz in the national television standards committee (NTSC) scheme. In the low refresh driving mode, the timing controller 130 may reduce the frame frequency to 1 Hz to 30 Hz in order to reduce a refresh rate of the pixels.
The timing controller 130 generates a data timing control signal for controlling operation timing of the data driver 110, switch control signals MUXA, MUXB, IEN1 and IEN2 for controlling operation timings of the demultiplexer 112 and the switch array 114, and a gate timing control signal for controlling operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, DE, and DCLK received from the host system. Voltage levels of the gate timing control signal and the switch control signals MUXA, MUXB, IEN1 and IEN2 output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and may be supplied to the gate driver 120. The level shifter converts a low level voltage of the gate timing control signal into the gate low voltage VGL and converts a high level voltage of the gate timing control signal into the gate high voltage VGH.
Referring to
The data driver 110 time-divides the data signal into a first data signal DATA1 and a second data signal DATA2 and sequentially outputs the first data signal DATA1 and the second data signal DATA2 through the first output terminal CH1 for one horizontal period 1H. One horizontal period 1H is time required to apply the data signal to pixels disposed on one pixel line.
The first switch element M1 is disposed between the first output terminal CH1 and a first data line D1. The first switch element M1 is turned on in response to the first switch control signal MUXA and supplies the first data signal DATA1 applied through the first output terminal CH1 to the first data line D1. A first subpixel 101A connected to the first data line D1 is supplied with the first data signal DATA1 through the first switch element M1. The second switch element M2 is disposed between the first output terminal CH1 and a second data line D2. The second switch element M2 is turned on in response to the second switch control signal MUXB and supplies the second data signal DATA2 applied through the first output terminal CH1 to the second data line D2. A second subpixel 101B connected to the second data line D2 is supplied with the second data signal DATA2 through the second switch element M2. The first and second subpixels 101A and 101B share a gate line with each other and are supplied with scan signals SCAN synchronized with the first and second data signals DATA1 and DATA2 through the shared gate line. After the first subpixel 101A is supplied with the first data signal DATA1 during an A period, the second subpixel 101B is supplied with the second data signal DATA2 during a B period. Each of the A period and the B period is about ½ horizontal period ½ H.
Each of the scan signals SCAN(N−1) and SCAN(N) may be generated as a pulse of one horizontal period 1H. The (N−1)th scan signal SCAN(N−1) is supplied to pixels of an (N−1)th pixel line and pixels of an Nth pixel line, where N is a positive integer greater than zero. During one horizontal period 1H in which a pulse of the (N−1)th scan signal SCAN(N−1) is generated, the pixels of the (N−1)th pixel line perform a process (hereinafter referred to as “Twr operation”) for sensing a threshold voltage and writing data in the driving element, and at the same time the pixels of the Nth pixel line perform an initialization process (hereinafter referred to as “Tini operation”). The Nth scan signal SCAN(N) is supplied to the pixels of the Nth pixel line and pixels of an (N+1)th pixel line. During one horizontal period 1H in which a pulse of the Nth scan signal SCAN(N) is generated, the pixels of the Nth pixel line perform the Twr operation, and at the same time the pixels of the (N+1)th pixel line perform the Tini operation.
The Twr operation is divided into the A period and the B period. The A period is time required to charge subpixels belonging to a first pixel group with the data voltage and to charge subpixels belonging to a second pixel group with the initialization voltage Vini. The B period is time required to charge or float the subpixels belonging to the first pixel group with the initialization voltage Vini and to charge the subpixels belonging to the second pixel group with the data voltage. In aspects disclosed herein, the first pixel group includes subpixels operating in the same way as the first subpixel 101A, and the second pixel group includes subpixels operating in the same way as the second subpixel 101B. Positions of the first pixel group and the second pixel group may be reversed every a predetermined time, for example, every N frame period, where N is a positive integer greater than zero.
The EM signal EM(N) defines a light emission operation Tem (hereinafter referred to as “EM period”) of the light emitting element of the pixel circuit. The EM signal EM(N) is generated as a pulse of the gate-off voltage for time in which the EM signal EM(N) overlaps the (N−1)th scan signal SCAN(N−1) and the Nth scan signal SCAN(N). The EM signal EM(N) is held at the gate-on voltage in most of a remaining time excluding a width of the pulse of the gate-off voltage from one frame period. During the EM period Tem, third and fourth switching TFT elements T3 and T4 are turned on due to an ON-time period of the EM signal EM(N) as shown in
The driving element of the pixel circuit is driven in accordance with a gate-to-source voltage Vgs for time, in which the EM signal EM(N) is generated at the gate-on voltage, and supplies a current to the light-emitting element. Thus, the light emitting element of the pixel circuit can emit light during the EM period Tem.
Each of the first and second switch control signals MUXA and MUXB may be generated as a pulse of a ½ horizontal period. The first and second switch control signals MUXA and MUXB do not overlap each other so that the first and second switch elements M1 and M2 are not simultaneously turned on. For example, after the first switch element M1 is turned on, the second switch element M2 may be turned on. On the contrary, after the second switch element M2 is turned on, the first switch element M1 may be turned on.
The data driver 110 may include switch elements M12 and M22 that are synchronized with the demultiplexer 112. The third switch element M12 is disposed between a first output buffer AMP1 and the first output terminal CH1. The third switch element M12 is turned on in response to the first switch control signal MUXA at the same time as the first switch element M1 and outputs the first data signal DATA1 through the first output terminal CH1. The fourth switch element M22 is disposed between a second output buffer AMP2 and the first output terminal CH1. The fourth switch element M22 is turned on in response to the second switch control signal MUXB at the same time as the second switch element M2 and outputs the second data signal DATA2 through the first output terminal CH1.
The first data line D1 is charged with the first data signal DATA1 supplied through the switch element M1 during the A period and then is floated or charged with the initialization voltage Vini during the B period. The fact that the first data line D1 is floated means that the switch elements M1 and S1 connected to the first data line D1 are turned off and thus no signal or voltage is applied to the first data line D1. The switch element S1 of the switch array 114 may be turned on in response to the first switch control signal IEN1 during the B period and may supply the initialization voltage Vini to the first data line D1. Alternatively, the switch element S1 of the switch array 114 may maintain an off-state during the B period so that the first data line D1 is floated.
The second data line D2 is charged with the initialization voltage Vini during the A period and then is charged with the second data signal DATA2 during the B period. The switch element S2 of the switch array 114 is turned on in response to the second switch control signal IEN2 during the A period and supplies the initialization voltage Vini to the second data line D2, so that malfunction of the second subpixel 101A is prevented.
Each data line 102 of the display panel 100 includes a parasitic capacitance Cp. If the switch array 114 is not provided, the subpixels of the second pixel group may malfunction in the A period due to the parasitic capacitance Cp. The switch array 114 applies the initialization voltage Vini to the data lines connected to the second subpixel 101B during the A period to thereby prevent the malfunction of the second pixel group.
Referring to
The TFTs T1 to T6 and DT may be implemented as p-type TFTs or PMOS transistors. However, aspects are not limited thereto.
The switching TFTs T1 to T6 are turned on or off in response to the gate signal from the gate line and thus initialize the pixel circuit in a Tini operation. Subsequently, in a Twr operation, the switching TFTs T1 to T6 sense a threshold voltage Vth of the driving element DT and supply a gate of the driving element DT with a data voltage that is compensated as much as the threshold voltage Vth. In an EM period Tem, the switching TFTs T1 to T6 form a current path between the VDD and the light emitting element EL and cause the light emitting element EL to emit light.
The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL. However, aspects are not limited thereto. When a power voltage is applied to the anode and the cathode, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emission layer EML and combine, thereby forming excitons. As a result, the emission layer EML generates visible light by the excitons. The OLED emits light with an amount of current that is controlled by the driving element DT. The anode of the OLED is connected to the fourth and sixth switching TFTs T4 and T6 through a sixth node n6. The cathode of the OLED is connected to the VSS electrode supplied with the low potential power voltage VSS. A current path of the OLED is switched by the fourth switching TFT T4.
A first electrode of the storage capacitor Cst is connected to the VDD line and a first electrode of the third switching TFT T3 through a second node n2. A second electrode of the storage capacitor Cst is connected to the gate of the driving TFT DT, a first electrode of the second switching TFT T2, and a first electrode of the fifth switching TFT T5 through a third node n3.
The first switching TFT T1 is a switch element for supplying data lines D1 and D2 to a first node n1 in response to the Nth scan signal SCAN(N). The first switching TFT T1 includes a gate connected to a first gate line G1, a first electrode connected to the data lines D1 and D2, and a second electrode connected to the first node n1. The Nth scan signal SCAN(N) is applied to the pixel circuit through the first gate line G1.
The second switching TFT T2 connects the third node n3 to a fourth node n4 in response to the Nth scan signal SCAN(N). The gate and a drain of the driving TFT DT are connected by the second switching TFT T2, and thus the driving TFT DT can operate as a diode. The second switching TFT T2 includes a gate connected to the first gate line G1, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.
The third switching TFT T3 connects the VDD line to the first node n1 in response to the EM signal EM(N). The third switching TFT T3 includes a gate connected to a second gate line G2 supplied with the EM signal EM(N), a first electrode connected to the VDD line through the second node n2, and a second electrode connected to the first node n1.
The fourth switching TFT T4 switches a current path of the light emitting element EL in response to the EM signal EM(N). A gate of the fourth switching TFT T4 is connected to the second gate line G2. A first electrode of the fourth switching TFT T4 is connected to a second electrode of the driving TFT DT and the second electrode of the second switching TFT T2 through the fourth node n4. A second electrode of the fourth switching TFT T4 is connected to a second electrode of the sixth switching TFT T6 and the anode of the light emitting element EL through the sixth node n6.
The fifth switching TFT T5 connects the third node n3 to a fifth node n5 in response to the (N−1)th scan signal SCAN(N−1). The fifth switching TFT T5 includes a gate connected to a third gate line G3 supplied with the (N−1)th scan signal SCAN(N−1), a first electrode connected to the second electrode of the storage capacitor Cst through the third node n3, and a second electrode connected to the Vini line and a first electrode of the sixth switching TFT T6 through the fifth node n5.
The sixth switching TFT T6 connects the fifth node n5 to the sixth node n6 in response to the (N−1)th scan signal SCAN(N−1). The sixth switching TFT T6 includes a gate connected to the third gate line G3, the first electrode connected to the second electrode of the fifth switching TFT T5 and the Vini line through the fifth node n5, and the second electrode connected to the second electrode of the fourth switching TFT T4 and the anode of the light emitting device EL through the sixth node n6.
The driving TFT DT controls a current flowing in the light emitting element EL depending on the gate-to-source voltage Vgs. The driving TFT DT includes the gate connected to the third node n3, a first electrode connected to the first node n1, and the second electrode connected to the fourth node n4.
In the Tini operation of the first and second subpixels 101A and 101B disposed on the Nth pixel line, the (N−1)th scan signal SCAN(N−1) is generated as a pulse of the gate-on voltage, and the Nth scan signal SCAN(N) and the EM signal EM(N) are held at the gate-off voltage. Thus, in the Tini operation, the fifth and sixth switching TFTs T5 and T6 are turned on, and the remaining switching TFTs T1 to T4 maintain an off-state. In the Tini operation, the second node n2 is initialized to the VDD, and the third, fifth, and sixth nodes n3, n5 and n6 are initialized to the Vini.
Referring to
Referring to
During the B period Twr-B, when the initialization voltage Vini is applied to the first data line D1, a source voltage of the driving TFT DT, i.e., a voltage of the first node n1 is reduced to a value equal to or less than the gate voltage of the driving TFT DT. Therefore, the driving TFT DT is turned off, and the gate voltage of the driving TFT DT is held at “Nth Line DATA+Vth”.
Referring to
Referring to
During the EM period Tem, the light emitting element EL emits light by the driving TFT DT driven depending on the gate-to-source voltage Vgs. The gate voltage of the driving TFT DT is held at the data voltage “Nth Line DATA+Vth” that is compensated as much as the threshold voltage Vth of the driving TFT DT due to the storage capacitor Cst.
Each data line 102 of the display panel 100 includes a parasitic capacitance Cp. If the switch array 114 is not provided, the second subpixel 101B may malfunction due to the parasitic capacitance Cp as shown in
When the switch array 114 is not provided, the first data line D1 is charged with the first data signal DATA1 during the A period and then is floated during the B period. On the other hand, the second data line D2 is floated during the A period and then is charged with the second data signal DATA2 during the B period.
Referring to
Referring to
During the B period Twr-B, the gate voltage of the driving TFT DT is “(N−1)th Line DATA+Vth” different from the initialization voltage Vini. When “(N−1)th Line DATA+Vth” is greater than “Nth Line DATA”, the driving TFT DT is turned off. Therefore, the gate voltage of the driving TFT DT cannot increase to “Nth Line DATA+Vth”. Thus, in the second subpixel 101B, when the initialization voltage Vini is not applied to the second data line D2 during the A period, the threshold voltage Vth of the driving TFT DT cannot be sensed in the Twr operation.
Aspects of the disclosure set the second data line D2 connected to the second subpixel 101B to the initialization voltage Vini during the A period Twr-A of the second subpixel 101B as shown in
Referring to
The switch array 114 supplies the initialization voltage Vini to the data lines D2 and D4 connected to the second pixel group in response to the first switch control signal IEN1 during the A period. The switch array 114 supplies the initialization voltage Vini to the data lines D1 and D3 connected to the first pixel group in response to the second switch control signal IEN2 during the B period.
The subpixels 101A of the first pixel group may be connected to the odd-numbered data lines D1 and D3, and the subpixels 101B of the second pixel group may be connected to the odd-numbered data lines D2 and D4. However, aspects are not limited thereto.
The first switch control signal MUXA of the demultiplexer 112 and the first switch control signal IEN1 of the switch array 114 are generated in antiphase. Further, the second switch control signal MUXB of the demultiplexer 112 and the second switch control signal IEN2 of the switch array 114 are generated in antiphase. Thus, as shown in
As described above with reference to
Referring to
A switch control signal IEN for controlling the switch array 114 and the first switch control signal MUXA of the demultiplexer 112 may be generated in phase. The switch array 114 includes switch elements S3 that supplies the initialization voltage Vini to the data lines D2 and D4 connected to the second pixel group in response to the switch control signal IEN during the A period. In the second aspect of the disclosure, the switch elements S3 of the switch array 114 do not need to be connected to the data lines D1 and D3 connected to the first pixel group. As described above with reference to
The first switch control signal MUXA of the demultiplexer 112 and the first switch control signal IEN1 of the switch array 114 are generated in antiphase. Thus, as shown in
Referring to
Referring to
When the switch control signals MUXA and MUXB are inverted every a predetermined time, for example, every horizontal period, the subpixels 101A of the first pixel group and the subpixels 101B of the second pixel group are alternately arranged in one frame period at intervals of one subpixel. When the arrangement of the first and second pixel groups is the same in every frame period as described above, a luminance difference may occur based on one subpixel.
When the switch control signals MUXA and MUXB are inverted every horizontal period and are also inverted every frame period, the subpixels 101A of the first pixel group and the subpixels 101B of the second pixel group are positioned adjacent to each other in up, down, left and right directions in one frame period as shown in
A method for reducing power consumption by reducing the number of switching operations of the demultiplexer is disclosed in U.S. Patent Publication No. 2016-0078826A1 (17 Mar. 2016) corresponding to the present applicant, and which are hereby incorporated by reference in their entirety. The method, as shown in
A threshold voltage sensing time of the pixels is determined by ON-time of the demultiplexer 112 and ON-time of the scan signal synchronized with the data signal. Aspects of the disclosure can uniformly control spatially and in time a luminance of the pixels by properly changing an ON-time period of switch control signals MUX1 and MUX2 and an ON-time period of the scan signal in each frame period as shown in
As shown in
Referring again to
The switch control signals MUXA and MUXB shown in
Referring to
The ON-time period of the switch control signal MUX is divided into a first portion FH corresponding to a first half of the pulse and a second portion SH corresponding to a second half of the pulse. In the same manner as the switch control signal MUX, the ON-time period of the scan signal SCAN(N) is divided into a first portion FH corresponding to a first half of the pulse and a second portion SH corresponding to a second half of the pulse. In the following description, a first scan signal SCAN1 and the switch control signals MUX1 and MUX2 are abbreviated as reference marks.
The SCAN1 generated in the first frame period FR1 is synchronized with data signals R and G applied to the subpixels of the first pixel line LINE1. The data signal R is supplied to the first data line D1 through the first switch element M1, which is turned on in response to the MUX2, and is supplied to the R subpixel in the first portion FH of the SCAN1. The data signal G is supplied to the second data line D2 through the second switch element M2, which is turned on in response to the MUX1, and is supplied to the G subpixel in the second portion SH of the SCAN1. The R subpixel operates in the same manner as the first subpixel 101A in the first frame period FR1. Because the R subpixel starts to be charged with the voltage of the data signal from an overlap period of the second portion SH of the MUX2 and the first portion FH of the SCAN1 in the first frame period FR1, the R subpixel senses the threshold voltage of the driving TFT during about one horizontal period 1H and compensates for the data voltage as much as the sensed threshold voltage. On the other hand, the G subpixel operates in the same manner as the second subpixel 101B in the first frame period FR1. Because the G subpixel starts to be charged with the voltage of the data signal from an overlap period of the first portion FH of the MUX1 and the second portion SH of the SCAN1 in the first frame period FR1, the G subpixel senses the threshold voltage of the driving TFT during about ½ horizontal period (½)H and compensates for the data voltage as much as the sensed threshold voltage.
The SCAN1 generated in the second frame period FR2 is synchronized with data signals R and G applied to the subpixels of the first pixel line LINE1. The data signal R is supplied to the first data line D1 through the first switch element M1, which is turned on in response to the MUX1, and is supplied to the R subpixel in the second portion SH of the SCAN1. The data signal G is supplied to the second data line D2 through the second switch element M2, which is turned on in response to the MUX2, and is supplied to the G subpixel in the first portion FH of the SCAN1. The R subpixel operates in the same manner as the second subpixel 101B in the second frame period FR2. Because the R subpixel starts to be charged with the voltage of the data signal from an overlap period of the first portion FH of the MUX1 and the second portion SH of the SCAN1 in the second frame period FR2, the R subpixel senses the threshold voltage of the driving TFT during about ½ horizontal period (½)H and compensates for the data voltage as much as the sensed threshold voltage. On the other hand, the G subpixel operates in the same manner as the first subpixel 101A in the second frame period FR2. Because the G subpixel starts to be charged with the voltage of the data signal from an overlap period of the second portion SH of the MUX2 and the first portion FH of the SCAN1 in the second frame period FR2, the G subpixel senses the threshold voltage of the driving TFT during about one horizontal period 1H and compensates for the data voltage as much as the sensed threshold voltage.
The SCAN1 generated in the third frame period FR3 is synchronized with data signals R and G applied to the subpixels of the first pixel line LINE1. The data signal R is supplied to the first data line D1 through the first switch element M1, which is turned on in response to the MUX2, and is supplied to the R subpixel in the second portion SH of the SCAN1. The data signal G is supplied to the second data line D2 through the second switch element M2, which is turned on in response to the MUX1, and is supplied to the G subpixel in the first portion FH of the SCAN1. The R subpixel operates in the same manner as the second subpixel 101B in the third frame period FR3. Because the R subpixel starts to be charged with the voltage of the data signal from an overlap period of the first portion FH of the MUX2 and the second portion SH of the SCAN1 in the third frame period FR3, the R subpixel senses the threshold voltage of the driving TFT during about ½ horizontal period (½)H and compensates for the data voltage as much as the sensed threshold voltage. On the other hand, the G subpixel operates in the same manner as the first subpixel 101A in the third frame period FR3. Because the G subpixel starts to be charged with the voltage of the data signal from an overlap period of the second portion SH of the MUX1 and the first portion FH of the SCAN1 in the third frame period FR3, the G subpixel senses the threshold voltage of the driving TFT during about one horizontal period 1H and compensates for the data voltage as much as the sensed threshold voltage.
The SCAN1 generated in the fourth frame period FR4 is synchronized with data signals R and G applied to the subpixels of the first pixel line LINE1. The data signal R is supplied to the first data line D1 through the first switch element M1, which is turned on in response to the MUX1, and is supplied to the R subpixel in the first portion FH of the SCAN1. The data signal G is supplied to the second data line D2 through the second switch element M2, which is turned on in response to the MUX2, and is supplied to the G subpixel in the second portion SH of the SCAN1. The R subpixel operates in the same manner as the first subpixel 101A in the fourth frame period FR4. Because the R subpixel starts to be charged with the voltage of the data signal from an overlap period of the second portion SH of the MUX1 and the first portion FH of the SCAN1 in the fourth frame period FR4, the R subpixel senses the threshold voltage of the driving TFT during about one horizontal period 1H and compensates for the data voltage as much as the sensed threshold voltage. On the other hand, the G subpixel operates in the same manner as the second subpixel 101B in the fourth frame period FR4. Because the G subpixel starts to be charged with the voltage of the data signal from an overlap period of the first portion FH of the MUX2 and the second portion SH of the SCAN1 in the fourth frame period FR4, the G subpixel senses the threshold voltage of the driving TFT during about ½ horizontal period (½)H and compensates for the data voltage as much as the sensed threshold voltage.
When the R subpixel is driven in the method illustrated in
When the R subpixel is driven in the method illustrated in
As described above, the pixels according to the aspects of the disclosure are driven in the initialization operation, the operation of sensing the threshold voltage and writing data in the driving element, and the emission operation. Thus, the aspects of the present disclosure can compensate for the threshold voltage of each of the driving elements included in all the pixels and achieve the uniform luminance.
The aspects of the disclosure time-divide the data signals output through one output terminal of the data driver and distribute the divided data signals to the data lines through the demultiplexer. Further, the aspects of the disclosure supply the predetermined reference voltage using the switch array at the moment, when the data line is floated, in the operation of sensing the threshold voltage and writing data in the driving element. As a result, the aspects of the disclosure can prevent malfunction of the subpixels resulting from the parasitic capacitance
The aspects of the disclosure can implement the compensation circuit in which there is no difference in a sensing time of the threshold voltage of the driving element between the pixels, by properly combining the ON-time period of the demultiplexer and the ON-time period of the gate signal (or the scan signal) every a predetermined time. Hence, the aspects of the disclosure can implement the image quality in which there is no difference in the luminance between all the pixels.
Although aspects have been described with reference to a number of illustrative aspects thereof, it should be understood that numerous other modifications and aspects can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2017-0083271 | Jun 2017 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 7557783 | Kim | Jul 2009 | B2 |
| 8299990 | Park | Oct 2012 | B2 |
| 9870749 | Yoo | Jan 2018 | B2 |
| 10170054 | Park | Jan 2019 | B2 |
| 20060071884 | Kim | Apr 2006 | A1 |
| 20090251455 | Park et al. | Oct 2009 | A1 |
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| 20160148569 | Park et al. | May 2016 | A1 |
| Number | Date | Country |
|---|---|---|
| 10-2016-0033289 | Mar 2016 | KR |
| 10-2016-0063462 | Jun 2016 | KR |
| Entry |
|---|
| Search Report dated Aug. 7, 2018 issued in the corresponding European Patent Application No. 18177531.3, 12 Pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20190005889 A1 | Jan 2019 | US |
