Patent Application
20250081745
The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application No. 10-2023-0113996, filed on Aug. 29, 2023, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.
One or more embodiments described herein relate to a display panel and a manufacturing method thereof.
The importance of display devices has increased as information technologies evolve. Examples of display devices include liquid crystal display devices, organic light emitting display devices, and an inorganic light emitting display devices.
In a super-resolution display, the distance between sub-pixels is narrow. As a result, leakage current (or lateral leakage phenomenon) may occur between adjacent sub-pixels through a commonly provided light emitting structure. The sub-pixels, therefore, may not emit light with a desired luminance, which adversely affects display quality.
Embodiments provide a display panel and a manufacturing method thereof, which can reduce influence of a leakage current migrating between pixels, or sub-pixels, that can deteriorate the quality of images displayed by the display panel.
In accordance with an aspect of the present disclosure, there is provided a method of manufacturing a display panel, the method including: forming, on a substrate, a pixel circuit layer including a sub-pixel circuit of each of a plurality of sub-pixels; forming a first electrode of a light emitting element on the pixel circuit layer, wherein the first electrode of the light emitting element is electrically connected to the sub-pixel circuit; forming a pixel defining layer on the first electrode of the light emitting element; forming a light emitting structure of the light emitting element on the pixel defining layer; forming a hole in a boundary area between adjacent ones of the plurality of sub-pixels, wherein the hole is formed using a wire of a hole generator; and forming a second electrode of the light emitting element on the light emitting structure.
Forming the hole may include: applying a high-potential voltage to a first end of the wire; and applying a low-potential voltage to a second end of the wire.
The plurality of sub-pixels may be arranged side-by-side in a first direction and a second direction intersecting the first direction in the display panel. Forming the hole may include: forming a first hole between the plurality of sub-pixels arranged side-by-side in the first direction; and forming a second hole between the plurality of sub-pixels arranged side-by-side in the second direction.
The light emitting structure may include a first light emitting area, a charge generation layer stacked in a third direction on the first light emitting unit, and a second light emitting area stacked in the third direction on the charge generation layer. In forming the hole, the light emitting structure may be removed to a predetermined depth by the wire.
In forming the hole, the second light emitting area and the charge generation layer may be sequentially removed.
In forming the hole, at least a portion of the first light emitting area may be further removed.
In forming the hole, the pixel defining layer may be exposed.
In forming the hole, a width of the hole may be formed less than a width of a top surface of the pixel defining layer.
In forming the hole, at least a portion of the first light emitting area may be exposed.
In forming the hole, a width of the hole may be formed less than a width of a top surface of the pixel defining layer.
In forming the hole, a width of the hole may be formed to be greater than a width of a top surface of the pixel defining layer.
The hole and the first electrode of the light emitting element may be located while overlapping with each other in the third direction.
The wire may include silver and have a width of 200 nm.
In the forming of the hole, any one of the substrate and the hole generator may be rotated by 90 degrees.
In accordance with another aspect of the present disclosure, there is provided a display panel including: a substrate having a plurality of sub-pixels disposed thereon; a pixel circuit layer disposed on the substrate, the pixel circuit layer including a sub-pixel circuit of each of the plurality of sub-pixels; and a light emitting element layer disposed on the pixel circuit layer, the light emitting element layer including a plurality of light emitting elements, each including a first electrode, a light emitting structure, and a second electrode, the light emitting element layer having a hole at least a portion of the light emitting structure in a boundary area between the plurality of sub-pixels. The hole may be formed using the wire of a hole generator.
The plurality of sub-pixels may be arranged side-by-side in a first direction and a second direction intersecting the first direction. The hole may be located between the plurality of sub-pixels arranged side-by-side in the first direction and between the plurality of sub-pixels arranged side-by-side in the second direction.
The light emitting structure may include: a first light emitting unit including a first light emitting layer; a charge generation layer stacked in a third direction on the first light emitting unit; and a second light emitting unit including a second light emitting layer, the second light emitting unit being stacked in the third direction on the charge generation layer. The hole may be located in an area in which the second light emitting unit and the charge generation layer are removed.
The hole may be located in an area in which the first light emitting unit is further removed.
The hole and the first electrode of the light emitting element may overlap with each other in the third direction.
In accordance with one or more embodiments, a display panel includes a first sub-pixel including a first electrode; a second sub-pixel including a second electrode adjacent to the first electrode; and a light emitting structure disposed on the first electrode and the second electrode, wherein the light emitting structure includes a hole disposed at a location between the first sub-pixel and the second sub-pixel, the hole extending to a depth that removes a charge generation layer between a stacked arrangement of different light emitting areas of at least one of the first sub-pixel and the second sub-pixel.
The display panel may include a pixel defining layer commonly included in the first sub-pixel and the second sub-pixel. The depth of the hole may be less than a distance between a top surface of the first electrode and a top surface of the light emitting structure. The hole may overlap the pixel defining layer. The hole may have a width that is less than a width between the first electrode and the second electrode.
The hole may have a width that is less than a width between the first electrode and the second electrode. The hole may have a width greater than a width between the first electrode and the second electrode. The hole may overlap respective portions of the first electrode and the second electrode. The depth of the hole may be less than a distance between a top surface of the first electrode and a top surface of the light emitting structure.
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.
In the drawing figures, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.
Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art may easily practice the present disclosure. The present disclosure may be implemented in various different forms and is not limited to the exemplary embodiments described in the present specification.
A part irrelevant to the description will be omitted to clearly describe the present disclosure, and the same or similar constituent elements will be designated by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements.
In addition, the size and thickness of each component illustrated in the drawings are arbitrarily shown for better understanding and ease of description, but the present disclosure is not limited thereto. Thicknesses of several portions and regions are exaggerated for clear expressions.
In description, the expression “same”, “equal” may mean “substantially same”, “substantially equal”. That is, this may mean equality to a degree to which those skilled in the art can understand the equality. Other expressions may be expressions in which “substantially” is omitted.
It will be understood that, although the terms “first”, “second” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a “first” element discussed below could also be termed a “second” element without departing from the teachings of the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Spatially relative terms, such as “below”, “above” and the like, may be used herein for ease of description to describe the relationship of one element to another element, as illustrated in the figures. It will be understood that the spatially relative terms, as well as the illustrated configurations, are intended to encompass different orientations of the apparatus in use or operation in addition to the orientations described herein and depicted in the figures. For example, if the apparatus in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term, “above” may encompass both an orientation of above and below. The apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Unless defined otherwise, it is to be understood that all the terms (including technical and scientific terms) used in the specification has the same meaning as those that are understood by those who skilled in the art. Further, the terms defined by the dictionary generally used should not be ideally or excessively formally defined unless clearly defined specifically.
It will be further understood that the terms “includes” and/or “including”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence and/or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
In the entire specification, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the another element or be indirectly connected or coupled to the another element with one or more intervening elements interposed therebetween. The technical terms used herein are used only for the purpose of illustrating a specific embodiment and not intended to limit the embodiment. It will be understood that when a component “includes” an element, unless there is another opposite description thereto, it should be understood that the component does not exclude another element but may further include another element. It will be understood that for the purposes of this disclosure, “at least one of X, Y, and Z” can be construed as X only, Y only, Z only, or any combination of two or more items of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Similarly, for the purposes of this disclosure, “at least one selected from the group consisting of X, Y, and Z” can be construed as X only, Y only, Z only, or any combination of two or more items of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ).
In addition, the embodiments of the disclosure are described here with reference to schematic diagrams of ideal embodiments (and an intermediate structure) of the present disclosure, so that changes in a shape as shown due to, for example, manufacturing technology and/or a tolerance may be expected. Therefore, the embodiments of the present disclosure shall not be limited to the specific shapes of a region shown here, but include shape deviations caused by, for example, the manufacturing technology. The regions shown in the drawings are schematic in nature, and the shapes thereof do not represent the actual shapes of the regions of the device, and do not limit the scope of the disclosure.
Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Referring to
The display panel 110 may include a plurality of pixels PXL, each including a plurality of sub-pixels SP. First to mth gate lines GL1 to GLm (m is an integer of 2 or more) connected to the plurality of sub-pixels SP may be disposed in the display panel 110. First to nth data lines DL1 to DLn (n is an integer of 2 or more), which are connected to the plurality of sub-pixels SP, may be disposed in the display panel 110.
The plurality of sub-pixels SP may be connected (e.g., electrically connected) to the gate driving circuit 120 through the first to mth gate lines GL1 to GLm. The plurality of sub-pixels SP may be connected (e.g., electrically connected) to the data driver 130 through the first to nth data lines DL1 to DLn.
Each of the plurality of sub-pixels SP may include at least one light emitting element configured to generate light. Each of the plurality of sub-pixels SP may generate light of a predetermined color (e.g., a specific color or a specific wavelength band) such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels SP among the plurality of sub-pixels SP may constitute one pixel PXL. For example, three sub-pixels SP may constitute one pixel PXL as shown in
The gate driving circuit 120 may be connected (e.g., electrically connected) to the plurality of sub-pixels SP (e.g., the plurality of sub-pixels SP entirely arranged in a first direction DR1) through the first to mth gate lines GL1 to GLm. The first direction DR1 may be, for example, a direction crossing the display panel 110 from one side (e.g., a left side) to the other side (e.g., a right side) of the display panel 110. The first direction DR1 may be, for example, a row direction.
The gate driving circuit 120 may output gate signals (e.g., gate signals having a turn-on level or a turn-off level) to the first to mth gate lines GL1 to GLm in response to a gate control signal GCS. In embodiments, the gate control signal GCS may include a start signal indicating a start of each frame, a horizontal synchronization signal for outputting gate signals in synchronization with timings at which data signals are applied, and/or other signals.
In embodiments, first to mth emission control lines EL1 to ELm (which are connected to the plurality of sub-pixels SP) may be further disposed in the display panel 110. The first to mth emission control lines EL1 to ELm may be disposed in the display panel 110 and extend in the row direction. The plurality of sub-pixels SP may be connected (e.g., electrically connected) to the first to mth emission control lines EL1 to ELm. In the above embodiment, the gate driving circuit 120 may include an emission control driver configured to control the first to mth emission control lines EL1 to ELm. In one embodiment, the emission control driver may be provided separately from the gate driving circuit 120. The emission control driver may operate under the control of the controller 150.
The gate driving circuit 120 may be disposed at one side of the display panel 110. However, embodiments of the present disclosure are not limited thereto. For example, the gate driving circuit 120 may be divided into two or more driving circuits which are physically and/or logically divided, and these driving circuits may be disposed at one side of the display panel 110 and the other side of the display panel 110 (e.g., the other side of the display panel 110, which faces the one side of the display panel 110). As such, in some embodiments, the gate driving circuit 120 may be disposed in various forms in the display panel 110 or at the periphery of the display panel 110.
The data driver 130 may be connected (e.g., electrically connected) to the plurality of sub-pixels SP (e.g., the plurality of sub-pixels SP entirely arranged in a second direction DR2) through the first to nth data lines DL1 to DLn. The second direction DR2 may be, for example, a direction crossing the display panel 110 from one side (e.g., a lower side) of the display panel 110 to the other side (e.g., an upper side) of the display panel 110. The second direction DR2 may be, for example, a column direction.
The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In embodiments, the data control signal DCS may include one or more of a source start pulse, a source shift clock, a source output enable signal, and/or other signals.
The data driver 130 may apply grayscale voltages corresponding to the image data DATA to the first to nth data lines DL1 to DLn by using voltages (e.g., gamma voltages Vgamma) from the voltage generator 140. When a gate signal (e.g., a gate signal having the turn-on level) is applied to each of the first to mth gate lines GL1 to GLm, data signals corresponding to the image data DATA may be applied to the data line DL1 to DLn. Each of the plurality of sub-pixels SP may receive a data signal applied at a corresponding timing in response to the gate signal (e.g., the gate signal having the turn-on level). Each of the plurality of sub-pixels SP may generate light corresponding to the received data signal. Accordingly, an image may be displayed in the display panel 110.
In embodiments, each of the gate driving circuit 120 and the data driver 130 may include complementary metal-oxide semiconductor (CMOS) circuit elements.
The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may receive an input voltage from a source outside of the display device 100. The voltage generator 140 may adjust (e.g., decrease) a level of the received input voltage and regulate the voltage having the adjusted level. The voltage generator 140 may be configured to generate a plurality of voltages.
The voltage generator 140 may generate, for example, a first power voltage VDD, a second power voltage VSS, a gamma voltage Vgamma, and the like. The generated first and second power voltages VDD and VSS may be applied (e.g., commonly applied) to the plurality of sub-pixels SP. The first power voltage VDD may have a relatively high voltage level. The second power voltage VSS may have a voltage level lower than the voltage level of the first power voltage VDD. The generated gamma voltage Vgamma may be provided to the data driver 130. In other embodiments, the first power voltage VDD and/or the second power voltage VSS may be provided by an external device of the display device 100 (e.g., a Power Management Integrated Circuit (PMIC)).
In some embodiments, the voltage generator 140 may also generate another voltage. For example, the voltage generator 140 may generate an initialization voltage that is to be applied (e.g., commonly applied) to the plurality of sub-pixels SP. For example, in a sensing operation for sensing electrical characteristics of transistors and/or a light emitting element(s) of the plurality of sub-pixels SP, a predetermined reference voltage may be applied to the first to nth data lines DL1 to DLn, and the voltage generator 140 may generate the reference voltage.
The controller 150 may be configured to control overall operation of the display device 100. The controller 150 may receive, from an external source, input image data IMG and a control signal CTRL for controlling display thereof. The controller 150 may provide the gate control signal GCS, the data control signal DCS, the voltage control signal VCS, and the like in response to the received control signal CTRL.
The controller 150 may convert the input image data IMG that is suitable for the display device 100 or the display panel 110, so that the image data DATA may be output. In embodiments, the controller 150 may align the input image data IMG to be suitable for the sub-pixels SP in units of rows, to thereby output the image data DATA.
Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. As shown in
The temperature sensor 160 may be configured to sense a temperature (e.g., a temperature at the periphery thereof) and generate temperature data TEP indicating the sensed temperature. In some embodiments, the temperature sensor 160 may be disposed in the display panel 110. In some embodiments, the temperature sensor 160 may be disposed to be adjacent to the display panel 110 and/or the driver integrated circuit DIC. In some embodiments, the display device 100 may include two or more temperature sensors 160.
The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In embodiments, the controller 150 may adjust the luminance of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may adjust at least one of the data signals, the first power voltage VDD, or the second power voltage VSS, which are input to the display panel 110, by controlling components such as the data driver 130 and/or the voltage generator 140.
Referring to
The light emitting element LD may include a first electrode AE, a light emitting structure EMS, and a second electrode CE. The first electrode AE may be any one of an anode electrode or a cathode electrode of the light emitting element LD. The second electrode CE may be the other of the anode electrode or the cathode electrode of the light emitting element LD. Hereinafter, for convenience of description, a case where the first electrode AE of the light emitting element LD is the anode electrode and the second electrode CE of the light emitting element LD is the cathode electrode is described as an example.
The first electrode AE of the light emitting element LD may be connected (e.g., electrically connected) to the first power voltage node VDDN through the sub-pixel circuit SPC. The second electrode CE of the light emitting element LD may be connected (e.g., electrically connected) to the second power voltage node VSSN. For example, the first electrode AE of the light emitting element LD may be connected (e.g., electrically connected) to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.
The sub-pixel circuit SPC of the sub-pixel SPij may be connected (e.g., electrically connected) to an ith gate line GLi among the first to mth gate lines GL1 to GLm shown in
The sub-pixel circuit SPC may operate in response to a gate signal received through the ith gate line GLi. The sub-pixel circuit SPC may also operate in response to an emission control signal received through the ith emission control line ELi.
The sub-pixel circuit SPC may receive a data signal through a jth data line DLj. The sub-pixel circuit SPC may store a voltage of the data signal (or a voltage corresponding to the data signal) in response to the gate signal (e.g., the gate signal having the turn-on level) received through the ith gate line GLi. The sub-pixel circuit SPC may adjust a timing at which a current flows through the light emitting element LD in response to the emission control signal (e.g., the emission control signal having the turn-on level) applied through the ith emission control line ELi. The magnitude of the current flowing through the light emitting element LD may vary according to a voltage stored in the sub-pixel circuit SPC. The light emitting element LD may generate light with a luminance corresponding to the data signal.
An embodiment of a display panel DP shown in
Referring to
The display panel DP may include a substrate SUB, a plurality of sub-pixels SP disposed (or formed) on the substrate SUB, and a plurality of signal pads PD disposed (or formed) on the substrate SUB.
When the display panel DP in accordance with the embodiments of the present disclosure is used as a display screen of a Head Mounted Display (HMD), a Virtual Reality (VR) device, a Mixed Reality (MR) device, an Augmented Reality (AR) device, and the like, the display panel DP may be located very close to eyes of a user. In the above embodiment, it may be that the sub-pixels SP are to be integrated with a relatively high density. In order to increase integration of the sub-pixels SP, the substrate SUB in accordance with the embodiments of the present disclosure may be provided as a silicon substrate. The sub-pixels SP may be formed on the substrate SUB as the silicon substrate. The display device 100 (e.g., see
The plurality of sub-pixels SP may be disposed in the display area DA on the substrate SUB. Referring to
A component for controlling the sub-pixels SP may be disposed in the non-display area NDA on the substrate SUB. For example, lines such as the first to mth gate lines GL1 to GLm and the first to nth data lines DL1 to DLn, which, for example, are shown in
At least one of the gate driving circuit 120, the data driver 130, the voltage generator 140, the controller 150, or the temperature sensor 160, which are shown in
In an embodiment, the gate driving circuit 120 shown in
In an embodiment, the temperature sensor 160 shown in
The signal pads PD may be disposed in the non-display area NDA on the substrate SUB. The signal pads PD may be electrically connected to the sub-pixels SP through the lines. For example, the signal pads PD may be connected to the sub-pixels SP through the first to nth data lines DL1 to DLn.
The signal pads PD may interface the display panel DP, for example, with other components of the display device 100 (e.g., see
In embodiments, a circuit board may be electrically connected to the signal pads PD, using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a Flexible Printed Circuit Board (FPCB) or a flexible film, which has a flexible material. The driver integrated circuit DIC (see
In embodiments, the display area DA may have one of various shapes. For example, the display area DA may have a closed-loop shape including linear sides and/or curved sides. For example, the display area DA may have shapes such as a polygon, a circle, a semicircle, and an ellipse.
In embodiments, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may at least partially have a round display surface. In embodiments, the display panel DP may be bendable, foldable or rollable. The display panel DP and/or the substrate SUB may include rigid or flexible materials.
In
Referring to
In
The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a thin film encapsulation layer TFE, an optical functional layer OFL, an overcoat layer OC, and a cover window CW.
In embodiments, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and/or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a Silicon On Insulator (SOI) layer, a Semiconductor On Insulator (SeOI) layer, or the like. In other embodiments, the substrate SUB may include a glass substrate. In still other embodiments, the substrate SUB may include a polyimide (PI) substrate.
The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and/or the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL may serve as at least some of circuit elements, lines, and the like. The conductive patterns may include copper, but embodiments are not limited thereto.
The circuit elements may include a sub-pixel circuit SPC (see
The lines of the pixel circuit layer PCL may include signal lines, e.g., a gate line, an emission control line, a data line, and the like, which are connected to each of the first to third sub-pixels SP1 to SP3. The lines may further include a line connected to the first power voltage node VDDN shown in
The light emitting element layer LDL may include first electrodes AE, a pixel defining layer PDL, a light emitting structure EMS, and a second electrode CE. The first electrodes AE may be disposed on the pixel circuit layer PCL and, for example, may be anode electrodes. The first electrodes AE may be connected to (e.g., be in contact with) the circuit elements of the pixel circuit layer PCL. The first electrodes AE may include an opaque conductive material capable of reflecting light. However, embodiments of the present disclosure are not limited thereto.
The pixel defining layer PDL may be disposed on the first electrodes AE. The pixel defining layer PDL may include an opening OP exposing a portion of each of the first electrodes AE. The opening OP of the pixel defining layer PDL may be an emission area of each of the first to third sub-pixels SP1 to SP3.
In embodiments, the pixel defining layer PDL may include an inorganic material. In the above embodiment, the pixel defining layer PDL may include an inorganic layer (e.g., a plurality of stacked inorganic layers). For example, the pixel defining layer PDL may include silicon oxide (SiOx) and/or silicon nitride (SiNx). In other embodiments, the pixel defining layer PDL may include an organic layer including an organic material. However, the material constituting the pixel defining layer PDL in accordance with the embodiments of the present disclosure is not limited as described above.
The light emitting structure EMS may be disposed on the first electrodes AE exposed by the openings OP of the pixel defining layer PDL. The light emitting structure EMS may include at least one functional layer. The light emitting structure EMS may include, for example, a plurality of functional layers such as a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.
In embodiments, the light emitting structure EMS may fill the openings OP of the pixel defining layer PDL. In embodiments, the light emitting structure EMS may be entirely disposed on the top of the pixel defining layer PDL. For example, the light emitting structure EMS may extend throughout the first to third sub-pixels SP1 to SP3. In the above embodiment, at least some of the functional layers in the light emitting structure EMS may be cut or curved at boundaries between the first to third sub-pixels SP1 to SP3. However, embodiments of the present disclosure are not limited thereto. For example, portions of the light emitting structure EMS, which correspond to the first to third sub-pixels SP1 to SP3, may be separated from each other, and each of the portions may be disposed in the openings OP of the pixel defining layer PDL.
The second electrode CE may be disposed on the light emitting structure EMS and, for example, may be a cathode electrode. The second electrode CE may extend throughout (or overlap) the first to third sub-pixels SP1 to SP3. The second electrode CE may be provided as a common electrode commonly connected to the first to third sub-pixels SP1 to SP3.
The second electrode CE may have light transmissivity. For example, the second electrode CE may be a thin metal layer having a thickness to a degree to which light emitted from the light emitting structure EMS can be transmitted therethrough. The second electrode CE may be formed of a metal material to have a relatively thin thickness or be formed of a conductive material having light transmissivity (e.g., transparency). In embodiments, the second electrode CE may include at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. However, the material constituting the second electrode CE in accordance with the embodiments of the present disclosure is not limited as described above. In one embodiment, the second electrode CE may serve as a half mirror which allows light emitted from the light emitting structure EMS to be partially transmitted therethrough and allows light emitted from the light emitting structure EMS to be partially reflected therefrom.
It may be understood that any one of the first electrodes AE, a portion of the light emitting structure EMS (which overlaps therewith), and a portion of the second electrode CE (which overlaps therewith) constitute one light emitting element LD (e.g., see
The thin film encapsulation layer TFE may be disposed over the second electrode CE. The thin film encapsulation layer TFE may cover the light emitting element layer LDL and/or the pixel circuit layer PCL. The thin film encapsulation layer TFE may be configured to prevent oxygen and/or moisture from infiltrating into the light emitting element layer LDL. In embodiments, the thin film encapsulation layer TFE may include a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. For example, the inorganic layer may include silicon nitride, silicon oxide, silicon oxynitride (SiOxNy), or the like. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, polyphenylenesulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the thin film encapsulation layer TFE are not limited as described above.
In order to improve encapsulation efficiency of the thin film encapsulation layer TFE, the thin film encapsulation layer TFE may further include a thin film including aluminum oxide (AlOx). The thin film including the aluminum oxide may be located on a top surface of the thin film encapsulation layer TFE (which faces the optical functional layer OFL) and/or a bottom surface of the thin film encapsulation layer TFE which faces the light emitting element layer LDL. The thin film including the aluminum oxide may be formed, for example, through an Atomic Layer Deposition (ALD) process. However, embodiments of the present disclosure are not limited thereto. The thin film encapsulation layer TFE may further include a thin film formed of at least one of various materials suitable for improvement of the encapsulation efficiency.
The optical functional layer OFL may be disposed on the thin film encapsulation layer TFE. The optical functional layer OFL may include a color filter layer CFL and a lens array LA. In embodiments, the optical functional layer OFL may be attached to the thin film encapsulation layer TFE through an adhesive layer. For example, the optical functional layer OFL may be separately manufactured to be attached to the thin film encapsulation layer TFE through the adhesive layer. The adhesive layer may further perform a function of protecting lower layers including the thin film encapsulation layer TFE.
The color filter layer CFL may be disposed between the thin film encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter light emitted from the light emitting structure EMS, to thereby selectively output light having a wavelength band corresponding to each sub-pixel SP.
The color filter layer CFL may include color filters CF respectively corresponding to the first to third sub-pixels SP1 to SP3. Each of the color filters CF may allow light having a wavelength band corresponding to a corresponding sub-pixel SP to pass therethrough. For example, a color filter CF corresponding to the first sub-pixel SP1 may allow light of a first (e.g., red) color to pass therethrough, a color filter CF corresponding to the second sub-pixel SP2 may allow light of a second (e.g., green) color to pass therethrough, and a color filter corresponding to the third sub-pixel SP3 may allow light of a third (e.g., blue) color to pass therethrough. According to light emitted from the light emitting structure EMS in each sub-pixel SP, at least some of the color filters CF may be omitted. In some embodiments, the color filter layer CFL may be omitted. In embodiments, the color filters CF may overlap (e.g., partially overlap) with each other in boundary areas between the first to third sub-pixels SP1 to SP3. In other embodiments, the color filters CF may be spaced apart from each other in the boundary areas between the first to third sub-pixels SP1 to SP3, and a black matrix may be provided between the color filters CF.
The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS respectively corresponding to the first to third sub-pixels SP1 to SP3. Each of the lenses LS may output light emitted from the light emitting structure EMS along an intended path, thereby improving light emission efficiency. In embodiments, the lenses LS may include an organic material. In embodiments, the lenses LS may include an acryl-based material. However, the material of the lenses LS is not limited thereto.
In embodiments, as compared with the opening OP of the pixel defining layer PDL, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be shifted in a direction parallel to a plane defined by the first and second directions DR1 and DR2. For example, in a central area of the display area DA, the center of the color filter CF and the center of the lens LS may be aligned or overlap with the center of a corresponding opening OP of the pixel defining layer PDL when viewed in the third direction DR3. For example, in the central area of the display area DA, the opening OP of the pixel defining layer PDL may completely overlap with a corresponding color filter CF of the color filter layer CFL and a corresponding lens LS of the lens array LA. In an area adjacent to the non-display area NDA of the display area DA, the center of the color filter CF and the center of the lens LS may be shifted in a plane direction from the center of the opening OP of the pixel defining layer PDL when viewed in the third direction DR3. For example, in an area adjacent to the non-display area NDA of the display area DA, the opening OP of the pixel defining layer PDL may partially overlap with a corresponding color filter CF of the color filter layer CFL and a corresponding lens LS of the lens array LA. Accordingly, at the center of the display area DA, light emitted from the light emitting structure EMS can be efficiently output in a normal direction of the display surface. At an outer portion of the display area DA, light emitted from the light emitting structure EMS can be efficiently output in a direction inclined by a predetermined angle with respect to the normal direction.
The overcoat layer OC may be disposed over the lens array LA. The overcoat layer OC may cover the optical functional layer OFL, the thin film encapsulation layer TFE, the light emitting structure EMS, and/or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting lower layers thereof from foreign matters such as dust, debris and moisture. For example, the overcoat layer OC may include an inorganic insulating layer. For example, the overcoat layer OC may include epoxy, but embodiments are not limited thereto. The overcoat layer OC may have a refractive index lower than a refractive index of the lens array LA.
The cover window CW may be disposed on the overcoat layer OC. The cover window CW may be configured to protect lower layers thereof. The cover window CW may have a refractive index different from (e.g., higher than) the refractive index of the overcoat layer OC. The cover window CW may include glass, but embodiments are not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect components disposed on the bottom thereof. In other embodiments, the cover window CW may be omitted.
The first sub-pixel SP1 may include a first emission area EMA1 and a non-emission area NEA at the periphery of the first emission area EMA1. The second sub-pixel SP2 may include a second emission area EMA2 and the non-emission area NEA at the periphery of the second emission area EMA2. The third sub-pixel SP3 may include a third emission area EMA3 and the non-emission area NEA at the periphery of the third emission area EMA3.
The first emission area EMA1 may be an area in which light is emitted from a portion of the light emitting structure EMS (e.g., see
To increase resolution, efforts are being made to reduce the sizes of pixels PXL. As the size of the first pixel PXL1 becomes smaller, the distance between the first to third sub-pixels SP1 to SP3 may become smaller. Accordingly, a leakage current may flow in an adjacent sub-pixel SP. Therefore, display quality may be deteriorated by the leakage current. In addition, the leakage current may flow in an adjacent sub-pixel SP through the light emitting structure EMS (e.g., see
Referring to
The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor of the first sub-pixel SP1, a transistor of the second sub-pixel SP2, and a transistor of the third sub-pixel SP3.
Each of the first to third sub-pixels SP1 to SP3 may include a first electrode AE. Referring to
The pixel defining layer PDL may be disposed on portions of the first electrodes AE1 to AE3 and the pixel circuit layer PCL (e.g., a planarization layer of the pixel circuit layer PCL). The pixel defining layer PDL may include openings OP (e.g., see also
In embodiments, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include at least one of silicon oxide (SiOx) or silicon nitride (SiNx). For example, the pixel defining layer PDL may include first to third inorganic insulating layers which are sequentially stacked, and each of the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon oxynitride. However, embodiments of the present disclosure are not limited thereto. The first to third inorganic insulating layers may have a step-shaped section in an area adjacent to the opening OP.
The light emitting structure EMS may be disposed on the first electrodes AE exposed by the openings OP (e.g., see also
In accordance with one or more embodiments described herein, as shown in
For example, the first hole 710 may be located in a boundary area between adjacent sub-pixels SP. Referring to
As further shown in
The width (e.g., width in the first direction DR1 or the second direction DR2) of the first hole 710 may be a first width WT1. The depth (e.g., a depth in the third direction DR3) of the first hole 710 may be a first depth DEP1. The width and the depth of the first hole 710 may be described relative to the pixel defining layer PDL. For example, the width of a top surface of the pixel defining layer PDL may be a reference width WTr. The distance from a top surface of the light emitting structure EMS to the top surface of the pixel defining layer PDL may be a reference depth DEPr. In accordance with one embodiment, the width (or the first width WT1) of the first hole 710 may be less than the reference width WTr, and the depth (or the first depth DEP1) of the first hole 710 may be less than the reference depth DEPr.
Referring to
The width (e.g., a width in the first direction DR1 or the second direction DR2) of the second hole 810 may be a first width WT1. The depth (e.g., a depth in the third direction DR3) of the second hole 810 may be a second depth DEP2. The width and the depth of the second hole 810 may be described relative to the pixel defining layer PDL. The width of a top surface of the pixel defining layer PDL may be a reference width WTr. The distance from a top surface of the light emitting structure EMS to the top surface of the pixel defining layer PDL may be a reference depth DEPr. The width (or the first width WT1) of the second hole 810 may be less than the reference width WTr. In accordance with the present embodiment, the depth (or the second depth DEP2) of the second hole 810 may be equal (or substantially equal) to the reference depth DEPr. As shown, at least a portion of the pixel defining layer PDL (e.g., the top surface of the pixel defining layer PDL) may be exposed by the second hole 810.
Referring to
The third hole 910 may overlap (e.g., overlap in the third direction DR3) with at least a portion of the first electrode AE1 of the first sub-pixel SP1. In one embodiment, the third hole 910 may also overlap (e.g., overlap in the third direction DR3) with at least a portion of the first electrode AE2 of the second sub-pixel SP2. The other third hole 910 may overlap (e.g., overlap in the third direction DR3) with at least a portion of the first electrode AE3 of the third sub-pixel SP3. The degree to which the third hole 910 overlaps adjacent ones of the first electrodes AE may be the same or different.
The width (e.g., a width in the first direction DR1 or the second direction DR2) of the third hole 910 may be a second width WT2. The depth (e.g., a depth in the third direction DR3) of the third hole 910 may be the first depth DEP1. The width and the depth of the third hole 910 may be described relative to the pixel defining layer PDL. The width of a top surface of the pixel defining layer PDL may be the reference width WTr. The distance from a top surface of the light emitting structure EMS to the top surface of the pixel defining layer PDL may be the reference depth DEPr. The width (or the second width WT2) of the third hole 910 may be greater than the reference width WTr, and the depth (or the first depth DEP1) of the third hole 910 may be less than the reference depth DEPr.
The third hole 910 may define the non-emission area NEA (see
The hole CUH described with reference to
According to the manufacturing method used to form the hole CUH using the wire, the hole CUH may be formed regardless of any material located while overlapping (e.g., located while overlapping in the third direction DR3) with the area in which the hole CUH is formed. For example, according to the above-described manufacturing method of the hole CUH, the hole CUH may be easily formed even when a material (e.g., the first electrode AE of the light emitting element, or the like) capable of reflecting light is located while overlapping with the area in which the hole CUH is formed.
On the other hand, when at least a portion of the light emitting structure EMS is removed using laser, the laser is reflected in an area in which a material (e.g., a metal or the like) capable of reflecting light is located under an area onto which the laser is irradiated. In this case, it may be difficult to appropriately remove the material of the light emitting structure EMS to form the hole CUH. Such a technical difficulty may occur, for example, when a display device (e.g., an OLEDoS display device) is manufactured to have pixels that are integrated with a high density or resolution.
Referring to
Each of the first and second light emitting units EU1 and EU2 may include a light emitting layer configured to generate light according to an applied current. The first light emitting unit EU1 may include a first light emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light emitting unit EU2 may include a second light emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.
Each of the first and second hole transport units HTU1 and HTU2 may include at least one of a hole injection layer and a hole transport layer. In some embodiments, each of the first and second hole transport units HTU1 and HTU2 may further include a hole buffer layer, an electron blocking layer, and the like. The first and second hole transport units HTU1 and HTU2 may have the same configuration or different configurations.
Each of the first and second electron transport units ETU1 and ETU2 may include at least one of an electron injection layer and an electron transport layer. In some embodiments, each of the first and second electron transport units ETU1 and ETU2 may further include an electron buffer layer, a hole blocking layer, and the like. The first and second electron transport units ETU1 and ETU2 may have the same configuration or different configurations.
A connection layer may be provided in the form of a charge generation layer CGL between the first light emitting unit EU1 and the second light emitting unit EU2. The connection layer may electrically connect the first light emitting unit EU1 and the second light emitting unit EU2 to each other. In embodiments, the charge generation layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ or NDP-9. For example, the n-dopant layer may include an alkali metal, an alkali earth metal, a lanthanide-based metal, or any combination thereof. However, embodiments of the present disclosure are not limited thereto.
In embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of different colors (or wavelength bands). Light respectively emitted from the first light emitting layer EML1 and the second light emitting layer EML2 may be mixed together to be viewed as white light. For example, the first light emitting layer EML1 may generate light of a blue color, and the second light emitting layer EML2 may generate light of a yellow color. In embodiments, the second light emitting layer EML2 may include a structure in which a first sub-light emitting layer configured to generate light of a red color and a second sub-light emitting layer configured to generate light of a green color are stacked. In one embodiment, red color light and green color light may be mixed together to provide the light of the yellow color. An intermediate layer (or functional layer) configured to perform a function of transporting holes and/or a function of blocking transportation of electrons may be further disposed between the first and second sub-light emitting layers.
In other embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of the same color (or wavelength band).
In embodiments, the light emitting structure EMS may be formed through a process such as vacuum deposition or inkjet printing, but embodiments are not limited thereto.
Without hole CUH, leakage current may be generated between adjacent sub-pixels SP due to charges generated in the charge generation layer CGL. In accordance with embodiments described herein, because the charge generation layer CGL is removed at a boundary area between the sub-pixels SP, a phenomenon in which the leakage current is generated can be reduced (or prevented), thereby preventing deterioration of images displayed by the display device.
Without hole CUH, leakage current may be generated between adjacent sub-pixels SP due to charges generated in the charge generation layer CGL. In accordance with one or more embodiments, the charge generation layer CGL is removed at a boundary area between the sub-pixels SP, so that a phenomenon in which the leakage current is generated can be reduced (or prevented), thereby preventing deterioration of images generated by the display device.
Referring to
Each of the first to third hole transport units HTU1′ to HTU3′ may include at least one of a hole injection layer and a hole transport layer. In some embodiments, each of the first to third hole transport units HTU1′ to HTU3′ may further include a hole buffer layer, an electron blocking layer, and the like. The first to third hole transport units HTU1′ to HTU3′ may have the same configuration or have different configurations.
Each of the first to third electron transport units ETU1′ to ETU3′ may include at least one of an electron injection layer and an electron transport layer. In some embodiments, each of the first to third electron transport units ETU1′ to ETU3′ may further include an electron buffer layer, a hole blocking layer, and the like. The first to third electron transport units ETU1′ to ETU3′ may have the same configuration or different configurations.
A first charge generation layer CGL1′ may be disposed between the first light emitting unit EU1′ and the second light emitting unit EU2′. A second charge generation layer CGL2′ may be disposed between the second light emitting unit EU2′ and the third light emitting unit EU3′.
In embodiments, the first to third light emitting layers EML1′ to EML3′ may generate light of different colors (or wavelength bands). Light respectively emitted from the first to third light emitting layers EML1′ to EML3′ may be mixed together to form white light. For example, the first light emitting layer EML1′ may generate light of a first wavelength band (e.g., a blue color), the second light emitting layer EML2′ may generate light of a second wavelength band (e.g., a green color), and the third light emitting layer EML3′ may generate light of a third wavelength band (e.g., a red color). In other embodiments, at least two light emitting layers of the first to third light emitting layers EML1′ to EML3′ may generate light of the same color (or wavelength band).
The depth of the hole CUH may be a first depth DEP1. The hole CUH shown in
Without hole CUH, leakage current may be generated between adjacent sub-pixels SP due to charges generated in the first charge generation layer CGL1′ and/or the second charge generation layer CGL2′. In accordance with the present embodiment, the first charge generation layer CGL1′ and the second charge generation layer CGL2′ are removed at a boundary area between the sub-pixels SP, so that a phenomenon in which the leakage current is generated can be reduced (or prevented), thereby preventing deterioration of images generated by the display device.
Without hole CUH, leakage current may be generated between adjacent sub-pixels SP due to charges generated in the first charge generation layer CGL1′ and/or the second charge generation layer CGL2′. In accordance with one or more embodiments, the first charge generation layer CGL1′ and the second charge generation layer CGL2′ are removed at a boundary area between the sub-pixels SP, so that a phenomenon in which the leakage current is generated can be reduced (or prevented), thereby preventing deterioration of images displayed by the display device.
Referring to
The first and second units 1610 and 1620 may supply voltages of predetermined levels. For example, one (e.g., the first unit 1610) of the first unit 1610 or the second unit 1620 may supply a high-potential voltage, and the other (e.g., the second unit 1620) of the first unit 1610 or the second unit 1620 may supply a low-potential voltage.
The high-potential voltage may be applied to the one end of the wire 1630, and the low-potential voltage may be applied to the other end of the wire 1630. A voltage may be applied to the wire 1630, and heat may be generated in the wire 1630 by resistance of the wire 1630. A hole may be formed in the display panel MDP by the heat generated in the wire 1630. The wire 1630 may include silver (Ag), but may be made of a different conductive material in another embodiment. The wire 1630 may have a predetermined width. For example, the wire 1630 may have a width of about 200 nm (nanometer), but the embodiments of the present disclosure are not limited thereto.
Referring to
Referring to
Referring to
As compared with
Referring to
Referring to
Referring to
Referring to
The wire 1630 may have a resistance, e.g., a predetermined resistance R. Heat may be generated in the wire 1630 based on the potential difference Vs between ends of the wire 1630. The above-described hole CUH may be formed in the display panel MDP (e.g., see
Referring to
In
Through the first channel CH1, the processor 2010 may transmit first image data IMG1 and a first control signal CTRL1 to the first display device 2020. The first display device 2020 may display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 2020 may be configured identically to the display device 100 described with reference to
Through the second channel CH2, the processor 2010 may transmit second image data IMG2 and a second control signal CTRL2 to the second display device 2030. The second display device 2030 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 2030 may be configured identically to the display device 100 described with reference to
The display system 2000 may include a computing system for providing an image display function. Examples include a portable computer, a mobile phone, a smartphone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, or an ultra mobile computer (UMPC). Also, the display system 2000 may include at least one of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.
Referring to
The head mounted display device 2100 may include a head mounting band 2110 and a display device accommodating case 2120. The head mounting band 2110 may be connected to the display device accommodating case 2120. The head mounting band 2110 may include a horizontal band and/or a vertical band, used to fix the head mounted display device 2100 to the head of the user. The horizontal band may be configured to surround a side portion of the head of the user, and the vertical band may be configured to surround an upper portion of the head of the user. However, embodiments are not limited thereto. For example, the head mounting band 2110 may be implemented in the form of a glasses frame, a helmet or the like.
The display device accommodating case 2120 may accommodate the first and second display devices 2020 and 2030 shown in
Referring to
In the display device accommodating case 2120, the right-eye lens RLNS may be disposed between the first display panel DP1 and a right eye of the user. In the display device accommodating case 2120, the left-eye lens LLNS may be disposed between the second display panel DP2 and a left eye of the user.
An image output from the first display panel DP1 may be viewed by the right eye of the user through the right-eye lens RLNS. The right-eye lens RLNS may refract light emitted from the first display panel DP1 to face the right eye of the user. The right-eye lens RLNS may perform an optical function for adjusting a viewing distance between the first display panel DP1 and the right eye of the user.
An image output from the second display panel DP2 may be viewed by the left eye of the user through the left-eye lens LLNS. The left-eye lens LLNS may refract light emitted from the second display panel DP2 to face the left eye of the user. The left-eye lens LLNS may perform an optical function for adjusting a viewing distance between the second display panel DP2 and the left eye of the user.
In embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped section. In embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-areas having different optical characteristics. In the above embodiment, each of the first and second display panels DP1 and DP2 may output images corresponding to the sub-areas of the multi-channel lens, and the output images may be viewed by the user while respectively passing through corresponding sub-areas.
In the display panel and the manufacturing method thereof in accordance with the present disclosure influence of a leakage current between adjacent pixels, or adjacent sub-pixels of a pixel, can be reduced or prevented.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0113996 | Aug 2023 | KR | national |
