Patent Grant
11670247
The present application relates to the field of display technology, and particularly, to a display panel, a method for driving the display panel, and a display device.
Organic Light-Emitting Diode (OLED) has certain advantages, such as low power consumption, low cost, self-luminescence, wide viewing angle, and fast response speed, and thus has become one of the current research hotspots in the display field. Different refresh rates are used by electronic products for displaying in different application scenarios, for example, a driving method with a higher refresh rate is used for driving the displaying of dynamic images (such as sports events or game scenes) to ensure the smoothness of display images; and a driving method with a lower refresh rate is used for driving the displaying of slow-motion images or static images to reduce power consumption. However, electronic products using organic self-luminous technology can encounter screen flicker phenomenon when displaying slow-motion images or static images, which affects the visual experience.
In a first aspect, an embodiment of the present disclosure provides a display panel. The display panel includes a light emitting element and at least one pixel circuit. A pixel circuit of the at least one pixel circuit includes a driving transistor and a third transistor. The driving transistor is configured to provide a driving current to the light emitting element. The third transistor is configured to provide an adjusting voltage to the driving transistor and includes a first terminal connected to a voltage adjusting signal input terminal, a second terminal connected to the driving transistor, and a gate connected to a third control signal terminal. The adjusting voltage provided by the third transistor to the driving transistor is configured to adjust a bias state of the driving transistor.
In a second aspect, an embodiment of the present disclosure provides a method for driving a display panel. The display panel includes a light emitting element and a pixel circuit including a driving transistor and a third transistor. The driving transistor is configured to provide a driving current to the light emitting element. The third transistor is configured to provide an adjusting voltage to the driving transistor and includes a first terminal connected to a voltage adjusting signal input terminal, a second terminal connected to the driving transistor, and a gate connected to a third control signal terminal. The adjusting voltage provided by the third transistor to the driving transistor is configured to adjust a bias state of the driving transistor. An operation process of the display panel includes a reset and adjustment phase. The method includes: during the reset and adjustment phase, controlling the third transistor to turn on with a signal of the third control signal terminal, and providing, by the third transistor, the adjusting voltage to the driving transistor.
In a third aspect, an embodiment of the present disclosure further provides a display device including the display panel provided in the first aspect.
In order to more clearly explain technical solutions of embodiments of the present disclosure or the related art, the drawings needed in the description of the embodiments or the related art are briefly described as below. The drawings described below are merely some of the embodiments of the present disclosure. Those skilled in the art can also obtain other drawings based on these drawings.
In order to make the objectives, technical solutions, and advantages of the present disclosure more clearly, the technical solutions of the present disclosure will be further described by embodiments with reference to the accompanying drawings. The described embodiments are some embodiments of the present disclosure, but not all of the embodiments. Other embodiments obtained by those persons skilled in the art based on the embodiments of the present disclosure shall fall within the protection scope of the present disclosure.
The terms used in the embodiments of the present disclosure are merely for the purpose of describing specific embodiment, rather than limiting the present disclosure. The terms “a”, “an”, “the” and “said” in a singular form in the embodiments of the present disclosure and the attached claims are also intended to include plural forms thereof, unless the context indicates its meaning clearly.
The present disclosure provides a display panel, a method for driving the display panel, and a display device. The display panel includes a pixel circuit and a light emitting element. The pixel circuit is electrically connected to the light emitting element to drive the light emitting element to emit light, and thus the display panel displays screen images. When one frame of image is displayed, under control of a light-emission controlling signal, the pixel circuit supplies a driving current to the light emitting element to control the light emitting element to emit light. The beginning of the light emitting period of the light emitting element includes a light brightness rising process, and the brightness rising rate is affected by the bias state of the driving transistor. In the related art, the bias states of the driving transistor in two adjacent frames are significantly different, so the brightness rising rates are significantly different, which in turn leads to flicker in the display images. In the present disclosure, the operation process of driving the display panel includes a period of a data writing frame and a period of a holding frame. A data signal is written to a source of a driving transistor in the period of the data writing phase of the data writing frame, and the driving transistor is controlled to be in a biased state in the light emitting state to generate a driving current. In a reset and adjustment phase of the period of the holding frame, an adjusting voltage is written to a first terminal (source) of the driving transistor to adjust the bias state of the driving transistor. By providing the reset and adjustment phase in the period of the holding frame, the difference between the bias state of the driving transistor in the period of the holding frame and the bias state of the driving transistor in the period of the data writing frame is reduced, and thus the difference between a brightness rising rate of the light emitting element at the beginning of the period of the holding frame and a brightness rising rate of the light emitting element at the beginning of the period of the data writing frame is reduced, thereby reducing the flicker phenomenon of the display images. The present disclosure will be described in detail with specific embodiments below.
As shown in
The structure of the pixel circuit 21 can be referred to the schematic diagram in
As shown in
In an embodiment, a control terminal of the data writing module 211 is electrically connected to a first control signal terminal S1, a first terminal of the data writing module 211 is electrically connected to a data signal input terminal Data, and a second terminal of the data writing module 211 is connected to the source of the driving transistor Mn. A control terminal of the compensation module 213 is electrically connected to a second control signal terminal S2, a first terminal of the compensation module 213 is electrically connected to the source of the driving transistor Mn, and a second terminal of the compensation module 213 is electrically connected to the drain of the driving transistor Mn. The light-emission controlling module 214, the driving transistor Mn, and the light emitting element 31 are connected in series. A control terminal of the light-emission controlling module 214 is electrically connected to a light-emission controlling signal terminal E, and a terminal of the light-emission controlling module 214 is electrically connected to a first power supply terminal PV. A control signal of the reset module 215 is electrically connected to a reset controlling signal terminal Sr, a first terminal of the reset module 215 is electrically connected to a reset signal terminal Ref, and a second terminal of the reset module 215 is electrically connected to the gate of the driving transistor Mn.
In an embodiment, the pixel circuit 21 further includes an anode reset transistor M6 configured to provide a reset signal to an anode (e.g., the reflective anode) of the light emitting element 31. The anode reset transistor M6 includes a first terminal electrically connected to a reset voltage input terminal Ref, a second terminal electrically connected to the anode of the light emitting element 31, and a gate electrically connected to the first control signal terminal S1.
With reference to the timing sequence diagram shown in
In the period Z1 of the data writing frame, the pixel circuit executes a reset phase T1, a data writing phase T2, and a light emitting phase T3. The reset phase T1 is prior to the data writing phase T2. In the reset phase T1, the reset module 215 is turned on to reset the gate of the driving transistor Mn. Specifically, the reset module 215 is turned on under the control of a signal of a reset control signal terminal Sr, and supplies the signal of the reset signal terminal Ref to the gate of the driving transistor Mn to reset the gate of the driving transistor Mn, such that when the display panel executes the period Z1 of the data writing frame, the accurate data voltage can be written to the gate of the driving transistor. During the data writing phase T2, the data writing module 211 and the compensation module 213 are turned on, the data signal is written to the gate of the driving transistor Mn, and the compensation module 213 compensates the threshold voltage of the driving transistor Mn. Specifically, the data writing module 211 is turned on under control of the signal of the first control signal terminal S1 and writes the signal provided by the data signal input terminal Data to the source of the driving transistor Mn, the compensation module 213 is turned on under control of the signal of the second control signal terminal S2 and supplies the voltage of the drain of the driving transistor Mn to the gate of the driving transistor Mn, and the anode reset transistor M6 is turned on under control of the first control signal terminal S1 and then provides the reset signal to the anode of the light emitting element 31. During the light emitting phase T3, the light-emission controlling module 214 is turned on under the control of the light-emission control signal terminal E, and supplies the driving current generated by the driving transistor Mn to the light emitting element 31.
In the period Z2 of the holding frame, the pixel circuit executes a reset and adjustment phase T4 and the light emitting phase T3. During the reset and adjustment phase T4, the data writing module 211 is turned on, the compensation module 213 is turned off, the data writing module 211 writes the adjusting voltage for adjusting the bias state of the driving transistor Mn. Specifically, the data writing module 211 is turned on under the control of the signal of the first control signal terminal S1 and writes the adjusting voltage, which is transmitted through the data signal input terminal Data, to the source of the driving transistor, so as to adjust the bias state of the driving transistor Mn; and the anode reset transistor M6 is turned on under control of the first control signal terminal S1 and then provides the reset signal to the anode of the light emitting element 31. The operating process of the pixel circuit in the light emitting phase T3 of the period Z2 of the holding frame is the same as the operating process in the light emitting phase T3 of the period Z1 of the data writing frame.
The display panel includes data lines electrically connected to the plurality of pixel circuits. The data line is the data signal input terminal. As can be seen from the timing sequence diagram shown in
When the light-emission controlling module 214 is turned off, the light-emission controlling module 214 cannot supply the driving current to the light emitting element 31, and thus the light emitting element 31 does not emit light. When an effective level signal is provided by the light-emission controlling signal terminal E, the light-emission controlling module 214 is turned on and can supply the driving current generated by the driving transistor Mn to the light emitting element 31, and thus the light emitting element 31 emits light. In the beginning of the light emitting phase of the light emitting element 31 includes a brightness rising process, and the brightness rising rate is related to the bias state of the driving transistor Mn.
The period Z1 of the data writing frame includes a phase for resetting the gate of the driving transistor Mn. After a voltage VR of the voltage signal of the reset signal terminal Ref is supplied to the gate of the driving transistor Mn, it begins to affect the bias state of the driving transistor Mn. In the beginning of the data writing phase T2, the voltage of the gate of the driving transistor Mn is VR, and the voltage of the source of the driving transistor Mn is maintained at its voltage in the previous light emitting phase, which is close to the voltage VP provided by the first power supply terminal PV. Therefore, the gate-source voltage of the driving transistor Mn is Vgs1=VR−VP.
Continuing to refer to the timing sequence diagram shown in
In an embodiment, as shown in
Continuing to refer to
Continuing to refer to
In an embodiment, the first light-emission controlling module 214a includes a first light-emission controlling transistor M3, and the second light-emission controlling module 214b includes a second light-emission controlling transistor M4. A gate of the first light-emission controlling transistor M3 and a gate of the second light-emission controlling transistor M4 are both connected to the light-emission controlling terminal E. A first terminal of the first light-emission controlling transistor M3 is connected to the first power supply terminal PV, and a second terminal of the first light-emission controlling transistor M3 is connected to the source of the driving transistor Mn. A first terminal of the second light-emission controlling transistor M4 is connected to the drain of the driving transistor Mn, and a second terminal of the second light-emission controlling transistor M4 is connected to the light emitting element 31.
In an embodiment, as shown in
In an embodiment, during the reset phase T1, the voltage of the gate of the driving transistor Mn is Vg1, a voltage of the source of the driving transistor Mn is Vs1, and a gate-source voltage of the of the driving transistor Mn is Vgs, which is equal to Vg1−Vs1. In an embodiment, Vg1 is close to the reset signal VR that is written to the gate of the driving transistor Mn by the reset module 215, the voltage of the source of the driving transistor Mn is maintained at its voltage in the previous phase during the light emitting, and Vs1 is close to the voltage VP provided by the first power supply terminal PV.
In the reset and adjustment phase T4, the gate-source voltage of the driving transistor Mn is Vg2, the voltage of the source of the driving transistor Mn is Vs2, and a gate-source voltage of the driving transistor Mn is Vgs1, which is equal to Vg2−Vs2. Specifically, the gate of the driving transistor Mn is maintained at its potential in the light emitting phase, and thus Vg2 is close to VData+Vth, and Vs2 is close to the adjusting voltage VJ that is written to the source of the driving transistor.
For the driving transistor Mn, when its gate-source voltage is smaller than Vth, the driving transistor is turned on, and the greater the gate-source voltage, the greater the bias degree of the driving transistor. In the present embodiment, −3V≤Vg1−Vs1−(Vg2−Vs2)≤3V, that is, −3V≤Vgs−Vgs1≤3V. In this way, the difference between the bias state of the driving transistor Mn in the period Z2 of the holding frame and the bias state of the driving transistor Mn in the period Z1 of the data writing frame is small, which can decrease the brightness rising rate of the light emitting element 31 in the period Z2 of the holding frame. Therefore, the brightness rising rate of the light emitting element in the period Z2 of the holding frame is consistent with the brightness rising rate of the light emitting element in the period Z1 of the data writing frame, thereby reducing the flicker problem of the display images.
In some embodiments, −2V≤Vg1−Vs1−(Vg2−Vs2)≤2V. In some other embodiments, −1V≤Vg1−Vs1−(Vg2−Vs2)≤1V. With such configuration, the difference between the bias state of the driving transistor Mn in the period Z1 of the holding frame and the bias state of the driving transistor Mn in the period Z2 of the data writing frame can be further reduced, and the flicker problem of the display images can be further improved, thereby improving the display effects.
In the embodiments of the present disclosure, the adjusting voltage is written to the source of the driving transistor Mn in the reset and adjustment phase T4 so as to adjust the bias state of the driving transistor Mn, and the following factors can be taken into account for the value of the adjusting voltage VJ.
In an embodiment, at the beginning of the reset and adjustment phase T4, the voltage of the source of the driving transistor Mn is Vs1, and VJ>Vs1. The adjusting voltage VJ is written to the source of the driving transistor Mn during the reset and adjustment phase T4, the voltage of the source of the driving transistor Mn is increased during the reset and adjustment phase T4, and thus the bias state of the driving transistor Mn is increased, and the difference between the bias state of the driving transistor Mn in the period Z1 of the holding frame and the bias state of the driving transistor Mn in the period Z2 of the data writing frame. In an embodiment, 0V<VJ−Vs1≤3.5V. In an embodiment, 1V<VJ−Vs1≤3.5V. It is set that VJ>Vs1 so as to adjust the bias state of the driving transistor in the period of the holding frame, and it is not necessary to set VJ at a too large value while reducing the flicker problem of the display images, to reduce power consumption.
In an embodiment, the period Z2 of the holding frame does not include the reset phase T1 or the data writing phase T2. At the beginning of the reset and adjustment phase T4, the source of the driving transistor Mn is maintained at its voltage in the previous light emitting phase. Vs1 is close to the power supply voltage VP that is written to the source of the driving transistor Mn through turning on the first power supply terminal PV by the light-emission controlling module 214 in the previous light emitting phase. In the embodiments of the present disclosure, VJ≥VP, so as to adjust the bias state of the driving transistor in the holding frame, which is equivalent to writing the adjusting voltage VJ to the source of the driving transistor Mn in the reset and adjustment phase T4 to simulate the bias state of the driving transistor Mn in the period Z1 of the data writing frame, and thus the brightness rising rate of the light emitting element 31 in the period Z2 of the holding frame is reduced, such that the brightness rising rate of the light emitting element in the period Z2 of the holding frame is consistent with the brightness rising rate of the light emitting element in the period Z1 of the data writing frame, thereby reducing the flicker problem of the display images.
In an embodiment, VP=4.6V, and 6V≤VJ≤8V. VJ is set to be greater than VP, and VJ is not too large to avoid excessive power consumption.
In an embodiment, a maximum value of the voltage of a preset data signal is VD, VJ≥VD. The voltage of the preset data signal is the preset data voltage needed for different display gray scales of the display panel. The lower the display gray scale, the greater the voltage of the corresponding preset data signal. VJ≥VD, that is, VJ is not smaller than a preset dark-state voltage of the display panel. According to the description in the above embodiments, after resetting the gate of the driving transistor Mn in the period Z1 of the data writing frame, the gate-source voltage of the driving transistor Mn is Vgs1, which is equal to VR−VP. During the reset and adjustment phase T4, the gate-source voltage of the driving transistor Mn is Vgs2, which is equal to VData+Vth−VJ. VJ≥VD≥VData, so VData−VJ≤0, and Vgs2≤Vth, and only when VData=VD, Vgs2=Vth. That is, when the holding frame displays a non-dark-state, it can be ensured that the driving transistor is in the bias state after the adjusting voltage is written to the driving transistor during the reset and adjustment phase, and thus the bias of the driving transistor is adjusted. In the embodiments of the present disclosure, the power supply voltage VP provided by the first power supply terminal PV is smaller than VD. In an embodiment, VP=4.6V, and VD=5.5V. Based on the description of the principle in the above embodiment of
In an embodiment, the voltage of the reset signal is VR, and VJ≥VR. The voltage VR of the reset signal in the display panel is relatively small. By setting VJ not smaller than VR, it can be avoided that the voltage written to the source of the driving transistor is too small for the bias adjustment when adjusting the bias state of the driving transistor in the period of the holding frame.
In an embodiment, the adjusting voltage VJ is a constant voltage.
Corresponding to the pixel circuit structure in the embodiments shown in
Corresponding to the pixel circuit structure of the embodiments shown in
In an embodiment, in the reset and adjustment phase T4, the voltage of the gate of the driving transistor Mn is Vg2, the voltage of the source of the driving transistor Mn is Vs2, and the gate-source voltage of the driving transistor Mn is set to Vgs2=Vg2−Vs2≤−2V. The value of Vgs2 is set within a certain range so as to ensure the driving transistor Mn is in the bias state, and the bias state in this phase is close to the bias state of the driving transistor Mn during the period Z1 of the data writing frame. Therefore, the brightness rising rate of the light emitting element in the period Z2 of the holding frame is consistent with the brightness rising rate of the light emitting element in the period Z1 of the data writing frame, thereby reducing the flicker problem of the display images.
In an embodiment,
When the display panel is operating, the driving circuit 22 supplies a data signal to the data writing module 211 through the data line 23 during the data writing phase T2, and the driving circuit 22 supplies an adjusting voltage VJ to the data writing module 211 though the data line 23 during the reset and adjustment phase T4. In an embodiment, the display panel executes at least one period Z2 of the holding frame after the period Z1 of the data writing frame. One data line 23 is electrically connected to multiple pixel circuits in one pixel column. In an embodiment, in the period Z1 of the data writing frame, after the multiple pixel circuits connected to one data line 23 all finish the data writing phase T2, the driving circuit 22 controls to supply the adjusting voltage VJ to the data line 23 so as to achieve that in the period Z2 of the holding frame, the pixel circuits adjacent to this data line 23 executes the reset and adjustment phase T4. In an embodiment, the adjusting voltage VJ is not smaller than the maximum value of the preset data voltage the driving circuit 22 can output. In the present embodiment, the driving circuit supplies different voltage signals to the data line in different operation phases, such that the data writing module is reused in the data writing phase and the reset and adjustment phase, and the bias state of the driving transistor in the period of the holding frame is adjusted to reduce the flicker problem of the display panel while there is no need to change the structure of the pixel circuit and the connection between the pixel circuit and the driving circuit.
In another embodiment,
As shown in
The operating process of the display panel includes a period Z1 of the data writing frame and a period Z2 of the holding frame.
In the period Z1 of the data writing frame, the pixel circuit executes a reset phase T1, a data writing phase T2, and a light emitting phase T3. During the reset phase T1, the reset module 215 is turned on under the control of a signal of a reset control signal terminal Sr, and supplies the signal of the reset signal terminal Ref to the gate of the driving transistor Mn to reset the gate of the driving transistor Mn. During the data writing phase T2, under control of the signal of the second control signal terminal S2, the second transistor M1b writes the data signal to the source of the driving transistor Mn, and at the same time, under control of the signal of the second control signal terminal S2, the compensation transistor M2 is turned on and supplies the voltage of the drain of the driving transistor Mn to the gate of the driving transistor Mn. In this phase, the data signal is written to the gate of the driving transistor Mn, and the threshold voltage of the driving transistor Mn is compensated. During the light emitting phase T3, the light-emission controlling module 214 is turned on under the control of the light-emission control signal terminal E, and thus supplies the driving current generated by the driving transistor Mn to the light emitting element 31.
In the period Z2 of the holding frame, the pixel circuit executes a reset and adjustment phase T4 and the light emitting phase T3. During the reset and adjustment phase T4, under control of the signal of the third control signal terminal S3, the third transistor M1c writes the adjusting voltage VJ to the source of the driving transistor Mn. During the light emitting phase T3, the light-emission controlling module 214 is turned on under the control of the signal of the light-emission control signal terminal E, and the gate of the driving transistor Mn is maintained at the potential in the previous light emitting phase, and the driving transistor Mn is turned on udder the control of the voltage of the gate and generates the driving current. In this phase, the driving current generated by the driving transistor Mn is supplied to the light emitting element 31. In the period Z2 of the holding frame, the compensation module 213 and the reset module 215 are turned off.
In this embodiment, the reset and adjustment phase T4 is within the period Z2 of the holding frame. During the reset and adjustment phase T4, the adjusting voltage VJ is written to the source of the driving transistor Mn to simulate the bias state of the driving transistor Mn in the period Z1 of the data writing frame, and thus the brightness rising rate of the light emitting element 31 in the period Z2 of the holding frame is reduced, such that the brightness rising rate of the light emitting element in the period Z2 of the holding frame is consistent with the brightness rising rate of the light emitting element in the period Z1 of the data writing frame, thereby reducing the flicker problem of the display images. The data writing module 211 includes a second transistor M1b and a third transistor M1c. The second transistor M1b is a data writing transistor, and the third transistor M1c is a voltage adjusting transistor. The input terminal (the first terminal) of the second transistor and the input terminal (the first terminal) of the third transistor are connected to different signal input terminals, and the two transistors are controlled by different control signal terminals, which can control the data writing phase and the reset and adjustment phase independently. The gate of the data writing transistor and the gate of the compensation transistor are connected to a same control signal terminal (the second control signal terminal), which can ensure that the compensation transistor and the data writing transistor can be turned on simultaneously during the data writing phase, without additional control of the compensation transistor.
In an embodiment, adjusting signal input terminals of at least two third transistors are connected to a same adjust signal line.
In another embodiment, the voltage adjusting signal input terminals corresponding to the third transistors of multiple pixel circuits in the same pixel row are connected to a same voltage adjusting signal line, which is not illustrated in the drawing.
Since the voltage adjusting signal input terminals corresponding to the third transistors of multiple pixel circuits are connected to the same voltage adjusting signal line, the number of the voltage adjusting signal lines in the display panel is reduced, the space for wiring in the display panel can be saved. In an embodiment, the input terminals of all voltage adjusting signal line in the display panel is connected to a same output port of the driving circuit (driving chip), and thus, the number of ports is reduced, and at the same time, the voltage dropping of the voltage adjusting signal line during the transmission of the voltage adjusting signal is also reduced to reduce the power consumption.
In another embodiment,
As shown in
The operating process of the display panel includes a period Z1 of the data writing frame and a period Z2 of the holding frame. Specifically:
In the period Z1 of the data writing frame, the pixel circuit executes a reset phase T1, a data writing phase T2, and a light emitting phase T3. During the reset phase T1, the reset module 215 is turned on under the control of the signal of the reset control signal terminal Sr, and supplies the signal of the reset signal terminal Ref to the gate of the driving transistor Mn to reset the gate of the driving transistor Mn. During the data writing phase T2, under control of the signal of the second control signal terminal S2, the second transistor M1b writes the data signal to the source of the driving transistor Mn, and at the same time, under control of the signal of the second control signal terminal S2, the compensation transistor M2 is turned on and supplies the voltage of the drain of the driving transistor Mn to the gate of the driving transistor Mn. In this phase, the data signal is written to the gate of the driving transistor Mn, and the threshold voltage of the driving transistor Mn is compensated. During the light emitting phase T3, the light-emission controlling module 214 is turned on under the control of the light-emission control signal terminal E, and supplies the driving current generated by the driving transistor Mn to the light emitting element 31.
In the period Z2 of the holding frame, the pixel circuit executes a reset and adjustment phase T4 and the light emitting phase T3. During the reset and adjustment phase T4, under control of the signal of the fourth control signal terminal S4, the fourth transistor M1d writes the adjusting voltage VJ to the source of the driving transistor Mn. During the light emitting phase T3, the light-emission controlling module 214 is turned on under the control of the signal of the light-emission control signal terminal E, and the gate of the driving transistor Mn is maintained at the potential in the previous light emitting phase, and the driving transistor Mn is turned on udder the control of the voltage of the gate and generates the driving current. In this phase, the driving current generated by the driving transistor Mn is supplied to the light emitting element 31. In the period Z2 of the holding frame, the compensation module 213 and the reset module 215 are turned off.
In this embodiment, the reset and adjustment phase T4 is provided in the period Z2 of the holding frame. During the reset and adjustment phase T4, the adjusting voltage VJ is written to the source of the driving transistor Mn to simulate the bias state of the driving transistor Mn in the period Z1 of the data writing frame, and thus the brightness rising rate of the light emitting element 31 in the period Z2 of the holding frame is reduced, such that the brightness rising rate of the light emitting element in the period Z2 of the holding frame is consistent with the brightness rising rate of the light emitting element in the period Z1 of the data writing frame, thereby reducing the flicker problem of the display images. The data writing module 211 includes a second transistor M1b and a fourth transistor M1d. The second transistor M1b is the data writing transistor, and the fourth transistor M1d is the voltage adjusting transistor. The input terminal (the first terminal) of the second transistor and the input terminal (the first terminal) of the fourth transistor are connected to the same signal input terminal, and the two transistors are controlled by different control signal terminals, and the gate of the data writing transistor and the gate of the compensation transistor are connected to the same control signal terminal (the second control signal terminal), such that the compensation transistor and the data writing transistor can be turned on simultaneously during the data writing phase, and the data writing module supplies the voltage signal to the source of the driving transistor through different transistors in the period of the data writing frame and the period of the holding frame respectively.
In an embodiment, the operation mode of the display panel includes a first mode, the first mode includes repeated first cycles, and the first cycle includes one period of the data writing frame and at least one period of the holding frame.
In an embodiment, when the display panel is driven to operate in the first mode, the display panel displays slow-motion video images. In another embodiment, when the display panel is driven to operate in the first mode, the display panel displays a static image.
In an embodiment, the operation mode of the display panel further includes a second mode. The second mode includes repeated periods Z1 of the data writing frame. An image refreshing rate of the display panel in the second mode is greater than an image refreshing rate of the display panel in the first mode. Compared with the first mode, the second mode is a high-frequency operation mode, and the first mode is a low-frequency operation mode. In application, the first mode is used in a scene where the display panel is driven to display dynamic images. The display panel provided by the embodiment of the present disclosure includes different operation modes, and the display panel is switched between the first mode and the second mode according to different requirements for the refreshing rate of the display images of the display panel. For example, the display panel is driven to display static images or a slow-motion video when operating in the first mode, which can reduce the power consumption of the display panel; and the display panel is driven to display dynamic images when operating in the second mode, which can improve the smoothness of the display images.
In an embodiment, the driving transistor Mn is a P-type transistor. In an embodiment, material of an active layer of the driving transistor Mn includes silicon. In an embodiment, the driving transistor Mn is a low-temperature polysilicon transistor. The low-temperature polysilicon transistor has high electron mobility and stability. In an embodiment, the transistor in each module of the pixel circuit is P-type transistor. The pixel circuit including the low-temperature polysilicon transistor can occupy a smaller area while satisfying the driving performance of the light emitting element.
In an embodiment of the present disclosure, the pixel circuit further includes a light emitting element resetting module electrically connected to the light emitting element and configured to reset an electrode of the light emitting element. A first terminal of the light emitting element resetting module is electrically connected to a reset signal terminal, and a second terminal of the light emitting element resetting module is connected to the light emitting element.
In an embodiment, a control terminal of the light emitting element resetting module and the control terminal of the reset module are connected to a same control terminal, and the light emitting element resetting module resets the electrode of the light emitting element during the reset phase.
In another embodiment, the control terminal of the light emitting element resetting module and the control terminal of the compensation module are connected to a same control terminal, and the light emitting element resetting module reset the electrode of the light emitting element during the data writing phase.
An embodiment of the present disclosure also provides a method for driving a display panel, which can be applied to drive the display panel provided in the embodiments of the present disclosure. The display panel includes a pixel circuit and a light emitting element. The structure of the pixel circuit, reference can be made to the
In the period Z1 of the data writing frame, the pixel circuit 21 executes a data writing phase T2 and a light emitting phase T3. During the data writing phase T2, the data writing module 211 and the compensation module 213 are turned on, and the data writing module 211 writes a data signal.
In the period Z2 of the holding frame, the pixel circuit 21 executes a reset and adjustment phase T4 and the light emitting phase T3. During the reset and adjustment phase T4, the data writing module 211 is turned on, the compensation module 213 is turned off, and the data writing module 211 writes the adjusting voltage for adjusting a bias state of the driving transistor Mn.
According to the method provided in the embodiments of the present disclosure, when the display panel is operating in the period of the holding frame, the pixel circuit is controlled to execute the reset and adjustment phase so as to adjust the bias state of the driving transistor in the period of the holding frame. Therefore, the difference between the bias state of the driving transistor in the period of the holding frame and the bias state of the driving transistor in the period of the data writing frame is reduced, and thus the difference between the brightness rising rate of the light emitting element at the beginning of the period of the holding frame and the brightness rising rate of the light emitting element at the beginning of the period of the data writing frame is reduced, thereby improving the flicker phenomenon of the display image.
In an embodiment, as shown in
An embodiment of the present disclosure provides a method that can drive the display panel in the embodiment of
During the reset phase T1, the first scanning signal controls the reset module 215 to be turned on, the second scanning signal controls the data writing module 211 to be turned off, the third scanning signal controls the compensation module 213 to be turned off, and the fourth scanning signal controls the light-emission controlling module 214 to be turned off. In this phase, the gate of the driving transistor Mn is reset by the reset module 215.
During the data writing phase T2, the first scanning signal controls the reset module 215 to be turned off, the second scanning signal controls the data writing module 211 to be turned on, the third scanning signal controls the compensation module 213 to be turned on, and the fourth scanning signal controls the light-emission controlling module 214 to be turned off. In this phase, the data signal is written to the gate of the driving transistor Mn, and the shift of the threshold voltage of the driving transistor Mn is compensated.
During the light emitting phase T3, the first scanning signal controls the reset module 215 to be turned off, the second scanning signal controls the data writing module 211 to be turned off, the third scanning signal controls the compensation module 213 to be turned off, and the fourth scanning signal controls the light-emission controlling module 214 to be turned on. In this phase, the driving transistor Mn generates the driving transistor, and the light-emission controlling module 214 controls to provision of the driving current to the light emitting element.
The driving method further includes sequentially executing, by the pixel circuit, the reset and adjustment phase T4 and the light emitting phase T3 in period of the holding frame.
During the reset and adjustment phase T4, the first scanning signal controls the reset module 215 to be turned off, the second scanning signal controls the data writing module 211 to be turned on, the third scanning signal controls the compensation module 213 to be turned off, and the fourth scanning signal controls the light-emission controlling module 214 to be turned off. In this phase, the data writing module 211 is turned on and writes the adjusting voltage to the source of the driving transistor Mn so as to adjust the bias state of the driving transistor Mn.
During the light emitting phase, the first scanning signal controls the reset module 215 to be turned off, the second scanning signal controls the data writing module 211 to be turned off, the third scanning signal controls the compensation module 213 to be turned off, and the fourth scanning signal controls the light-emission controlling module 214 to be turned on. In this phase, the gate of the driving transistor Mn is maintained at the potential in the previous light emitting phase, and the driving transistor Mn generates the driving current under the control of this potential, and the light-emission controlling module 214 controls to provision of the driving current to the light emitting element.
In the method provided by the present embodiment, the data writing module is controlled to write the voltage signal to the source of the driving transistor during the data writing phase, and the data writing module is controlled to write the adjusting voltage to the source of the driving transistor during the reset and adjustment phase so as to adjust the bias state of the driving transistor. That is, the data writing module is reused in the data writing phase and the reset and adjustment phase. The flicker problem of the display images can be improved just by changing the driving timing sequence of the pixel circuit without changing the structure of the pixel circuit.
An embodiment of the present disclosure provides another method that can drive the display panel provided in the embodiments of
Corresponding to the pixel circuit shown in
Corresponding to the pixel circuit shown in
The method for driving the display panel provided in the embodiment of the present disclosure includes the following steps.
In the period Z1 of the data writing frame, the pixel circuit sequentially executes the reset phase T1, the data writing phase T2, and the light emitting phase T3.
During the reset phase T1, the first scanning signal controls the reset module 215 to be turned on, the second scanning signal controls the first sub-module (the second transistor M1b) to be turned off, the third control signal controls the second sub-module (the third transistor M1c in the embodiment of
During the data writing phase T2, the first scanning signal controls the reset module 215 to be turned off, the second scanning signal controls the first sub-module and the compensation module 213 to be turned on, the third scanning signal controls the second sub-module to be turned off, and the fourth scanning signal controls the light-emission controlling module 214 to be turned off. In this phase, the first sub-module and the compensation module are turned on at the same time, the data signal is written to the gate of the driving transistor Mn, and the shift of the threshold voltage of the driving transistor Mn is compensated.
During the light emitting phase T3 of the period Z1 of the data writing frame, the first scanning signal controls the reset module 215 to be turned off, the second scanning signal controls the first sub-module and the compensation module 213 to be turned off, the third scanning signal controls the second sub-module to be turned off, and the fourth scanning signal controls the light-emission controlling module 214 to be turned on. In this phase, the driving transistor Mn generates the driving current, and the light-emission controlling module 214 controls the provision of the driving current to the light emitting element.
In the period Z2 of the holding frame, the pixel circuit sequentially executes the reset and adjustment phase T4 and the light emitting phase T3.
During the reset and adjustment phase T4, the first scanning signal controls the reset module 215 to be turned off, the second scanning signal controls the first sub-module and the compensation module 213 to be turned off, the third scanning signal controls the second sub-module to be turned on, and the fourth scanning signal controls the light-emission controlling module 214 to be turned off. In this phase, the second sub-module is turned on, the adjusting voltage is written to the source of the driving transistor Mn so as to adjust the bias state of the driving transistor Mn.
During the light emitting phase T3 of the period Z2 of the holding frame, the first scanning signal controls the reset module 215 to be turned off, the second scanning signal controls the first sub-module and the compensation module 213 to be turned off, the third scanning signal controls the second sub-module to be turned off, and the fourth scanning signal controls the light-emission controlling module 214 to be turned on. In this phase, the gate of the driving transistor Mn is maintained at the potential in the previous light emitting phase, the driving transistor Mn generates the driving current under control of this potential, and the light-emission controlling module 214 controls the provision of the driving current to the light emitting element.
In the method for driving the display panel provided in this embodiment, the first sub-module in the data writing module is controlled to write the voltage signal to the source of the driving transistor in the data writing phase, the second sub-module in the data writing module is controlled to write the adjusting voltage to the source of the driving transistor in the reset and adjustment phase so as to adjust the bias state of the driving transistor. The first sub-module and the second sub-module are controlled by different control signals, and thus the compensation module and the first sub-module can be controlled by a common control signal, such that the compensation module and the first sub-module can be turned on simultaneously and turned off simultaneously.
When applied in a display panel, the first scanning signal, the second scanning signal, the third scanning signal, and the fourth scanning signal are respectively provided by different shift driving circuits. When the method provided by the embodiment of the present disclosure is applied, the display panel is provided with four groups of different shift driving circuits. Each shift driving circuit includes a plurality of cascaded shift registers.
An embodiment of the present disclosure further provides a display device.
The above are merely some embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent substitutions or improvements made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
It should be noted that the above embodiments are only used to illustrate, but not to limit the technical solutions of the present disclosure. Although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art shall understand that they can modify the technical solutions described in the foregoing embodiments, or equivalently replace some or all of the technical features. The modifications or replacements shall not direct the essence of the corresponding technical solutions away from the scope of the technical solutions of the embodiments of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110226111.4 | Mar 2021 | CN | national |
The present application is a continuation of U.S. patent application Ser. No. 17/332,222, filed on May 27, 2021, which claims priority to Chinese Patent Application No. 202110226111.4, filed on, Mar. 1, 2021. All of the afore-mentioned patent applications are hereby incorporated by reference in their entireties
| Number | Name | Date | Kind |
|---|---|---|---|
| 20070063932 | Nathan | Mar 2007 | A1 |
| 20140062843 | Yang | Mar 2014 | A1 |
| 20190096330 | Kim | Mar 2019 | A1 |
| 20210118368 | In | Apr 2021 | A1 |
| 20210383743 | Yuan | Dec 2021 | A1 |
| Number | Date | Country |
|---|---|---|
| 112102778 | Dec 2020 | CN |
| 112133242 | Dec 2020 | CN |
| Entry |
|---|
| First Office Action, Chinese Patent Application No. 202110226111.4, dated Nov. 9, 2021, 26 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20220277696 A1 | Sep 2022 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17332222 | May 2021 | US |
| Child | 17567487 | US |
