Patent Application
20240234524
This application claims priority to China Patent Application No. 202211311534.7, filed Oct. 25, 2022, the disclosure of which is incorporated herein by reference in its entirety.
The present application relates to a technical field of displays, and particularly to a display panel and a method of manufacturing the same, and a display device including the display panel.
Micro light-emitting diodes (micro-LEDs) and mini-LEDs are emerging display technologies that use current-driven displays.
With ever-increasing requirements of better image quality for high-definition display panels, it is inevitable now to improve resolution and display image quality. However, in current mini/micro LED displays, both sides of semiconductor layers of thin-film transistors are generally conductorized to form source and drain contact regions. Source and drain electrodes are connected to the semiconductor layers through the source and drain contact regions, and channel regions are located between the source and drain contact regions. Lengths of the channel regions are generally determined by lengths of gate electrodes, making them difficult to achieve thin-film transistors with short channels, which is not conducive to reduction of the size of the thin-film transistors, rendering achievement of high resolution difficult.
An object of the embodiments of the present application is to provide a display panel and a method of manufacturing the same, and a display device that are capable of achieving thin-film transistors with short channels, reducing size of the thin-film transistors, and fulfilling high-resolution display panels.
In order to achieve the above-mentioned object, an embodiment of the present application provides a display panel including a thin-film transistor, the thin-film transistor including an active portion, and a source electrode and a drain electrode that are contact-connected to the active portion.
The display panel further includes a substrate, a first metal layer disposed on the substrate and including the source electrode and the drain electrode, and an active layer disposed on a side of the first metal layer away from the substrate and including the active portion, the active portion including a conductor sublayer and a semiconductor sublayer.
The conductor sublayer includes a first conductor subsection and a second conductor subsection spaced apart from each other, and the semiconductor sublayer is connected at least between the first conductor subsection and the second conductor subsection.
In some embodiments of the present application, the active portion includes a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region. The conductor sublayer further includes an isolation groove located between the first conductor subsection and the second conductor subsection in the channel region, and the semiconductor sublayer is filled at least in the isolation groove.
In some embodiments of the present application, the first conductor subsection extends to the source contact region, the second conductor subsection extends to the drain contact region, the source electrode is electrically connected to the first conductor subsection located in the source contact region, and the drain electrode is electrically connected to the second conductor subsection in the drain contact region.
In some embodiments of the present application, a length of the isolation groove in a first direction is less than a distance between the source contact region and the drain contact region, and the first direction is a direction in which the source contact region points to the drain contact region.
In some embodiments of the present application, the length of the isolation groove in the first direction is less than or equal to 3 microns.
In some embodiments of the present application, the thin-film transistor further includes a gate electrode, and the display panel further includes a second metal layer disposed on a side of the active layer away from the first metal layer. The second metal layer includes the gate electrode located on a side of the active portion away from the substrate, and an orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the gate electrode on the substrate.
In some embodiments of the present application, the display panel further includes an interlayer dielectric layer and a third metal layer disposed on a side of the active layer away from the substrate. The interlayer dielectric layer covers the active layer and the second metal layer, and the third metal layer is located on a side of the interlayer dielectric layer away from the second metal layer.
The third metal layer includes a first electrode member, and the first electrode member is electrically connected to the thin-film transistor through the interlayer dielectric layer.
In some embodiments of the present application, the orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the first electrode member on the substrate.
In some embodiments of the present application, the display panel further includes a moisture-oxygen barrier layer disposed between the interlayer dielectric layer and the third metal layer. The orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the moisture-oxygen barrier layer on the substrate.
In some embodiments of the present application, the first metal layer further includes a light shielding portion located between the active portion and the substrate.
In some embodiments of the present application, one end of the source electrode is connected to the active portion, the other end is connected to the light shielding portion, and the source electrode is made of a material same as a material of the light shielding portion.
According to the above object of the present application, an embodiment of the present application further provides a method of manufacturing a display panel, the display panel including a thin-film transistor, the thin-film transistor including an active portion, and a source electrode and a drain electrode that are contact-connected to the active portion.
The method of manufacturing the display panel including:
According to the above object of the present application, an embodiment of the present application further provides a display device. The display device includes a display panel and a device body which are combined into one body.
The display panel includes a thin-film transistor, the thin-film transistor including an active portion, and a source electrode and a drain electrode that are contact-connected to the active portion.
The display panel further includes a substrate, a first metal layer disposed on the substrate and including the source electrode and the drain electrode, and an active layer disposed on a side of the first metal layer away from the substrate and including the active portion, the active portion including a conductor sublayer and a semiconductor sublayer.
The conductor sublayer includes a first conductor subsection and a second conductor subsection spaced apart from each other, and the semiconductor sublayer is connected at least between the first conductor subsection and the second conductor subsection.
In some embodiments of the present application, the active portion includes a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region. The conductor sublayer further includes an isolation groove located between the first conductor subsection and the second conductor subsection in the channel region, and the semiconductor sublayer is filled at least in the isolation groove.
In some embodiments of the present application, the first conductor subsection extends to the source contact region, the second conductor subsection extends to the drain contact region, the source electrode is electrically connected to the first conductor subsection located in the source contact region, and the drain electrode is electrically connected to the second conductor subsection in the drain contact region.
In some embodiments of the present application, a length of the isolation groove in a first direction is less than a distance between the source contact region and the drain contact region, and the first direction is a direction in which the source contact region points to the drain contact region.
In some embodiments of the present application, the length of the isolation groove in the first direction is less than or equal to 3 microns.
In some embodiments of the present application, the thin-film transistor further includes a gate electrode, and the display panel further includes a second metal layer disposed on a side of the active layer away from the first metal layer. The second metal layer includes the gate electrode located on a side of the active portion away from the substrate, and an orthographic projection of the isolation groove on the substrate is located within a coverage range of an orthographic projection of the gate electrode on the substrate.
In some embodiments of the present application, the first metal layer further includes a light shielding portion located between the active portion and the substrate.
In some embodiments of the present application, one end of the source electrode is connected to the active portion, the other end is connected to the light shielding portion, and the source electrode is made of a material same as a material of the light shielding portion.
The present application has advantageous effects as follows: compared with prior art, the active portion in the embodiment of the present application includes the conductor sublayer and the semiconductor sublayer, and the conductor sublayer includes the first conductor subsection and the second conductor subsection spaced apart from each other. The semiconductor sublayer is connected at least between the first conductor subsection and the second conductor subsection, so that the active portion can form a channel in a spaced region between the first conductor subsection and the second conductor subsection, and a smaller-sized channel can be obtained by precise photolithography on the conductor sublayer, thus obtaining the thin-film transistor with an ultra-short channel, thereby effectively improving current passing capacity and mobility of the thin-film transistor, reducing the size of the thin-film transistor, and increasing resolution of the display panel.
The technical solutions and other advantageous effects of the present application will be apparent through the detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.
The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of this application.
The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the application. Furthermore, this application may repeat reference numerals and/or reference letters in different instances for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments-and/or arrangements discussed. Moreover, this application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
An embodiment of the present application provides a display panel. Referring to
Further, the display panel further includes a substrate 10, a first metal layer 20, and an active layer. The first metal layer 20 is disposed on the substrate 10 and includes a source electrode 21 and a drain electrode 22. The active layer is disposed on a side of the first metal layer 20 away from the substrate 10, and includes an active portion 30, and the active portion 30 includes a conductor sublayer 31 and a semiconductor sublayer 32.
Specifically, the conductor sublayer 31 includes a first conductor subsection 311 and a second conductor subsection 312 spaced apart from each other, and the semiconductor sublayer 32 is connected at least between the first conductor subsection 311 and the second conductor subsection 312.
In practical application processes, the active portion 30 in the embodiment of the present application includes the conductor sublayer 31 and the semiconductor sublayer 32, and the conductor sublayer 31 includes the first conductor subsection 311 and the second conductor subsection 312 spaced apart from each other. The semiconductor sublayer 32 is connected at least between the first conductor subsection 311 and the second conductor subsection 312, so that the active portion 30 can form a channel in a spaced region between the first conductor subsection 311 and the second conductor subsection 312, and a smaller-sized channel can be obtained by precise photolithography on the conductor sublayer 31, thus obtaining the thin-film transistor T with an ultra-short channel, thereby effectively improving current passing capacity and mobility of the thin-film transistor T, reducing a size of the thin-film transistor T, and increasing resolution of the display panel.
Specifically, please continue to refer to
It should be noted that the display panel provided in the embodiment of the present application includes a plurality of thin-film transistors T, and each of the thin-film transistors T includes the active portion 30, the source electrode 21, the drain electrode 22, and the gate electrode 41.
Further, the first metal layer 20 includes a plurality of the source electrodes 21 and a plurality of the drain electrodes 22, the active layer includes a plurality of the active portions 30, and the second metal layer 40 includes a plurality of the gate electrodes 41. Specifically, in a same thin-film transistor T, the source electrode 21 and the drain electrode 22 are located between a corresponding one of the active portions 30 and the substrate 10, and two sides of the active portion 30 are contact-connected to the source electrode 21 and the drain electrode 22 through via holes extending through the insulating layer 51, respectively, and the gate electrode 41 is located on a side of the gate insulating layer 52 away from the active portion 30.
In the embodiment of the present application, the first metal layer 20 further includes a plurality of light shielding portions 23, and each of the light shielding portions 23 is disposed corresponding to an active portion 30 to prevent ambient light or reflected light from irradiating the active portion 30, thus adversely affecting electrical stability of the active portion 30. In addition, in a same thin-film transistor T, one end of the source electrode 21 is connected to the active portion 30, and the other end is connected to the light shielding portion 23.
Preferably, the source electrode 21 is made of a material same as a material of the light shielding portion 23, and the source electrode 21 and the light shielding portion 23 are integrally formed. Furthermore, compared with prior art, in the embodiment of the present application, the source electrode 21 and the drain electrode 22 are arranged in a same layer as the light shielding portion 23, so that they can be formed through a same photomask, which saves process steps and reduces process cost.
Further, since the source electrode 21, the drain electrode 22, and the light shielding portion 23 are all incorporated into the first metal layer 20 in the embodiment of the present application, number of insulating film layers covering the source and drain electrodes will be reduced compared with the prior art, so that number of the film layers that block moisture and oxygen above the active portion 30 is reduced. However, in the embodiment of the present application, the gate electrode 41 is disposed above the active portion 30, which can effectively block moisture and oxygen, and improve the stability of the thin-film transistor T. That is, the embodiment of the present application can ensure the stability of the thin-film transistor T and improve the yield of the display panel on the basis of simplifying a process flow and reducing the process cost. In addition, compared with the prior art, a conventional gate electrode is located under a semiconductor layer, so that a film layer under the semiconductor layer is uneven, causing the semiconductor layer to form slope-like structures, which is prone to the risk of disconnection. In contrast, in the embodiment of the present application, the gate electrode 41 is disposed above the active portion 30, preventing the slope-like structure of the active portion 30, reducing the risk of disconnection of the active portion 30, and further improving the yield of the thin-film transistor T.
As noted above, in the embodiment of the present application, each active portion 30 has a source contact region 301, a drain contact region 302, and a channel region 303 located between the source contact region 301 and the drain contact region 302. Furthermore, the source electrode 21 is electrically connected to part of the active portion 30 located in the source contact region 301, and the drain electrode 22 is electrically connected to part of the active portion 30 located in the drain contact region 302.
Each of the active portions 30 includes the conductor sublayer 31 and the semiconductor sublayer 32. Specifically, the conductor sublayer 31 includes the first conductor subsection 311 and the second conductor subsection 312 spaced apart from each other, and an isolation groove 313 located between the first conductor subsection 311 and the second conductor subsection 312, and the isolation groove 313 is situated in the channel region 303. At least the first conductor subsection 311 extends into the source contact region 301, and at least the second conductor subsection 312 extends into the drain contact region 302. Specifically, the source electrode 21 is contact-connected to the first conductor subsection 311 located in the source contact region 301 through a source electrode contact hole extending through the insulating layer 51. The drain electrode 22 is contact-connected to the second conductor subsection 312 in the drain contact region 302 through a drain contact hole extending through the insulating layer 51.
It can be understood that, in the embodiment of the present application, the semiconductor sublayer 32 is connected at least between the first conductor subsection 311 and the second conductor subsection 312. Further, The semiconductor sublayer 32 is filled at least in the isolation groove 313 to form a channel in the channel region 303. In addition, the semiconductor sublayer 32 may also be filled in the isolation groove 313 and extend partially to the source contact region 301 and/or partially to the drain contact region 302. Specifically, the semiconductor sublayer 32 may include a first subportion filled in the isolation groove 313 and a second subportion extending outside the isolation groove 313, and the second subportion is located on a side of the conductor sublayer 31 away from the substrate 10.
Optionally, the conductor sublayer 31 may be made of a material including at least one of indium tin oxide (ITO) or indium zinc oxide (IZO), whereas the semiconductor sublayer 32 may be made of a material including at least one of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO).
Optionally, a thickness of the conductor sublayer 31 may be greater than or equal to 750 angstroms and less than or equal to 1000 angstroms, and a thickness of those semiconductor sublayer 32 may be about 300 angstroms.
Specifically, a length of the isolation groove 313 in a first direction is less than a distance between the source contact region 301 and the drain contact region 302, and the first direction is a direction in which the source contact region 301 points to the drain contact region 302. In this embodiment of the present application, the precise photolithography process on the conductor sublayer 31 can be used to precisely control the length of the isolation groove 313, and the isolation groove 313 with a shorter length can be obtained, that is, the thin-film transistor T with a short channel can be obtained. In the embodiment of the present application, the length of the isolation groove 313 in the first direction is less than or equal to 3 micrometers. Compared with the prior art, a length of a current channel is generally determined by a length of a gate, so that the length of the current channel is generally about 8 microns. In contrast, in the embodiments of the present application, a channel length of the thin-film transistor T can be effectively reduced, so that the current passing capability and mobility of the thin-film transistor T can be improved. In addition, the embodiments of the present application can also reduce the size of the thin-film transistor T by reducing the channel length of the thin-film transistor T, thereby saving more space to increase the number of thin-film transistors T, and improving the resolution of the display panel.
Further, in the embodiment of the present application, the source electrode 21 is contact-connected to the first conductor subsection 311, the drain electrode 22 is contact-connected to the second conductor subsection 312, and the semiconductor sublayer 32 is only configured to form the channel. Therefore, in this embodiment of the present application, the semiconductor sublayer 32 does not need to be subjected to conducting treatment. In the prior art, during a conductorization process of a semiconductor layer, requirements for equipment stability and process time control are extremely strict, and a slight fluctuation will greatly affect electrical properties of devices. For this reason, the embodiments of the present application can effectively simplify the process flow, reduce the difficulty of the process, and improve the yield of the display panel.
In the embodiment of the present application, an orthographic projection of the isolation groove 313 on the substrate 10 is within a coverage range of an orthographic projection of the gate electrode 41 on the substrate 10. In this manner, the gate electrode 41 effectively prevents ions in a film layer above the gate electrode 41 and ions in the environment from diffusing into the active portion 30, thereby reducing the influence of ion diffusion on the semiconductor sublayer 32 located in the channel region 303, thus improving the reliability and stability of the thin-film transistor T.
In addition, the third metal layer 60 includes a first electrode member 61, and the first electrode member 61 is electrically connected to the thin-film transistor T through a via hole extending through the interlayer dielectric layer 53. Specifically, the first electrode member 61 is contact-connected to the second conductive subsection 312 through a via hole extending through the interlayer dielectric layer 53, so as to realize the electrical connection between the first electrode member 61 and the drain electrode 22 for signal transmission.
Specifically, referring to
It should be noted that when the display panel provided by the embodiment of the present application is an organic light-emitting diode (OLED) display panel, the first electrode member 61 may be an anode in the OLED display panel, and the second electrode member 62 may be located in a non-display area of the OLED display panel and connected to a surface cathode of the OLED display panel, so as to obtain an OLED display panel with a short channel. Further, in this embodiment of the present application, positions of the source electrode 21 and the drain electrode 22 may be interchanged, which is not limited herein.
In another embodiment of the present application, referring to
Optionally, an orthographic projection of the thin-film transistor T on the substrate 10 is located within the coverage range of the orthographic projection of the first electrode member 61 on the substrate 10.
In another embodiment of the present application, referring to
Optionally, the orthographic projection of the thin-film transistor T on the substrate 10 is located within the coverage area of the orthographic projection of the water-oxygen barrier layer 80 on the substrate 10, and the first electrode member 61 passes through the moisture-oxygen barrier layer 80 and the interlayer dielectric layer 53 to be contact-connected to the second conductor subsection 312 in order to achieve electrical connection between the first electrode member 61 and the drain electrode 22. Further, the moisture-oxygen barrier layer 80 can also cover an entire display area of the display panel.
Optionally, the moisture-oxygen barrier layer 80 is made of a material including aluminum oxide (AlOx) or titanium oxide (TiOx). A thickness of the moisture-oxygen barrier layer 80 is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms.
Accordingly, the active portion 30 in the embodiment of the present application includes the conductor sublayer 31 and the semiconductor sublayer 32, and the conductor sublayer 31 includes the first conductor subsection 311 and the second conductor subsection 312 spaced apart from each other. The semiconductor sublayer 32 is connected at least between the first conductor subsection 311 and the second conductor subsection 312, so that the active portion 30 can form a channel in a spaced region between the first conductor subsection 311 and the second conductor subsection 312, and a smaller-sized channel can be obtained by precise photolithography on the conductor sublayer 31, thus obtaining the thin-film transistor T with an ultra-short channel, thereby effectively improving current passing capacity and mobility of the thin-film transistor T, reducing the size of the thin-film transistor T, and increasing the resolution of the display panel.
Furthermore, referring to
A method of manufacturing the display panel includes:
Step S10: providing a substrate 10.
The substrate 70 may be a glass substrate.
Step S20: forming a first metal layer 20 on the substrate 10, and the first metal layer 20 includes a source electrode 21 and a drain electrode 22.
A first metal material layer is deposited on the substrate 10 by a physical vapor sputtering method, and the first metal material layer is patterned to obtain the first metal layer 20, wherein the first metal layer 20 includes a plurality of the source electrodes 21, a plurality of the drain electrodes 22, and a plurality of light shielding portions 23. Specifically, each of the source electrodes 21 is correspondingly connected to one of the light shielding portions 23, and the source electrode 21 and the corresponding light shielding portion 23 are integrally formed.
Optionally, the first metal material layer may be made of a material including at least one of molybdenum (Mo) and copper (Cu).
Step S30: forming an active layer on a side of the first metal layer 20 away from the substrate 10. The active layer includes an active portion 30 including a conductor sublayer 31 and a semiconductor sublayer 32. The conductor sublayer 31 includes a first conductor subsection 311 and a second conductor subsection 312 spaced apart from each other, and the semiconductor sublayer 32 is connected at least between the first conductor subsection 311 and the second conductor subsection 312.
A chemical vapor deposition method is performed to form an insulating material layer on the substrate 10, and the insulating material layer is subjected to high temperature annealing treatment for 2 to 3 hours, and the temperature may be 300° C. to 400° C. to obtain an insulating layer 51.
Optionally, the insulating material layer may be made of a material including at least one of silicon nitride (SiNx) and silicon oxide (SiOx).
Next, the insulating layer 51 is patterned to obtain a source contact hole 511 and a drain contact hole 512.
A metal oxide layer is deposited on the insulating layer 51, and the metal oxide layer is patterned to obtain a plurality of the conductor sublayers 31. In addition, the conductor sublayers 31 are located above and arranged in a one-to-one correspondence with the source electrodes 21 and the drain electrodes 22. The conductor sublayers 31 are contact-connected to the source electrode 21 and the drain electrode 22 through the source contact hole 511 and the drain contact hole 512, respectively.
Specifically, in the process of patterning the metal oxide layer, in addition to forming the conductor sublayers 31, the first conductor subsection 311 and the second conductor subsection 312 spaced apart from each other are formed in each of the conductor sublayers 31, and an isolation groove 313 is formed between the first conductor subsection 311 and the second conductor subsection 312. Specifically, the first conductor subsection 311 is contact-connected to the source electrode 21 through the source contact hole 511, and the second conductor subsection 312 is contact-connected to the drain electrode 22 through the drain contact hole 512.
Optionally, the metal oxide layer is made of a material including at least one of ITO or IZO. A thickness of the conductor sublayer 31 is greater than or equal to 750 angstroms and less than or equal to 1000 angstroms.
Then, an oxide semiconductor layer is formed on the conductor sublayer 31 and the insulating layer 51 by a physical vapor sputtering method, and the oxide semiconductor layer is subjected to patterning to obtain a plurality of the semiconductor sublayers 32. Each semiconductor sublayer 32 is located on one conductor sublayer 31 correspondingly. Specifically, each semiconductor sublayer 32 is filled in the isolation groove 313 of a corresponding one of the conductor sublayers 31, and partially extends to the side of the conductor sublayer 31 away from the substrate 10. In addition, one conductor sublayer 31 and one semiconductor sublayer 32 together form one active portion 30.
Optionally, a material of the oxide semiconductor layer includes at least one of IGZO, IGTO, or IGZTO, and a thickness of the semiconductor sublayer 32 may be about 300 angstroms.
Next, a gate insulating material layer and a second metal material layer are sequentially deposited on the semiconductor sublayer 32 and the insulating layer 51. First, the second metal material layer is patterned to obtain a second metal layer 40, and the second metal layer 40 includes a plurality of gate electrodes 41. Each of the gate electrodes 41 is correspondingly located over one active portion 30, and then the gate insulating material layer is patterned by a self-alignment process of the gate electrode 41 to obtain a gate insulating layer 52 located between the gate electrode 41 and the active portion 30.
An interlayer dielectric layer 53 is formed on the gate electrode 41 and the insulating layer 51 by chemical vapor deposition. The interlayer dielectric layer 53 covers the active portion 30, the gate electrode 41, and the insulating layer 51. Then, the interlayer dielectric layer 53 is subjected to an opening process to expose part of an upper surface of the drain electrode 22.
Optionally, the interlayer dielectric layer 53 is made of a material including at least one of SiOx or SiNx.
A physical vapor deposition method is used to form an electrode material layer on the interlayer dielectric layer 53, and the electrode material layer is patterned to obtain a third metal layer 60. The third metal layer 60 includes a first electrode member 61 being contact-connected to the drain electrode 22 through a via hole extending through the interlayer dielectric layer 53 to achieve electrical signal transmission, as shown in
Optionally, a material of the electrode material layer may include at least one of IZO or ITO.
In another embodiment of the present application, referring to
Further, in another embodiment of the present application, referring to
Next, a photolithography process may be used to form holes in the moisture-oxygen barrier layer 80 and the interlayer dielectric layer 53 to expose an upper surface of the second conductor subsection 312.
Then, an electrode material layer is formed on the interlayer dielectric layer 53 by a physical vapor deposition method, and the electrode material layer is patterned to obtain a third metal layer 60. The third metal layer 60 includes a first electrode member 61 being contact-connected to the second conductor subsection 312 through a via hole extending through the moisture-oxygen barrier layer 80 and the interlayer dielectric layer 53 to achieve the electrical connection between the first electrode member 61 and the drain electrode 22 for electrical signal transmission, as shown in
Optionally, the moisture-oxygen barrier layer 80 is made of a material including aluminum oxide (AlOx) or titanium oxide (TiOx). A thickness of the moisture-oxygen barrier layer 80 is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms.
Accordingly, the active portion 30 in the embodiment of the present application includes the conductor sublayer 31 and the semiconductor sublayer 32, and the conductor sublayer 31 includes the first conductor subsection 311 and the second conductor subsection 312 spaced apart from each other. The semiconductor sublayer 32 is connected at least between the first conductor subsection 311 and the second conductor subsection 312, so that the active portion 30 can form a channel in a spaced region between the first conductor subsection 311 and the second conductor subsection 312, and a smaller-sized channel can be obtained by precise photolithography on the conductor sublayer 31, thus obtaining the thin-film transistor T with an ultra-short channel, thereby effectively improving current passing capacity and mobility of the thin-film transistor T, reducing the size of the thin-film transistor T, and increasing the resolution of the display panel.
Furthermore, an embodiment of the present application further provides a display device. The display device includes the display panel described in the above-mentioned embodiments, or includes a display panel and a device main body manufactured by the method of manufacturing the display panel described in the above embodiments in which the display panel and the device main body are combined into one body.
In the embodiment of the present application, the display panel may be the display panel described in the above-mentioned embodiments, and the device main body may include a frame body, a driving module, and the like.
The display device may be a display terminal, such as a mobile phone, a tablet, a television, etc., which is not limited here.
In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in an embodiment, reference may be made to related descriptions of other embodiments.
The display panel and the method of manufacturing the same provided by the embodiments of the present application are described in detail above. The principles and implementations of the present application are described with specific examples herein. The descriptions of the above embodiments are only used to help understand the technical solutions and kernel ideas of the present disclosure; those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, whereas these modifications or substitutions do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211311534.7 | Oct 2022 | CN | national |
| Number | Date | Country | |
|---|---|---|---|
| 20240136415 A1 | Apr 2024 | US |
