Patent Application
20240334750
This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2023-0043375, filed on Apr. 3, 2023, the contents of which are hereby incorporated by reference in its entirety.
The present disclosure relates to a display panel and a method of manufacturing the same. More particularly, the present disclosure relates to a display panel having improved brightness and a method of manufacturing the display panel.
Electronic devices providing a user with images, such as smartphones, tablet computers, digital cameras, notebook computers, navigation units, and televisions, include a display device to display the images.
The display device includes red, green, and blue pixels, and a light emitting layer having a color corresponding to a color of each pixel is disposed in each pixel. In general, the light emitting layer is formed through a deposition process using a shadow mask, but defects, such as a sagging of the mask, are likely to occur. In recent, a process of entirely and commonly forming the light emitting layer and other organic layers over each pixel using an open mask is being developed.
However, when the organic layer is commonly formed, a lateral leakage current occurs in the organic layer commonly formed over the pixels adjacent to each other, and a color mixture and a brightness defect occur.
The present disclosure may provide a display panel capable of preventing a driving voltage from excessively increasing, a color mixture from occurring, and a brightness from being lowered.
The present disclosure may provide a method of manufacturing the display panel.
Embodiments of the inventive concept provide a display panel including a base layer including a first pixel area and a second pixel area adjacent to the first pixel area, a pixel definition layer disposed on the base layer and including a pixel opening defined therethrough to correspond to the first pixel area and the second pixel area, respectively, a first electrode of which at least a portion is disposed in the pixel opening. The pixel definition layer includes a first slant portion, a second slant portion spaced apart from the first slant portion, a first convex portion disposed between the first slant portion and the second slant portion and adjacent to the first slant portion, and a first flat portion disposed between the first slant portion and the second slant portion and adjacent to the second slant portion. The first slant portion includes a first slant surface inclined at a first angle with respect to an upper surface of the base layer, the second slant portion includes a second slant surface inclined at a second angle with respect to the upper surface of the base layer, and the first angle is greater than the second angle.
The pixel definition layer includes a first closed portion disposed along a periphery of the first pixel area, including the first convex portion, and surrounding a portion of the first pixel area and a first opened portion that does not include the first convex portion and includes a portion of the first pixel area, which is not surrounded by the first closed portion, and a circumference length of the first opened portion is about 20% or more and about 30% or less of a sum of the circumference length of the first opened portion and a circumference length of the first closed portion.
The pixel definition layer further includes a spacer disposed on the first flat portion.
The first angle is equal to or greater than about 70° and equal to or less than about 130°, and the second angle is equal to or greater than about 10° and equal to or less than about 40°.
A step difference between the first convex portion and the first flat portion is equal to or greater than about 0.2 micrometers and equal to or less than about 1.0 micrometers, and the first convex portion has a width equal to or greater than about 2.5 micrometers and equal to or less than about 4.5 micrometers.
The base layer further includes a third pixel area adjacent to the second pixel area, the first pixel area displays a first light, the second pixel area displays a second light having a wavelength different from the first light, and the third pixel area displays a third light having a wavelength different from the first light and the second light.
The display panel further includes an organic layer disposed on the first electrode and the pixel definition layer and including a light emitting layer and a second electrode disposed on the organic layer.
The organic layer includes an organic first slant portion disposed on the first slant surface, an organic first convex portion disposed on the first convex portion, an organic first flat portion disposed on the first flat portion, and an organic second slant portion disposed on the second slant surface. The second electrode includes an electrode first slant portion disposed on the organic first slant portion, an electrode first convex portion disposed on the organic first convex portion, an electrode first flat portion disposed on the organic first flat portion, and an electrode second slant portion disposed on the organic second slant portion.
The organic first slant portion has a thickness of about 10% or more and about 30% or less of a thickness of the organic first flat portion or the organic second slant portion.
The organic layer further includes a hole control layer disposed on the first electrode and the pixel definition layer, the light emitting layer disposed on the hole control layer, and an electron control layer disposed between the light emitting layer and the second electrode.
The first slant portion is disposed adjacent to the first pixel area, and the second slant portion is disposed adjacent to the second pixel area.
The pixel definition layer further includes a third slant portion facing the first slant portion and including a third slant surface inclined at a third angle with respect to the upper surface of the base layer and a fourth slant portion spaced apart from the second slant portion with the first slant portion and the third slant portion interposed therebetween and including a fourth slant surface inclined at a fourth angle with respect to the upper surface of the base layer, and the third angle is greater than the fourth angle.
The third angle is equal to or greater than about 70° and equal to or less than about 130°, and the fourth angle is equal to or greater than about 10° and equal to or less than about 40°.
The pixel definition layer further includes a second convex portion disposed between the third slant portion and the fourth slant portion and adjacent to the third slant portion, and a separation distance between the first convex portion and the second convex portion is equal to or greater than about 4 micrometers and equal to or less than about 6 micrometers.
The pixel definition layer further includes a third slant portion facing the first slant portion and including a third slant surface inclined at a third angle with respect to the upper surface of the base layer and a fourth slant portion spaced apart from the second slant portion with the first slant portion and the third slant portion interposed therebetween and including a fourth slant surface inclined at a fourth angle with respect to the upper surface of the base layer, and each of the third and fourth angles is greater than the second angle.
Embodiments of the inventive concept provide a display panel including a base layer including a first pixel area and a second pixel area adjacent to the first pixel area, a pixel definition layer disposed on the base layer and including a pixel opening defined therethrough to correspond to the first pixel area and the second pixel area, respectively, a first electrode of which at least a portion is disposed in the pixel opening, an organic layer disposed on the first electrode and the pixel definition layer and including a light emitting layer, and a second electrode disposed on the organic layer. The pixel definition layer includes a first slant portion including a first slant surface inclined at a first angle with respect to an upper surface of the base layer and a second slant portion spaced apart from the first slant portion and including a second slant surface inclined at a second angle with respect to the upper surface of the base layer. The first angle is greater than the second angle, the organic layer includes an organic first slant portion disposed on the first slant surface and an organic second slant portion disposed on the second slant surface, the second electrode includes an electrode first slant portion disposed on the organic first slant portion and an electrode second slant portion disposed on the organic second slant portion, and the organic first slant portion has a thickness smaller than a thickness of the organic second slant portion.
The pixel definition layer further includes a first convex portion disposed between the first slant portion and the second slant portion and adjacent to the first slant portion and a first flat portion disposed between the first slant portion and the second slant portion and adjacent to the second slant portion, the organic layer further includes an organic first convex portion disposed on the first convex portion and an organic first flat portion disposed on the first flat portion, and the second electrode further includes an electrode first convex portion disposed on the organic first convex portion and an electrode first flat portion disposed on the organic first flat portion.
The organic first slant portion has a thickness of about 10% or more and about 30% or less of a thickness of the organic first flat portion or the organic second slant portion.
Embodiments of the inventive concept provide a method of manufacturing a display panel. The manufacturing method of the display panel includes preparing a base layer, forming a first electrode on the base layer, providing a negative photoresist that covers the first electrode to form a preliminary pixel definition layer, providing a mask including a first portion in which a first exposure non-transmissive portion, a first exposure transmissive portion, and a first exposure semi-transmissive portion are arranged in one direction and a second portion in which a second exposure transmissive portion, a second exposure semi-transmissive portion, and a second exposure non-transmissive portion are arranged in the one direction on the preliminary pixel definition layer, exposing the preliminary pixel definition layer to a light through the mask, and removing portions of the preliminary pixel definition layer except portions cured by the exposure process to form the pixel definition layer. The pixel definition layer includes a first slant portion formed corresponding to the first exposure non-transmissive portion of the mask, a first convex portion formed corresponding to the first exposure transmissive portion of the mask, a first flat portion formed corresponding to the first exposure semi-transmissive portion of the mask, a spacer formed corresponding to the second exposure transmissive portion of the mask, and a second slant portion formed corresponding to the second exposure semi-transmissive portion of the mask, the first slant portion includes a first slant surface inclined at a first angle with respect to an upper surface of the base layer, the second slant portion is spaced apart from the first slant portion and includes a second slant surface inclined at a second angle with respect to the upper surface of the base layer, the first convex portion is disposed between the first slant portion and the second slant portion and disposed adjacent to the first slant portion, the first flat portion is disposed between the first slant portion and the second slant portion and disposed adjacent to the second slant portion, and the first angle is greater than the second angle.
The first angle is equal to or greater than about 70° and equal to or less than about 130°, and the second angle is equal to or greater than about 10° and equal to or less than about 40°.
According to the display panel of the present disclosure, the angle formed between the slant surface of the portion of the pixel definition layer and the base layer increases, and thus, a portion of the organic layer and a portion of the second electrode, which are to be deposited, have a relatively thinner thickness. Accordingly, a lateral leakage current is prevented.
According to the method of manufacturing the display panel of the present disclosure, the pixel definition layer is formed using the mask in which the arrangement of an exposure transmissive portion, an exposure semi-transmissive portion, and an exposure non-transmissive portion in one part of mask is different from that of the other part of the mask. Accordingly, the manufacturing process becomes simplified, and productivity and yield are improved compared with a conventional manufacturing method.
The above and other advantages of the present disclosure will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
Hereinafter, embodiments of the present disclosure will be described with reference to accompanying drawings.
In the present disclosure, it will be understood that when an element (or area, layer, or portion) is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present.
Like numerals refer to like elements throughout. In the drawings, the thickness, ratio, and dimension of components are exaggerated for effective description of the technical content. As used herein, the term “and/or” may include any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. As used herein, the singular forms, “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another elements or features as shown in the figures.
It will be further understood that the terms “include”, “including”, “comprise”, and “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and groups thereof.
Meanwhile, in the present disclosure, when an element is referred to as being “directly connected” to another element, there are no intervening elements present between a layer, film region, or substrate and another layer, film, region, or substrate. For example, the term “directly connected” may mean that two layers or two members are disposed without employing additional adhesive therebetween.
Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Hereinafter, a display device according to an embodiment of the present disclosure will be described with reference to accompanying drawings.
Referring to
The electronic device ED may display the image IM through a display surface DS, which is substantially parallel to each of a first direction DR1 and a second direction DR2, toward a third direction DR3. The display surface DS through which the image IM is displayed may correspond to a front surface of the electronic device ED and a front surface of a window WM. Hereinafter, the display surface and the front surface of the electronic device ED and the front surface of the window WM will be assigned with the same reference numeral. The image IM may include a still image as well as a video.
In the present embodiment, front (or upper) and rear (or lower) surfaces of each member of the electronic device ED may be defined with respect to a direction in which the image IM is displayed. The front and rear surfaces may be opposite to each other in the third direction DR3, and a normal line direction of each of the front and rear surfaces may be substantially parallel to the third direction DR3. A separation distance in the third direction DR3 between the front surface and the rear surface may correspond to a thickness or a height in the third direction DR3 of the electronic device ED. Meanwhile, directions indicated by the first, second, and third directions DR1, DR2, and DR3 may be relative to each other and may be changed to other directions. In the following descriptions, the expression “when viewed in a plane” may mean a state of being viewed in the plane defined by the first direction DR1 and the second direction DR2.
The electronic device ED may sense a user input applied thereto from the outside. The user input may include various types of external inputs, such as a part of the user's body, light, heat, and pressure. In addition, the electronic device ED may sense the user input applied to a side or rear surface of the electronic device ED depending on its structure and should not be limited to a specific embodiment.
As shown in
The window WM may include an optically transparent material. The window WM may include an insulating panel. As an example, the window WM may include a glass, plastic, or combination thereof.
As described above, the front surface DS of the window WM may define the front surface of the electronic device ED.
The window WM may include a transmissive area and a bezel area. The transmissive area may be an optically transparent area. For example, the transmissive area may have a transmittance of about 90% or more with respect to a visible light.
The bezel area may have a light transmittance relatively lower than that of the transmissive area. The bezel area may define a shape of the transmissive area. The bezel area may be defined adjacent to the transmissive area and may surround the transmissive area. The bezel area may have a predetermined color. The bezel area may overlap a non-display area DP-NDA of a display panel DP described later. The bezel area may cover the non-display area DP-NDA of the display panel DP to prevent the non-display area DP-NDA from being viewed from the outside, however, this is merely an example. According to an embodiment, the bezel area may be omitted from the window WM.
The display module DM may include at least the display panel DP.
The display panel DP may include a display area DP-DA and the non-display area DP-NDA, which respectively correspond to a display area DA (refer to
The driving chip DIC may include driving elements to drive pixels of the display panel DP, e.g., a data driving circuit.
The external case EDC may accommodate the display module DM and may be coupled with the window WM. The external case EDC may protect components accommodated therein, such as the display module DM.
Referring to
The display surface DS may include a display area DA and a non-display area NDA around the display area DA. The display area DA may display the image IM, and the non-display area NDA may not display the image IM. The non-display area NDA may surround the display area DA, however, it should not be limited thereto or thereby, and the shape of the display area DA and the shape of the non-display area NDA may be changed.
According to the electronic device ED-1, the display surface DS may further include a signal transmission area TA. The signal transmission area TA may be a part of the display area DA or a part of the non-display area NDA. As shown in
Different from the electronic device ED-1 shown in
The electronic device ED-1 may include a folding area FA and a plurality of non-folding areas NFA1 and NFA2. The non-folding areas NFA1 and NFA2 may include a first non-folding area NFA1 and a second non-folding area NFA2. The folding area FA may be disposed between the first non-folding area NFA1 and the second non-folding area NFA2 on the second direction DR2.
As shown in
According to an embodiment, the electronic device ED-1 may be outwardly folded (outer-folding) such that the display surface DS is exposed to the outside. According to an embodiment, the electronic device ED-1 may be configured to repeat the unfolding operation and the in-folding operation or to repeat the unfolding operation and the out-folding operation, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the electronic device ED-1 may be selectively operated in any one of the unfolding operation, the in-folding operation, and the out-folding operation.
As shown in
Meanwhile,
As shown in
The display device DD may generate an image IM and may sense an external input. The display device DD may include a window WM and a display module DM. The window WM may provide a front surface of the electronic device ED-1. Details of the display module DM and the window WM described with reference to
According to the electronic device ED-1, a display panel DP may further include a signal transmission area DP-TA. The signal transmission area DP-TA may be an opening or may be an area having a lower resolution than that of a display area DP-DA. Consequently, the signal transmission area DP-TA may have a transmittance higher than the display area DP-DA and a non-display area DP-NDA. The signal transmission area DP-TA of the display panel DP may correspond to the signal transmission area TA (refer to
The external case EDC may accommodate the display module DM, the control module EM, the power supply module PSM, and the electronic module ELM. The external case EDC may include two cases EDC1 and EDC2 separated from each other, however, it should not be limited thereto or thereby. Although not shown in figure, the electronic device ED-1 may further include a hinge structure to connect the two cases EDC1 and EDC2. The external case EDC may be coupled with the window WM. The external case EDC may protect the display module DM, the control module EM, the power supply module PSM, and the electronic module ELM, which are accommodated in the external case EDC.
The electronic module ELM may be an electronic part that outputs or receives an optical signal. The electronic module ELM may transmit or receive the optical signal through a portion of the electronic device ED-1 corresponding to the signal transmission area TA (refer to
The electronic module ELM may be disposed under the display device DD. The electronic module ELM may be disposed to correspond to the signal transmission area TA (refer to
The power supply module PM may supply a power source necessary for an overall operation of the electronic device ED-1. The power supply module PM may include a well-known battery module.
The control module EM may include at least a main controller 10. The control module EM may include the main controller 10, a wireless communication module 20, an image input module 30, an audio input module 40, an audio output module 50, a memory 60, and an external interface module 70. The modules may be mounted on a circuit board to be electrically connected to each other or may be electrically connected to each other through a flexible circuit board. The control module EM may be electrically connected to the power supply module PSM.
The main controller 10 may control an overall operation of the electronic devices ED and ED-1. As an example, the main controller 10 may activate or deactivate the display device DD in response to the user input. The main controller 10 may control other modules, such as the image input module 30, the audio input module 40, the audio output module 50, or the like, in response to the user input. The main controller 10 may include at least one microprocessor.
The wireless communication module 20 may transmit/receive a wireless signal to/from other terminals using a Bluetooth or WiFi link. The wireless communication module 20 may transmit/receive a voice signal using a general communication line. The wireless communication module 20 may include a transmission circuit 22 that modulates a signal to be transmitted and transmits the modulated signal and a reception circuit 24 that demodulates the signal applied thereto.
The image input module 30 may process an image signal and may convert the image signal into image data that may be displayed through the display device DD. The audio input module 40 may receive an external sound signal through a microphone in a record mode or a voice recognition mode and may convert the external sound signal to electrical voice data. The audio output module 50 may convert sound data provided thereto from the wireless communication module 20 or sound data stored in the memory 60 and may output the converted sound data to the outside.
The external interface module 70 may serve as an interface between the main controller 10 and external devices, such as an external charger, a wired/wireless data port, a card socket (e.g., a memory card and a SIM/UIM card), etc.
Referring to
The display panel DP may be a light-emitting type display panel, however, it should not be particularly limited. For instance, the display panel DP may be an organic light emitting display panel or an inorganic light emitting display panel. A light emitting layer of the organic light emitting display panel may include an organic light emitting material. A light emitting layer of the inorganic light emitting display panel may include a quantum dot, a quantum rod, or a micro-LED. Hereinafter, the organic light emitting display panel will be described as a representative example of the display panel DP.
The input sensing unit ISU may be disposed on the display panel DP. The input sensing unit ISU may sense the external input applied thereto from the outside. The external input may include a variety of inputs provided from the outside of the electronic device ED (refer to
The input sensing unit ISU may be formed on the display panel DP through successive processes. In this case, the input sensing unit ISU may be disposed directly on the display panel DP. In the following descriptions, the expression “A component B is disposed directly on a component A.” means that no intervening elements are present between the component A and the component B. That is, a separate adhesive member may not be disposed between the input sensing unit ISU and the display panel DP.
The display panel DP may include a base layer BS, a circuit element layer DP-CL, a display element layer DP-OLED, and an upper insulating layer TFL. The circuit element layer DP-CL, the display element layer DP-OLED, and the upper insulating layer TFL may be disposed on the base layer BS.
The base layer BS may provide a base surface on which the circuit element layer DP-CL, the display element layer DP-OLED, and the upper insulating layer TFL are stacked. The base layer BS may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable. The base layer BS may be a glass substrate, a metal substrate, or a polymer substrate, however, it should not be limited thereto or thereby. According to an embodiment, the base layer BS may include an inorganic layer, an organic layer, or a composite material layer.
The base layer BS may have a multi-layer structure. For instance, the base layer BS may include a first synthetic resin layer, an inorganic layer having a single-layer or multi-layer structure, and a second synthetic resin layer disposed on the inorganic layer having a single-layer or multi-layer structure. Each of the first and second synthetic resin layers may include a polyimide-based resin, however, it should not be particularly limited.
The circuit element layer DP-CL may be disposed on the base layer BS. The circuit element layer DP-CL may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The conductive layers of the circuit element layer DP-CL may form signal lines or a control circuit of a pixel.
The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include light emitting elements. For example, the display element layer DP-OLED may include organic light emitting elements, however, this is merely an example. According to an embodiment, the display element layer DP-OLED may include inorganic light emitting elements, organic-inorganic light emitting elements, or a liquid crystal layer.
The upper insulating layer TFL may include a capping layer and a thin film encapsulation layer, which are described later. The upper insulating layer TFL may include an organic layer and a plurality of inorganic layers to encapsulate the organic layer.
The upper insulating layer TFL may be disposed on the display element layer DP-OLED and may protect the display element layer DP-OLED from moisture, oxygen, and a foreign substance such as dust particles. The upper insulating layer TFL may encapsulate the display element layer DP-OLED to prevent moisture and oxygen from entering the display element layer DP-OLED. The upper insulating layer TFL may include at least one inorganic layer. The upper insulating layer TFL may include an organic layer and a plurality of inorganic layers encapsulating the organic layer. The upper insulating layer TFL may include a stack structure in which an inorganic layer, an organic layer, and an inorganic layer are sequentially stacked.
The input sensing unit ISU may be disposed on the upper insulating layer TFL. The input sensing unit ISU may be formed on the upper insulating layer TFL through successive processes. The input sensing unit ISU may be disposed directly on the display panel DP. That is, a separate adhesive member may not be disposed between the input sensing unit ISU and the display panel DP. The input sensing unit ISU may be disposed to make contact with an inorganic layer disposed at an uppermost position of the upper insulating layer TFL.
Although not shown in figures, the display module DM may further include a protective member disposed on a lower surface of the display panel DP and an anti-reflective member disposed on an upper surface of the input sensing unit ISU. The anti-reflective member may reduce a reflectance of the display module DM with respect to the external light. The anti-reflective member may be disposed directly on the input sensing unit ISU through successive processes.
The anti-reflective member may include light blocking patterns overlapping a reflective structure disposed thereunder. The anti-reflective member may further include a color filter. The color filter may be disposed between the light blocking patterns and may include a first color filter, a second color filter, and a third color filter, which respectively correspond to a first color pixel, a second color pixel, and a third color pixel.
As shown in
Referring to
The circuit element layer DP-CL may include at least one insulating layer and a circuit element. The circuit element may include a signal line and a pixel driving circuit. The circuit element layer DP-CL may be formed by a coating or depositing process to form an insulating layer, a semiconductor layer, and a conductive layer and a photolithography process to pattern the insulating layer, the semiconductor layer, and the conductive layer.
A buffer layer BFL may include a plurality of inorganic layers stacked one on another. A semiconductor pattern may be disposed on the buffer layer BFL. The buffer layer BFL may increase a coupling force between the base layer BS and the semiconductor pattern.
The semiconductor pattern may include polysilicon, however, it should not be limited thereto or thereby. The semiconductor pattern may include an amorphous silicon or metal oxide.
The semiconductor pattern may have different electrical properties depending on whether it is doped or not or whether it is doped with an N-type dopant or a P-type dopant. The semiconductor pattern may include a first region A1 with low doping concentration and low conductivity and second regions S1 and D1 with relatively high doping concentration and high conductivity. One second region S1 may be disposed at one side of the first region A1, and the other second region S2 may be disposed at the other side of the first region A1. The second regions S1 and D1 may be doped with the N-type dopant or the P-type dopant. A P-type transistor may include a doped region doped with the P-type dopant. The first region A1 may be a non-doped region or may be doped at a concentration lower than the second regions S1 and D1.
The second regions S1 and D1 may substantially serve as an electrode or a signal line. The one second area S1 may correspond to a source of a transistor, and the other second area D1 may correspond to a drain of the transistor.
A first insulating layer 10′ may be disposed on the buffer layer BFL. The first insulating layer 10′ may commonly overlap the pixels arranged in the display area DP-DA and may cover the semiconductor pattern. The first insulating layer 10′ may be an inorganic layer or an organic layer and may have a single-layer or multi-layer structure (e.g., an inorganic layer and an organic layer). The first insulating layer 10′ may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. Not only the first insulating layer 10′ but also each of other insulating layers of the circuit element layer DP-CL described later may be an inorganic layer or an organic layer and may have a single-layer or multi-layer structure.
A gate G1 may be disposed on the first insulating layer 10′. The gate G1 may be a portion of a metal pattern. The gate G1 may overlap the first region A1. The gate G1 may be used as a mask in a process of doping the semiconductor pattern.
A second insulating layer 20′ may be disposed on the first insulating layer 10′ and may cover the gate G1. The second insulating layer 20′ may commonly overlap the pixels. An upper electrode UE may be disposed on the second insulating layer 20′. The upper electrode UE may overlap the gate G1. The upper electrode UE may include a plurality of metal layers. According to an embodiment, the upper electrode UE may be omitted.
A third insulating layer 30′ may be disposed on the second insulating layer 20′ and may cover the upper electrode UE. A first connection electrode CNE1 may be disposed on the third insulating layer 30′. The first connection electrode CNE1 may be connected to the connection signal line SCL via a contact hole CNT-1 defined through the first, second, and third insulating layers 10′, 20′, and 30′.
A fourth insulating layer 40′ may be disposed on the third insulating layer 30′, and a fifth insulating layer 50′ may be disposed on the fourth insulating layer 40′. The fourth insulating layer 40′ may be an organic layer. A second connection electrode CNE2 may be disposed on the fourth insulating layer 40′. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 defined through the fourth insulating layer 40′.
The fifth insulating layer 50′ may be disposed on the fourth insulating layer 40′ and may cover the second connection electrode CNE2. The fifth insulating layer 50′ may be an organic layer.
The light emitting element OLED may be disposed on the fifth insulating layer 50′. A first electrode AE may be disposed on the fifth insulating layer 50′. The first electrode AE may be connected to the second connection electrode CNE2 via a contact hole CNT-3 defined through the fifth insulating layer 50′. A pixel definition layer PDL may be provided with a pixel opening OP defined therethrough. At least a portion of the first electrode AE may be exposed through the pixel opening OP of the pixel definition layer PDL. The pixel definition layer PDL may be an organic layer.
As shown in
A hole control layer HCL may be commonly disposed in the pixel area PXA and the non-pixel area NPXA. The hole control layer HCL may include a hole transport layer and may further include a hole injection layer. A light emitting layer EML may be disposed on the hole control layer HCL.
An electron control layer ECL may be disposed on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and may further include an electron injection layer. The hole control layer HCL, the light emitting layer EML, and the electron control layer ECL may be commonly disposed over the pixels using an open mask, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, at least one of the hole control layer HCL, the light emitting layer EML, and the electron control layer ECL may be formed through a patterning process using a mask. As an example, the light emitting layer EML may be disposed in an area corresponding to the pixel opening OP. That is, the light emitting layer EML may be divided into plural portions respectively disposed in the pixels. The hole control layer HCL, the light emitting layer EML, and the electron control layer ECL may be referred to as an organic layer OL.
A second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may have an integral shape and may be commonly disposed over the pixels.
The upper insulating layer TFL may be disposed on the display element layer DP-OLED and may include a plurality of thin layers. According to an embodiment, the upper insulating layer TFL may include a capping layer CPL and an encapsulation layer TFE disposed on the capping layer CPL. The capping layer CPL may be disposed on the second electrode CE and may be in contact with the second electrode CE. The capping layer CPL may include an organic material.
The encapsulation layer TFE may include a first inorganic encapsulation layer TIOL1, an organic encapsulation layer TOL, and a second inorganic encapsulation layer TIOL2. The first inorganic encapsulation layer TIOL1 and the second inorganic encapsulation layer TIOL2 may protect the display element layer DP-OLED from moisture and oxygen, and the organic encapsulation layer TOL may protect the display element layer DP-OLED from a foreign substance such as dust particles.
Referring to
Each of the light emitting stacks ST1, ST2, and ST3 may include the light emitting layer EML (refer to
The light emitting stacks ST1, ST2, and ST3 shown in
The charge generation layers CGL1 and CGL2 may be disposed between the light emitting stacks ST1, ST2, and ST3 adjacent to each other. Each of the charge generation layers CGL1 and CGL2 may include a p-type charge generation layer or an N-type charge generation layer. The N-type charge generation layer may provide electrons to the stacks adjacent thereto. The N-type charge generation layer may be obtained by doping a base material with an n-dopant. The P-type charge generation layer may provide holes to the stacks adjacent thereto. A buffer layer may be further disposed between the N-type charge generation layer and the P-type charge generation layer.
When a voltage is applied, the charge generation layers CGL1 and CGL2 may form a complex through an oxidation-reduction reaction, and thus may generate charges (electrons and holes). In addition, the charge generation layers CGL1 and CGL2 may provide the generated charges to each of the light emitting stacks ST1, ST2, and ST3 adjacent thereto. The charge generation layers CGL1 and CGL2 may double the efficiency of current generated in the light emitting stacks ST1, ST2, and ST3 and may adjust a balance of the charges between the light emitting stacks ST1, ST2, and ST3 adjacent to each other.
Referring to
Meanwhile, each of the pixel areas PXA-B, PXA-R, and PXA-G may be distinguished from other pixel areas by the pixel definition layer PDL (refer to
As shown in
The pixel areas PXA-B, PXA-R, and PXA-G may have different sizes from each other depending on wavelengths of the lights emitted therefrom. As an example, as shown in
Each of the pixel areas PXA-B, PXA-R, and PXA-G may have a rectangular shape with rounded corners. First pixel area PXA-B may have the rectangular shape defined by long sides extending in the second direction DR2 and short sides extending in the first direction DR1 and provided with rounded corners. Each of the second pixel area PXA-R and the third pixel area PXA-G may have the rectangular shape defined by long sides extending in the first direction DR1 and short sides extending in the second direction DR2 and provided with rounded corners.
Meanwhile, the first convex portion CVP1 may be defined in the pixel definition layer PDL (refer to
According to the display device, the first convex portion CVP1 may be defined to surround a portion of each pixel area PXA to prevent a lateral leakage current from occurring between the pixels adjacent to each other. Meanwhile, in the present disclosure, the expression “lateral leakage current” indicates a current flowing in a direction that intersects the third direction DR3 rather than a current flowing in the third direction DR3 that corresponds to the stacking direction of the light emitting element, i.e., the direction to which the image is displayed. The lateral leakage current may indicate the current flowing in the direction substantially parallel to a plane defined by the first direction DR1 and the second direction DR2.
Referring to
According to an embodiment, a closed portion CPP may be defined in the pixel definition layer to overlap the non-pixel area NPXA and to surround a portion of each of the pixel areas PXA-B, PXA-R, and PXA-G. The closed portion CPP may include the first convex portion CVP1. The closed portion CPP may surround the portion of each of the pixel areas PXA-B, PXA-R, and PXA-G and may not surround the other portion of each of the pixel areas PXA-B, PXA-R, and PXA-G. The closed portion CPP may include a first closed portion CPP1 surrounding the portion of the first pixel area PXA-B, a second closed portion CPP2 surrounding the portion of the second pixel area PXA-R, and a third closed portion CPP3 surrounding the portion of the third pixel area PXA-G. In the present disclosure, the other portion of each of the pixel areas PXA-B, PXA-R, and PXA-G, which is not surrounded by the closed portion CPP will be referred to as an opened portion OPP.
The opened portion OPP may include a first opened portion OPP1 surrounding a portion of the first pixel area PXA-B, a second opened portion OPP2 surrounding a portion of the second pixel area PXA-R, and a third opened portion OPP3 surrounding a portion of the third pixel area PXA-G. The ratio of a length of the opened portion OPP to a total length including the length of the opened portion OPP and a length of the closed portion CPP in a specific pixel area may be defined as a cathode open ratio (%). As an example, when a sum of a length of the first opened portion OPP1 and a length of the first closed portion CPP1 is five times greater than the length of the first opened portion OPP1 in the first pixel area PXA-B, the cathode open ratio may be about 20%.
Meanwhile, the cathode open ratio (%) may be within a range from about 20% or more to about 30% or less, however, this is merely example. In a case where the cathode open ratio (%) is smaller than about 20%, the driving voltage excessively increases, and thus, an efficiency of the display device may be lowered. In a case where the cathode open ratio (%) is greater than about 30%, the lateral leakage current is excessively generated. As a result, the color mixture may occur between the pixels adjacent to each other, and thus, optical characteristics of the display device may be deteriorated.
According to the display device, the opened portions OPP1, OPP2, and OPP3 may be arranged not to face each other. In a case where the opened portions OPP1, OPP2, and OPP3 are defined to face each other, the lateral leakage current may occur between the pixels, which are adjacent to each other, in which the opened portions OPP1, OPP2, and OPP3 are defined to face each other. However, since the opened portions OPP1, OPP2, and OPP3 are arranged not to face each other in the display device according to the present disclosure, the current may be prevented from flowing in a direction along the plane defined by the first direction DR1 and the second direction DR2 other than an intended direction. Accordingly, the increase of a driving voltage of the display device, the occurrence of the color mixture between the pixels adjacent to each other, and the deterioration of the brightness may be prevented, and thus, a display efficiency of the display device may be improved.
Each of the pixel areas PXA-B, PXA-R, and PXA-G may be spaced apart from the pixel area adjacent thereto by a distance of about 20 micrometers, however, this is merely an example.
Referring to
An upper surface of the base layer BS may be substantially parallel to an upper surface of the first electrode AE.
The pixel definition layer PDL-1 may be disposed on the base layer BS. The pixel definition layer PDL-1 may include a first slant portion AP1, a second slant portion AP2, the first convex portion CVP1, and a first flat portion PP1. The first slant portion AP1 may include a first slant surface AS1 inclined at a first angle AG1 with respect to the upper surface of the base layer BS.
The second slant portion AP2 may be spaced apart from the first slant portion AP1. The second slant portion AP2 may include a second slant surface AS2 inclined at a second angle AG2 with respect to the upper surface of the base layer BS, and the first angle AG1 may be greater than the second angle AG2.
In a case where the angles AG1 and AG2 of the slant surfaces AS1 and AS2 with respect to the upper surface of the base layer BS are greater than about 130°, a damage, such as cracks, may be generated in the upper insulating layer TFL (refer to
The first convex portion CVP1 may be disposed between the first slant portion AP1 and the second slant portion AP2 and may be disposed adjacent to the first slant portion AP1. The first flat portion PP1 may be disposed between the first slant portion AP1 and the second slant portion AP2 and may be disposed adjacent to the second slant portion AP2. The first convex portion CVP1 may be disposed between the first slant portion AP1 and the first flat portion PP1. The first flat portion PP1 may be disposed between the first convex portion CVP1 and the second slant portion AP2. An upper surface of the first flat portion PP1 may be substantially parallel to the upper surface of the base layer BS.
A step difference between the first convex portion CVP1 and the first flat portion PP1 may be equal to or greater than about 0.2 μm and equal to or less than about 1.0 μm. That is, a distance between an upper surface of the first convex portion CVP1 and the upper surface of the base layer BS in the thickness direction may be greater by about 0.2 micrometers or more and about 1.0 micrometers or less compared to a distance between the upper surface of the first flat portion PP1 and the upper surface of the base layer BS. Meanwhile, in the present disclosure, the step difference between the first convex portion CVP1 and the first flat portion PP1 may be defined as a difference between the upper surface of the first flat portion PP1 and a portion which is the most protruded in the upper surface of the first convex portion CVP1. The first convex portion CVP1 may have a width equal to or greater than about 2.5 μm and equal to or less than about 4.5 μm, however, the present disclosure should not be limited thereto or thereby.
Referring to
Referring to
The organic layer OL may include at least the light emitting layer EML (refer to
The organic first slant portion OL-AP1 may have a thickness smaller than a thickness of the organic first flat portion OL-PP1 or the organic second slant portion OL-AP2.
The thickness of the organic first slant portion OL-AP1 may be about 10% or more and about 30% or less of the thickness of the organic first flat portion OL-PP1 or the organic second slant portion OL-AP2. In detail, the thickness of the organic first slant portion OL-AP1 may be about 10% or more or about 30% or less of the thickness of the organic first flat portion OL-PP1. The thickness of the organic first slant portion OL-AP1 may be about 10% or more and about 30% or less of the thickness of the organic second slant portion OL-AP2.
The organic first convex portion OL-CVP1, the organic first flat portion OL-PP1, the organic spacer portion OL-SP, and the organic second slant portion OL-AP2 may have substantially the same thickness as each other. The electrode first convex portion CE-CVP1, the electrode first flat portion CE-PP1, the electrode spacer portion CE-SP, and the electrode second slant portion CE-AP2 may have substantially the same thickness as each other, however, the present disclosure should not be limited thereto or thereby.
In a case where the thickness of the organic first slant portion OL-AP1 is smaller than about 10% of the thickness of the organic first flat portion OL-PP1 or the organic second slant portion OL-AP2, the organic first slant portion OL-AP1 with the above-described thickness may be difficult to implement in terms of manufacturing process. In a case where the thickness of the organic first slant portion OL-AP1 is greater than about 30% of the thickness of the organic first flat portion OL-PP1 or the organic second slant portion OL-AP2, the current may be leaked to the lateral side through the organic first slant portion OL-AP1, and the brightness may be lowered.
When the angle between the first slant surface AS1 and the upper surface of the base layer BS is equal to or greater than about 70°, it is difficult for the current to flow through the organic first slant portion OL-AP1 since the thickness of the organic first slant portion OL-AP1 is relatively thin compared with that when the angle between the first slant surface AS1 and the upper surface of the base layer BS is smaller than about 40°. As a result, the lateral leakage current may be prevented from being generated, and the occurrence of the color mixture between the pixel areas adjacent to each other and the deterioration of the brightness may be prevented.
Referring to
A closed portion CPP may be defined in each of the pixel areas PXA-B, PXA-R, and PXA-G to overlap a non-pixel area NPXA and to surround a portion of each of the pixel areas PXA-B, PXA-R, and PXA-G. The closed portion CPP may include a portion of the first convex portion CVP1 and a portion of the second convex portion CVP2. The closed portion CPP may surround the portion of each of the pixel areas PXA-B, PXA-R, and PXA-G and may not surround the other portion of each of the pixel areas PXA-B, PXA-R, and PXA-G. The closed portion CPP may include a first closed portion CPP1 surrounding a portion of a first pixel area PXA-B, a second closed portion CPP2 surrounding a portion of a second pixel area PXA-R, and a third closed portion CPP3 surrounding a portion of a third pixel area PXA-G.
In the present disclosure, a portion of each of the pixel areas PXA-B, PXA-R, and PXA-G, which is not surrounded by the closed portion CPP, will be referred to as an opened portion OPP. The opened portion OPP may include a first opened portion OPP1 surrounding a portion of the first pixel area PXA-B, a second opened portion OPP2 surrounding a portion of the second pixel area PXA-R, and a third opened portion OPP3 surrounding a portion of the third pixel area PXA-G. The ratio of a length of the opened portion OPP to a total length including the length of the opened portion OPP and a length of the closed portion CPP in a specific pixel area may be defined as a cathode open ratio (%). As an example, when a sum of a length of the first opened portion OPP1 and a length of the first closed portion CPP1 is five times greater than the length of the first opened portion OPP1 in the first pixel area PXA-B, the cathode open ratio may be about 20%.
Meanwhile, the cathode open ratio (%) may be within a range from about 20% or more to about 30% or less, however, this is merely example. In a case where the cathode open ratio (%) is smaller than about 20%, the driving voltage excessively increases, and thus, an efficiency of the display device may be lowered. In a case where the cathode open ratio (%) is greater than about 30%, the lateral leakage current is excessively generated. As a result, the color mixture may occur between the pixels adjacent to each other, and thus, optical characteristics of the display device may be deteriorated.
A base layer BS may include the first pixel area PXA-B and the second pixel area PXA-R adjacent to the first pixel area PXA-B, a pixel definition layer PDL-2, which is provided with a pixel opening OP corresponding to each of the first pixel area PXA-B and the second pixel area PXA-R, may be disposed on the base layer BS, and at least a portion of a first electrode AE may be disposed in the pixel opening OP.
The pixel definition layer PDL-2 may be disposed on the pixel areas PXA-B, PXA-R, and PXA-G and the base layer BS and may include a first slant portion AP1, a second slant portion AP2, a first convex portion CVP1, and a first flat portion PP1.
The first slant portion AP1 may include the first slant surface AS1 inclined at a first angle AG1 with respect to an upper surface of the base layer BS.
The second slant portion AP2 may include a second slant surface AS2 spaced apart from the first slant portion AP1 and inclined at a second angle AG2 with respect to the upper surface of the base layer BS.
The third slant portion AP3 may face the first slant portion AP1. The pixel definition layer PDL-2 may further include a third slant surface AS3 inclined at a third angle AG3 with respect to the upper surface of the base layer BS.
The pixel definition layer PDL-2 may further include a concave portion CCP disposed between the first slant portion AP1 and a third slant portion AP3. The upper surface of the base layer BS, the first electrode AE, and an upper surface of the concave portion CCP may be substantially parallel to each other.
The pixel definition layer PDL-2 may include a fourth slant portion AP4 spaced apart from the second slant portion AP2 with the first slant portion AP1 and the third slant portion AP3 interposed therebetween and including a fourth slant surface AS4 inclined at a fourth angle AG4 with respect to the base layer BS.
In a case where the angle between the slant surface AS1, AS2, AS3 and AS4 and the upper surface of the base layer BS is greater than about 130°, a damage, such as cracks, may be generated in the upper insulating layer TFL (refer to
The pixel definition layer PDL-2 may further include the second convex portion CVP2 disposed between the first slant portion AP1 and the second slant portion AP2. A separation distance between the first convex portion CVP1 and the second convex portion CVP2 may be equal to or greater than about 4 μm and equal to or less than about 6 μm, however, the present disclosure should not be limited thereto or thereby.
The pixel definition layer PDL-2 may further include a second flat portion PP2 disposed between the second convex portion CVP2 and the second slant surface AS2. An upper surface of the second flat portion PP2 may be substantially parallel to the upper surface of the base layer BS.
A step difference between the first convex portion CVP1 and the first flat portion PP1 may be equal to or greater than about 0.2 μm and equal to or less than about 1.0 μm. That is, a distance between an upper surface of the first convex portion CVP1 and the upper surface of the base layer BS in the thickness direction may be greater by about 0.2 micrometers or more and about 1.0 micrometers or less compared to a distance between the upper surface of the first flat portion PP1 and the upper surface of the base layer BS.
Each of the first convex portion CVP1 and the second convex portion CVP2 may have a width equal to or greater than about 2.5 μm and equal to or less than about 4.5 μm, however, the present disclosure should not be limited thereto or thereby.
Referring to
The organic layer OL may include at least a light emitting layer EML (refer to
The second electrode CE may include an electrode fourth slant portion CE-AP4 disposed on the organic fourth slant portion OL-AP4, an electrode first flat portion CE-PP1 disposed on the organic first flat portion OL-PP1, an electrode first convex portion CE-CVP1 disposed on the organic first convex portion OL-CVP1, an electrode third slant portion CE-AP3 disposed on the organic third slant portion OL-AP3, an electrode concave portion CE-CCP disposed on the organic concave portion OL-CCP, an electrode first slant portion CE-AP1 disposed on the organic first slant portion OL-AP1, an electrode second convex portion CE-CVP2 disposed on the organic second convex portion OL-CVP2, an electrode second flat portion CE-PP2 disposed on the organic second flat portion OL-PP2, and an electrode second slant portion CE-AP2 disposed on the organic second slant portion OL-AP2.
The organic fourth slant portion OL-AP4, the organic first flat portion OL-PP1, the organic first convex portion OL-CVP1, the organic concave portion OL-CCP, the organic second convex portion OL-CVP2, the organic second flat portion OL-PP2, and the organic second slant portion OL-AP2 may have substantially the same thickness as each other.
The organic third slant portion OL-AP3 and the organic first slant portion OL-AP1 may have substantially the same thickness as each other.
The electrode fourth slant portion CE-AP4, the electrode first flat portion CE-PP1, the electrode first convex portion CE-CVP1, the electrode concave portion CE-CCP, the electrode second convex portion CE-CVP2, the electrode second flat portion CE-PP2, and the electrode second slant portion CE-AP2 may have substantially the same thickness as each other.
The electrode third slant portion CE-AP3 and the electrode first slant portion CE-AP1 may have substantially the same thickness as each other.
The thickness of each of the organic third slant portion OL-AP3 and the organic first slant portion OL-AP1 may be smaller than the thickness of the organic first flat portion OL-PP1 or the organic second flat portion OL-PP2.
The thickness of each of the organic third slant portion OL-AP3 and the organic first slant portion OL-AP1 may be about 10% or more and about 30% or less of the thickness of the organic first flat portion OL-PP1 or the organic second flat portion OL-PP2. That is, the thickness of the organic third slant portion OL-AP3 may be about 10% or more and about 30% or less of the thickness of the organic first flat portion OL-PP1 or the organic second flat portion OL-PP2, and the thickness of the organic first slant portion OL-AP1 may be about 10% or more and about 30% or less of the thickness of each of the organic first flat portion OL-PP1 or the organic second flat portion OL-PP2, however, the present disclosure should not be limited thereto or thereby.
In a case where the thickness of the organic third slant portion OL-AP3 is smaller than about 10% of the thickness of the organic first flat portion OL-PP1 or the organic second flat portion OL-PP2 and in a case where the thickness of the organic first slant portion OL-AP1 is smaller than about 10% of the thickness of the organic first flat portion OL-PP1 or the organic second flat portion OL-PP2, the organic third slant portion OL-AP3 and the organic first slant portion OL-AP1 with the above-described thickness may be difficult to implement in terms of manufacturing process.
In a case where the thickness of the organic third slant portion OL-AP3 is greater than about 30% of the thickness of the organic first flat portion OL-PP1 or the organic second flat portion OL-PP2 and the thickness of the organic first slant portion OL-AP1 is greater than about 30% of the thickness of the organic first flat portion OL-PP1 or the organic second flat portion OL-PP2, the current may leak to the lateral side through the organic third slant portion OL-AP3 or the organic first slant portion OL-AP1, and the brightness is lowered.
When an angle between the upper surface of the base layer BS and each of the first slant surface AS1 and the third slant surface AS3 is equal to or greater than about 70°, it is difficult for the current to flow through the second electrode CE since the thickness of the organic layer OL and the second electrode CE, which are disposed on the first slant surface AS1 and the third slant surface AS3, is relatively thin. As a result, the lateral leakage current may be prevented from being generated, and the occurrence of the color mixture between the pixel areas adjacent to each other and the deterioration of the brightness may be prevented.
Referring to
Referring to
Referring to
In detail, each of a first angle AG1, a third angle AG3, and the fourth angle AG4 may be equal to or greater than about 70° and equal to or less than about 130°, and the second angle AG2 may be equal to or greater than about 10° and equal to or less than about 40°.
In a case where an angle between the slant surface AS1, AS2, AS3 and AS4 and the upper surface of the base layer BS is greater than about 130°, a damage, such as cracks, may be generated in the upper insulating layer TFL (refer to
Referring to
Meanwhile, although not shown in figures, the manufacturing method of the display panel may further include removing the mask after the forming of the pixel definition layer.
Referring to
The manufacturing method of the display panel may include the providing of the mask MK above the preliminary pixel definition layer P-PDL. The mask MK may include the first portion PA1 in which the first exposure non-transmissive portion NTP-1, the first exposure transmissive portion TP-1, and the first exposure semi-transmissive portion HTP-1 are sequentially arranged along a direction opposite to the second direction DR2 and the second portion PA2 in which the second exposure transmissive portion TP-2, the second exposure semi-transmissive portion HTP-2, and the second exposure non-transmissive portion NTP-2 are sequentially arranged along the direction opposite to the second direction DR2.
After the providing of the mask MK, the manufacturing method of the display panel may include providing the light L onto the mask MK to expose the preliminary pixel definition layer P-PDL to the light L. The light L may be provided to the entire surface of the mask MK. That is, the light L may be provided to the first portion PA1 in which the first exposure non-transmissive portion NTP-1, the first exposure transmissive portion TP-1, and the first exposure semi-transmissive portion HTP-1 are sequentially arranged along the direction opposite to the second direction DR2 and the second portion PA2 in which the second exposure transmissive portion TP-2, the second exposure semi-transmissive portion HTP-2, and the second exposure non-transmissive portion NTP-2 are sequentially arranged along the direction opposite to the second direction DR2. In other words, the light L may be provided to the non-transmissive portions NTP-1 and NTP-2, the exposure transmissive portions TP-1 and TP-2, and the exposure semi-transmissive portions HTP-1 and HTP-2 included in the first portion PA1 and the second portion PA2.
After the exposure process, the portions of the preliminary pixel definition layer P-PDL, which is cured after being exposed to the light L in the manufacturing method of the display panel, may be formed as the pixel definition layer PDL-1. The manufacturing method of the display panel may include the removing of the portions of the preliminary pixel definition layer P-PDL, which are not cured.
The pixel definition layer PDL-1 may include the first slant portion AP1 formed corresponding to the first exposure non-transmissive portion NTP-1 included in the first portion PA1, the first convex portion CVP1 formed corresponding to the first exposure transmissive portion TP-1 included in the first portion PA1, the first flat portion PP1 formed corresponding to the first exposure semi-transmissive portion HTP-1 included in the first portion PA1, the spacer SP formed corresponding to the second exposure transmissive portion TP-2 included in the second portion PA2, and the second slant portion AP2 formed corresponding to the second exposure semi-transmissive portion HTP-2 included in the second portion PA2.
The first slant portion AP1 may include the first slant surface AS1 inclined at the first angle AG1 with respect to the upper surface of the base layer BS, and the second slant portion AP2 may include the second slant surface AS2 inclined at the second angle AG2 with respect to the upper surface of the base layer BS.
Referring to
A graph of R2=0.8536 represents a relationship of the voltage increase (V) to the cathode open ratio (%), and a graph of R2=0.9291 represents the value of the gray crushing red (%) with respect to the cathode open ratio (%). A total of sixteen experiments were conducted, and in detail, eight experiments to measure the value of the gray crushing red (%) for each cathode open ratio % of about 4%, 5%, 10%, 20%, 30%, 40%, and 100% and eight experiments to measure the voltage increase (V) for each cathode open ratio % of about 4%, 5%, 10%, 20%, 30%, 40%, and 100% were conducted.
Referring to
According to the display panel DP, it is observed that as the value of the cathode open ratio (%) increases, the value of the voltage increase (V) is improved compared with when the value of the cathode open ratio (%) decreases.
That is, as the cathode open ratio (%) decreases, the value of the gray crushing red (%) is improved, but the value of the voltage increase (V) also increases, thereby deteriorating the efficiency.
In general, when the driving voltage (V) increases above 0.20 volts, the efficiency is not improved compared to the related art. Therefore, it is observed that a section where the voltage increase (V) has a value of about 0.20 voltage or less and the value of the gray crushing red (%) maintains about 90% or more is an optimal section, and this is the section in which the value of the cathode open ratio (%) is about 20% or more and about 30% or less.
Although the embodiments of the present disclosure have been described, it is understood that the present disclosure should not be limited to these embodiments but various changes and modifications can be made by one of ordinary skill in the art within the spirit and scope of the present disclosure as hereinafter claimed. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the present inventive concept shall be determined according to the attached claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0043375 | Apr 2023 | KR | national |
