Patent Application
20240162326
This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0150620, filed on Nov. 11, 2022, the entire content of which is incorporated by reference herein.
Aspects of embodiments of the present disclosure relate to a display panel, and more particularly, to a display panel including low resistance lines, and a method of manufacturing the same.
A display panel includes pixels for displaying an image. The pixel may include a display element, and signal lines or a driving element. The display element may include an emissive element or a reflective element. The driving element may include transistors and capacitors. The signal lines electrically connect the driving element, the display element, and other pixels to one another. The signal lines may transfer various electrical signals, and the display element and the driving element may be driven by the electrical signals provided from the signal lines.
The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure, and therefore, it may contain information that does not constitute prior art.
One or more embodiments of the present disclosure are directed to a display panel including low resistance lines, and a method of manufacturing the same.
According to one or more embodiments of the present disclosure, a display panel includes: a base substrate; a light emitting element on the base substrate; a transistor between the base substrate and the light emitting element, and connected with the light emitting element; and a conductive pattern between the base substrate and the light emitting element. The conductive pattern includes: a first conductive layer including a first material; a second conductive layer on the first conductive layer, and including a second material different from the first material; a blocking layer between the first conductive layer and the second conductive layer, and including a third material different from the first material; and an intermediate layer between the blocking layer and the second conductive layer, and contacting the second conductive layer. The intermediate layer includes an alloy of the first material and the second material.
In an embodiment, the first material may have a lower resistance than that of the second material.
In an embodiment, the third material may include a nitride of the second material.
In an embodiment, the second material may include titanium.
In an embodiment, the first material may include aluminum.
In an embodiment, the intermediate layer may contact the blocking layer.
In an embodiment, the intermediate layer may have a smaller thickness than that of the first conductive layer.
In an embodiment, the display panel may further include a shielding layer on the second conductive layer.
In an embodiment, the shielding layer may have a lower light transmittance than that of the second conductive layer.
In an embodiment, the shielding layer may include amorphous carbon.
In an embodiment, the transistor may include low-temperature polysilicon silicon.
In an embodiment, the conductive pattern may be a gate of the transistor, or a signal line located at a same layer as that of the gate.
According to one or more embodiments of the present disclosure, a display panel manufacturing method includes: providing a semiconductor pattern including amorphous silicon; providing a first conductive pattern including a first layer, a second layer, a third layer, and a fourth layer that are sequentially stacked; performing a first heat treatment; providing an additional layer on the first conductive pattern; and performing a second heat treatment for crystallizing the semiconductor pattern. In the performing of the first heat treatment, the fourth layer diffuses into the third layer to form an intermediate layer, and the intermediate layer includes an alloy of a material of the fourth layer and a material of the third layer.
In an embodiment, the performing of the first heat treatment may continue at a temperature of 600 degrees or lower.
In an embodiment, the intermediate layer may include an alloy of aluminum and titanium.
In an embodiment, the second layer may include titanium nitride.
In an embodiment, the performing of the second heat treatment may continue at a temperature of 600 degrees or lower.
In an embodiment, the first conductive pattern may further include a fifth layer on the fourth layer, and the fifth layer may have a higher light transmittance than that of the fourth layer.
In an embodiment, the fifth layer may have a lower light transmittance than that of the fourth layer after the performing of the first heat treatment.
In an embodiment, the fifth layer may include amorphous carbon.
In an embodiment, the method may further include forming at least one contact hole in the additional layer by an etching gas, and the etching gas may include fluorine.
The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of the illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:
Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numbers refer to like elements throughout. The present disclosure, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present disclosure may not be described. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and the written description, and thus, redundant description thereof may not be repeated.
When a certain embodiment may be implemented differently, a specific process order may be different from the described order. For example, two consecutively described processes may be performed at the same or substantially at the same time, or may be performed in an order opposite to the described order.
In the drawings, the relative sizes, thicknesses, and ratios of elements, layers, and regions may be exaggerated and/or simplified for clarity. Spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
In the figures, the x-axis, the y-axis, and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to or substantially perpendicular to one another, or may represent different directions from each other that are not perpendicular to one another.
It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure.
It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. Similarly, when a layer, an area, or an element is referred to as being “electrically connected” to another layer, area, or element, it may be directly electrically connected to the other layer, area, or element, and/or may be indirectly electrically connected with one or more intervening layers, areas, or elements therebetween. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” “including,” “has,” “have,” and “having,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and/or B” denotes A, B, or A and B. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression “at least one of a, b, or c,” “at least one of a, b, and c,” and “at least one selected from the group consisting of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.
As used herein, the term “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent variations in measured or calculated values that would be recognized by those of ordinary skill in the art. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.” As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.
Referring to
The display device 1000 may display an image through a display surface DD-IS. The display DD-IS is parallel to or substantially parallel to a surface defined by a first direction DR1 and a second direction DR2. The top surface of a member disposed at (e.g., in or on) the uppermost side of the display device 1000 may be defined as the display surface DD-IS. The normal direction of the display surface DD-IS, or in other words, the thickness direction of the display device 1000, is indicated by a third direction DR3. The front surfaces (e.g., top surfaces) and the rear surfaces (e.g., bottom surfaces) of the layers or units to be described in more detail below are distinguished from each other by the third direction DR3.
A display area 1000A and a non-display area 1000NA may be defined in the display device 1000. The non-display area 1000NA may be a peripheral area of the display area 1000A. The display device 1000 may display an image through the display area 1000A. The non-display area 1000NA may surround (e.g., around a periphery of) the display area 1000A. In an embodiment of the present disclosure, the non-display area 1000NA may be omitted as needed or desired, or may be disposed in (e.g., only in) one side of the display area 1000A.
Referring to
The display panel 100 may be a component configured to generate or substantially generate an image. The display panel 100 may be an emissive display panel, for example, such as an organic light emitting display panel, an inorganic light emitting display panel, an organic-inorganic display panel, a quantum dot display panel, a micro LED display panel, or a nano LED display panel.
The sensor layer 200 may be disposed on the display panel 100. The sensor layer 200 may sense an external input that is applied from the outside. The external input may be a user input. The user input includes various suitable kinds of external inputs including, for example, a part of the user's body, a pen, light, heat, pressure, and/or the like.
The sensor layer 200 may be provided on the display panel 100 through continuous processes. In this case, the sensor layer 200 may be represented as being directly disposed on the display panel 100. As used herein, the phrase “directly disposed” may mean that a third element is not disposed between the two elements (e.g., the sensor layer 200 and the display panel 100). In other words, a separate adhesive member may not be disposed between the sensor layer 200 and the display panel 100. In another embodiment, the sensor layer 200 may be combined with the display panel 100 through an adhesive member. The adhesive member may include a typical adhesive known to those having ordinary skill in the art, or a pressure sensitive adhesive. In an embodiment of the present disclosure, the sensor layer 200 may be omitted as needed or desired.
The optical film 300 may lower a reflectance of external light incident from the outside (e.g., externally). The optical film 300 may include a retarder and/or a polarizer. The optical film 300 may be referred to as a polarization film. The optical film may be connected to (e.g., attached to or coupled to) the sensor layer 200 through the adhesive layer.
As another example, the optical film 300 may include color filters. The color filters may have a suitable array (e.g., a prescribed or predetermined array). The array of the color filters may be determined in consideration of the light emission colors of the pixels included in the display panel 100. The optical film 300 may further include a black matrix that is adjacent to the color filters.
As another example, the optical film 300 may include a destructive interference structure. For example, the destructive interference structure may include a first reflection layer and a second reflection layer disposed at (e.g., in or on) different layers from each other. First reflection light and second reflection light reflected by the first reflection layer and the second reflection layer, respectively, may destructively interfere with each other, and accordingly, an external light reflection ratio may be reduced.
The window 400 may be disposed on the optical film 300. The window 400 may include an insulation material that is optically transparent. For example, the window 400 may include glass or plastic. The window 400 may have a multilayered structure or a single-layer structure. For example, the window 400 may include a plurality of plastic films that are bonded to one another with an adhesive, or a glass substrate and a plastic film that are bonded to each other with an adhesive.
Referring to
The driving controller 100C receives an image signal RGB and a control signal CTRL. The driving controller 100C may generate an image data signal DATA by converting the data format of the image signal RGB, so as to be matched with the specification of the interface with the data driver 2000. The driving controller 100C may output a first control signal GCS, a second control signal ECS, and a third control signal DCS.
The data driver 2000 may receive the third control signal DCS and the image data signal DATA from the driving controller 100C. The data driving circuit 2000 converts the image data signal DATA into data signals, and outputs the data signals to a plurality of data lines DL1 to DLm to be described in more detail below. The data signals may be analog voltages corresponding to a grayscale value of the image data signal DATA.
The scan driver 3000 may receive the first control signal GCS from the driving controller 100C. The scan driver 3000 may output scan signals to scan lines in response to the first control signal GCS.
The voltage generator 4000 generates voltages used for the operations of the display panel 100. In an embodiment, the voltage generator 4000 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.
The display panel 100 may include a display area DA and a non-display area NDA. The display panel 100 may include a plurality of pixels PX disposed in the display area DA. The plurality of pixels PX may be arranged according to a suitable rule (e.g., a prescribed or predetermined rule).
The display panel 100 further includes the data lines DL1 to DLm, the scan lines, and emission control lines EL1 to ELn. The scan lines may include initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, and write scan lines GWL1 to GWLn. Here, m and n may be positive integers.
The data lines DL1 to DLm extend in the first direction DR1, and are spaced apart from each other in the second direction DR2. The initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, and the emission control lines EL1 to ELn extend in the second direction DR2. The initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, and the emission control lines EL1 to ELn are spaced apart from each other in the first direction DR1.
The plurality of pixels PX are electrically connected to the initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, the emission control lines EL1 to ELn, and the data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines. For example, as shown in
The scan driver 3000 may be disposed in the non-display area NDA of the display panel 100. The scan driver 3000 may receive the first control signal GCS from the driving controller 100C. The scan driver 3000 outputs initialization scan signals to the initializations scan lines GIL1 to GILn in response to the first control signal GCS, and outputs compensation scan signals to the compensation scan lines GCL1 to GCLn. In addition, the scan driver 3000 may output write scan signals to the write scan lines GWL1 to GWLn in response to the first control signal GCS. As another example, the scan driver 3000 may include first and second scan drivers. The first scan driver may output the initialization scan signals and the compensation scan signals, and the second scan driver may output the write scan signals.
The emission driver 350C may be disposed in the non-display area NDA of the display panel 100. The emission driver 350C may receive the second control signal ECS from the driving controller 100C. The emission driver 350C may output emission control signals to the plurality of emission control lines EL1 to ELn in response to the second control signal ECS. As another example, the scan driver 3000 may be connected to the plurality of emission lines EL1 to ELn. In this case, the scan driver may output the emission control signals to the emission control lines EL1 to ELn.
Referring to
The pixel PXij may include a light emitting element ED and a pixel driving circuit PDC. The light emitting element ED may include a light emitting diode. As an example of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer.
The pixel driving circuit PDC may include first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and a storage capacitor (e.g., one storage capacitor) Cst. The first to seventh transistors T1 to T7 may be referred to as (e.g., may include) a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, a emission control thin-film transistor T6, and a second initialization thin-film transistor T7.
Some of the first to seventh transistors T1 to T7 may be P-type transistors, and the others may be N-type transistors. For example, the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be PMOS transistors, and the third and fourth transistors T3 and T4 may be NMOS transistors.
At least one from among the first to seventh transistors T1 to T7 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one from among the first to seventh transistors T1 to T7 may be a transistor having an oxide semiconductor layer.
In more detail, the first transistor T1, which directly influences the brightness of the display device, may be configured to include a semiconductor layer composed of a high reliable polycrystalline silicon, and thus, a display device having a high resolution may be implemented.
On the other hand, the oxide semiconductor has a high carrier mobility and a low leakage current, and thus, a voltage drop may not be large even with a long driving time. In other words, because a color change in an image according to the voltage drop may not be large even in a low frequency driving mode, low frequency driving may be possible. As such, the oxide semiconductor may desirably have a small leak current, and thus, at least one of the third transistor T3 connected to a driving gate electrode of the first transistor T1 or the fourth transistor T4 may employ (e.g., may be formed of) the oxide semiconductor to prevent or substantially prevent the leak current, which may flow to the driving gate electrode, and also, power consumption may be reduced.
Each of the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be a transistor having an LTPS transistor layer, and each of the third and fourth transistors T3 and T4 may be a transistor having an oxide semiconductor layer.
The configuration of the pixel driving circuit PDC is not limited to the embodiment shown in
The j-th initialization scan line GILj, the j-th compensation scan line GCLj, the j-th write scan line GWLj, the (j+1)-th write scan line GWLj+1, and the j-th emission control line EMj may respectively transfer, to the pixel PXij, a j-th initialization scan signal Glj, a j-th compensation scan signal GCj, a j-th write scan signal GWj, a (j+1)-th write scan signal GWj+1, and a j-th emission control signal ELj. The i-th data line DLi transfers an i-th data signal Di to the pixel PXij. The i-th data signal Di may have a voltage level corresponding to the image signal RGB (e.g., see
A first driving voltage line VL1 and a second driving voltage line VL2 may respectively transfer, to the pixel PXij, the first driving voltage ELVDD and the second driving voltage ELVSS. In addition, a first initialization voltage line VL3 may transfer a first initialization voltage VINT1 to the pixel PXij.
The first transistor T1 is connected between the first driving voltage line VL1 for receiving the first driving voltage and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via the fifth transistor T5, a second electrode electrically connected to an anode of the light emitting element ED via the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end of the storage capacitor Cst. The first transistor T1 may receive the i-th data signal Di transferred by the i-th data line DLi according to a switching operation of the second transistor T2, and may provide a driving current Id to the light emitting element ED.
The second transistor T2 is connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate connected to the j-th write scan line GWLj. The second transistor T2 may be turned on in response to the j-th write scan signal GWj transferred via the j-th write scan line GWLj, to transfer the i-th data signal Di, which has been transferred from the i-th data line DLi, to the first electrode of the first transistor T1.
The third transistor T3 is connected between the second electrode of the first transistor T1 and a first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate connected to the j-th compensation scan line GCLj. The third transistor T3 may be turned on in response to the j-th compensation scan signal GCj transferred via the j-th compensation scan line GCLj, to connect the third electrode (e.g., the gate) and the second electrode of the first transistor T1 to each other to diode-connect the first transistor T1.
The fourth transistor T4 is connected between the first initialization voltage line VL3 through which the first initial voltage VINT1 is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the gate of the first transistor T1, a second electrode connected to the first initialization voltage line VL3 through which the first initialization voltage VINT1 is transferred, and a gate connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on in response to the j-th initialization scan signal Glj transferred via the j-th initialization scan line GILj. The turned-on fourth transistor T4 transfers the first initialization voltage VINT1 to the gate of the first transistor T1, to initialize a potential at the gate of the first transistor T1 (i.e., the potential of the first node N1).
The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate connected to the j-th emission control line ELj.
The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate connected to the j-th emission control line ELj.
The fifth and sixth transistors T5 and T6 may be concurrently or substantially simultaneously turned on with each other in response to the j-th emission control signal EMj transferred via the j-th emission control line ELj. The first driving voltage ELVDD applied through the turned on fifth transistor T5 may be compensated for through the diode-connected first transistor T1, and then transferred to the light emitting element ED.
The seventh transistor T7 includes a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT1 is applied, a second electrode connected to the second electrode of the sixth transistor T6, and a gate connected to the (j+1)-th write scan line GWLj+1. As an example of the present disclosure, the first initialization voltage VINT1 may have a negative electrostatic voltage. For example, the first initialization voltage VINT1 may be about −3.5 V, but is not particularly limited thereto.
As described above, one end of the storage capacitor Cst is connected to the gate of the first transistor T1, and the other end of the storage capacitor Cst is connected to the first driving voltage line VL1. A cathode of the light emitting diode ED may be connected to the second driving voltage line VL2 configured to transfer the second driving voltage ELVSS. The second driving voltage ELVSS may have a lower level than that of the first driving voltage ELVDD. As an example of the present disclosure, the second driving voltage ELVSS may have a lower level than that of the first initialization voltage VINT1.
During an activation period of the j-th initialization scan signal Glj, when the j-th initialization scan signal Glj of a turn-on level (e.g., a high level) is applied through the j-th initialization scan line GILj, the fourth transistor T4 is turned on in response to the j-th initialization scan signal Glj of the turn-on level (e.g., the high level). The first initialization voltage VINT1 is transferred to the gate of the first transistor T1 through the turned-on fourth transistor T4, and the first node N1 (e.g., the gate of the first transistor T1) is initialized by the first initialization voltage VINT1. Accordingly, the activation period of the j-th initialization scan signal Glj may be an initialization period of the pixel PXij.
Next, the j-th compensation scan signal GCj may be activated, and during the activation period of the j-th compensation scan signal GCj, the third transistor T3 is turned on. For example, the third transistor T3 is turned on when the j-th compensation scan signal GCj of a turn-on level (e.g., a high level) is applied through the j-th compensation scan line GCj. The first transistor T1 is diode-connected and biased in a forward direction by the turned-on third transistor T3.
In addition, within the activation period of the j-th compensation scan signal GCj, the j-th write scan signal GWj may be activated. The j-th write scan signal GWj has a turn-on level (e.g., a low level) during the activation period. During the activation period of the j-th write scan signal GWj, the second transistor T2 is turned on by the j-th write scan signal GWj of the turn-on level (e.g., the low level). Then, a compensation voltage “Di-Vth”, which is reduced by a threshold voltage Vth of the first transistor T1 from the i-th data signal Di supplied from the data line DLi, is applied to the gate of the first transistor T1. In other words, the potential of the gate of the first transistor T1 may be the compensation voltage “Di-Vth”.
The first driving voltage ELVDD and the compensation voltage “Di-Vth” are applied to both ends of the capacitor Cst, and charges corresponding to a voltage difference thereof may be stored in the storage capacitor Cst. Here, the turn-on level period (e.g., the high level period) of the j-th compensation scan signal GCj may be referred to as a compensation period of the pixel PXij.
The (j+1)-th write scan signal (GWj+1) is then activated. The (j+1)-th write scan signal (GWj+1) has a turn-on level (e.g., a low level) during the activation period. During the activation period of the (j+1)-th write scan signal (GWj+1), the seventh transistor T7 is turned on. A portion of the driving current Id may be a bypass current Ibp that may get out through the seventh transistor T7.
Even when a minimum current of the first transistor T1, which displays a black image, flows as the driving current, the black image may not be properly displayed if the light emitting element ED emits light. Accordingly, the seventh transistor T7 in the pixel PXij according to an embodiment of the present disclosure may pass, as the bypass current Ibp, a portion of the minimum current of the first transistor T1 to a current path other than a current path to the light emitting element. Here, the minimum current of the first transistor T1 means a current under a condition that a gate-source voltage Vgs of the first transistor T1 is smaller than the threshold voltage Vth to turn off the first transistor T1. Under such a condition of turning off the first transistor T1, the minimum driving current (for example, a current of 10 pA or smaller) may be transferred to the light emitting element ED to display a black luminance image. When the minimum driving current for displaying the black image flows, an influence by the bypass current Ibp may be large. However, when a large driving current for displaying a typical image or a white image flows, there may be little influence by the bypass current Ibp. Accordingly, when the driving current for displaying the black image flows, the emission current led of the light emitting element ED, which is reduced from the driving current Id by a current amount of the bypass current Ibp bypassed through the seventh transistor T7, may have a minimum current amount that may reliably display the black image. Accordingly, a contrast ratio may be improved by implementing an accurate black luminance image using the seventh transistor T7.
Then, the j-th emission control signal EMj applied from the j-th emission control line ELj changes from a turn-off level (e.g., a high level) to a turn-on level (e.g., a low level). The fifth and sixth transistors T5, T6 are turned on by the emission control signal EMj. Thus, the driving current Id is generated according to the difference between the gate voltage of the first transistor T1 and the first driving voltage ELVDD, and the driving current Id is supplied to the light emitting element ED via the sixth transistor T6, so that the current led flows to the light emitting element ED.
Referring to
The substrate 110 may be a member for providing a base surface on which the circuit layer 120 is disposed. The substrate 110 may be a rigid substrate, or a flexible substrate that is bendable, foldable, rollable, or the like. The substrate 110 may be a glass substrate, a metal substrate, a polymer substrate, or the like. However, the present disclosure is not limited thereto, and the substrate 110 may be an inorganic layer, an organic layer, or a composite material layer.
The substrate 110 may have a multilayered structure. For example, the substrate 110 may include a first synthetic resin layer, an intermediate layer of a multilayered or single layer structure, and a second synthetic resin layer disposed on the intermediate layer. The intermediate layer may be referred to as a base barrier layer. The intermediate layer may include a silicon oxide (SiOx) layer, and an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, but is not particularly limited thereto. For example, the intermediate layer may include at least one from among a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an amorphous silicon layer.
Each of the first and second synthetic resin layers may include a polyimide-based resin. In addition, each of the first and second synthetic resin layers may include at least one from among an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, or a perylene-based resin. Further, in the present embodiment, “˜”-based resin means including a functional group of “˜”.
At least one inorganic layer is provided on the top surface of the substrate 110. The inorganic layer may include at least any suitable one from among aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, or halfnium oxide. The inorganic layer may be provided with multiple layers. The multiple inorganic layers may constitute a barrier layer BRL and/or a buffer layer BFL to be described in more detail below. The barrier layer BRL and the buffer layer BFL may be selectively (e.g., optionally) disposed.
The barrier layer BRL prevents or substantially prevents inflow of foreign matters from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of these layers may be provided in a plurality, and the silicon oxide layers and the silicon nitride layers may be alternately disposed (e.g., alternately laminated).
The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may improve a bonding force between the substrate 110 and a semiconductor pattern and/or a conductive pattern. The buffer layer BFL may include silicon oxide layers and silicon nitride layers. The silicon oxide layers and the silicon nitride layers may be alternately disposed (e.g., alternately laminated).
The semiconductor pattern may be disposed on the buffer layer BFL. Hereinafter, the semiconductor pattern that is directly disposed on the buffer layer BFL is defined as a first semiconductor pattern. The first semiconductor pattern may include a silicon semiconductor. The first semiconductor pattern may include polysilicon. However, the present disclosure is not limited thereto, and the first semiconductor pattern may include amorphous silicon.
The first area may have a greater conductivity than that of the second area, and may operate or substantially operate as an electrode or a signal line. The second area may correspond to or substantially correspond to an active area (e.g., a channel) of a transistor. In other words, a portion of the semiconductor pattern may be the active area of the transistor, another portion may be a source or a drain, and another portion may be a connection electrode or a signal connection line.
As shown in
The first insulation layer 10 may be disposed on the buffer layer BFL. The first insulation layer 10 may commonly overlap with the plurality of pixels PX, and may cover the first semiconductor pattern. The first insulation layer 10 may include an inorganic material and/or an organic material, and may have a single layer or multilayered structure. The first insulation layer 10 may include at least one from among aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, or hafnium oxide. In the present embodiment, the first insulation layer 10 may be a single layer of a silicon oxide layer. Not only the first insulation layer 10, but also the insulation layer of the circuit layer 120, which will be described in more detail below, may include an inorganic material and/or organic material, and may have a single layer or multilayered structure. The inorganic material layer may include at least one from among the aforementioned materials, but is not limited thereto.
The gate G1 of the first transistor T1 is disposed on the first insulation layer 10. The third electrode G1 may be a portion of the first conductive pattern. The gate G1 of the first transistor T1 may overlap with the channel part A1 of the first transistor T1. In a process for doping the first semiconductor pattern, the gate G1 of the first transistor T1 may function as a mask.
The second insulation layer 20 may be disposed on the first insulation layer 10, and may cover the gate G1 of the first transistor T1. The second insulation layer 20 may include an inorganic layer and/or organic layer, and may have a single layer or multilayered structure. The second insulation layer 20 may include at least one from among silicon oxide, silicon nitride, or silicon oxynitride. In the present embodiment, the second insulation layer 20 may have a multi-layered structure including a silicon oxide layer and a silicon nitride layer.
A third insulation layer 30 may be disposed on the second insulation layer 20. The third insulation layer 30 may have a single layer or multi-layered structure. For example, the third insulation layer 30 may have a multilayered structure including silicon oxide layers and silicon nitride layers. An upper electrode UE of the storage capacitor Cst may be disposed between the second insulation layer 20 and the third insulation layer 30. In addition, a lower electrode of the storage capacitor Cst may be disposed between the first insulation layer 10 and the second insulation layer 20. For example, in some embodiments, the gate G1 may function as the lower electrode of the storage capacitor Cst.
In an embodiment of the present disclosure, the second insulation layer 20 may be replaced with an insulation pattern. The upper electrode UE may be disposed on the insulation pattern. The upper electrode UE may serve as a mask used for providing an insulation pattern from the second insulation layer 20.
The second semiconductor pattern may be disposed on the third insulation layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of areas that are divided according to whether or not a metal oxide is reduced. An area (hereinafter, a reduced area) in which the metal oxide is reduced has a higher conductivity in comparison to an area (hereinafter, a non-reduced area) in which the metal oxide is not reduced. The reduced area may serve or substantially serve as a source/drain or a signal line of the transistor. The non-reduced area corresponds to or substantially corresponds to an active area (e.g., the semiconductor area, the channel part, and the like) of the transistor. In other words, a portion of the second semiconductor pattern may be the active area of the transistor, another portion may be a source/drain area of the transistor, and another portion may be a signal transfer area.
As shown in
A fourth insulation layer 40 may be arranged on the third insulation layer 30. The fourth insulation layer 40 may commonly overlap with the plurality of pixels PX, and may cover the second semiconductor pattern. The fourth insulation layer 40 may include at least one from among aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, or hafnium oxide.
The gate G3 of the third transistor T3 may be disposed on the fourth insulation layer 40. The gate G3 may be a portion of the third conductive pattern. The gate G3 of the third transistor T3 may overlap with the channel part A3 of the third transistor T3. In a process for doping the second semiconductor pattern, the gate G3 of the third transistor T3 may function as a mask.
In an embodiment of the present disclosure, the fourth insulation layer 40 may be replaced with an insulation pattern. The gate G3 of the third transistor T3 may be disposed on the insulation pattern. In the embodiment, the gate G3 may have the same or substantially the same shape as that of the insulation pattern in a plan view. In the embodiment, a single gate G3 is shown for convenience of illustration, but the third transistor T3 may also include two electrodes (e.g., two gates).
The fifth insulation layer 50 may be disposed on the fourth insulation layer 40, and may cover the gate G3 of the third transistor T3. The fifth insulation layer 50 may be an inorganic layer and/or an organic layer, and have a single layer or multilayered structure. For example, the fifth insulation layer 50 may include silicon oxide layers and silicon nitride layers. The fifth insulation layer 50 may include a plurality of silicon oxide layers and silicon nitride layers that are alternately disposed (e.g., alternately laminated).
The first and second electrodes of the fourth transistor T4 (e.g., see
The first connection electrode CNE10 may be disposed on the fifth insulation layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a contact hole CH1 penetrating through the first to fifth insulation layers 10, 20, 30, 40 and 50.
A sixth insulation layer 60 may be disposed on the fifth insulation layer 50. A second connection electrode CNE20 may be disposed on the sixth insulation layer 60. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a contact hole CH-60 penetrating through the sixth insulation layer 60. A seventh insulation layer 70 may be disposed on the sixth insulation layer 60, and may cover the second connection electrode CNE20.
Each of the sixth and seventh insulation layers 60 and 70 may be an organic layer. For example, each of the sixth and seventh insulation layers 60 and 70 may include a general purpose polymer, such as Benzocyclobutene (BCD), polyimide, Hexamethyldisiloxane (HMDSO), Polymethylmethacrylate (PMMA), or Polystyrene (PS), a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a suitable blend thereof.
The element layer 130 may include the light emitting element ED and a pixel definition layer PDL. The light emitting element ED may include an anode AE, a hole control layer HCL, a light emitting layer EML, an electronic control layer ECL, and a cathode CE.
The anode AE may be disposed on the seventh insulation layer 70. The anode AE may be connected with the second connection electrode CNE20 through a contact hole CH-70 penetrating through the seventh insulation layer 70. The anode AE may be a (semi-) transmissive electrode or a reflective electrode. In an embodiment, the anode AE may include a reflective layer composed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a suitable compound thereof, and a transparent or semi-transparent electrode layer provided on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium oxide (In2O3), and aluminum zinc oxide (AZO) doped with aluminum. For example, the anode AE may be provided with ITO/Ag/ITO.
The pixel definition layer PDL may be disposed on the seventh insulation layer 70. In an embodiment, the pixel definition layer PDL may have a light absorption property, and include, for example, a black color. The pixel definition layer PDL may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, aniline black, a suitable metal such as chromium, or suitable oxides thereof. The pixel definition layer PDL may be provided with a mixture of a blue organic material and a black organic material. The pixel definition layer PDL may include a lyophobic organic material.
An opening OP in the pixel definition layer PDL exposes at least a portion of the anode AE of the light emitting element ED. The opening OP in the pixel definition layer PDL may define a light emitting area PXA. For example, the plurality of pixels PX (e.g., see
The hole control layer HCL may be commonly disposed in the light emitting area PXA and the non-light emitting area NPXA. A common layer, such as the hole control layer HCL, may be commonly provided in the plurality of pixels PX. The hole control layer HCL may include a hole transport layer and a hole injection layer.
The light emitting layer EML is disposed on the hole control layer HCL. The light emitting layer EML may be commonly disposed in the plurality of pixels PX. In other words, the light emitting layer EML may be commonly disposed in the light emitting area PXA and the non-light emitting area NPXA. For example, the light emitting layer EML may be commonly provided by an open mask in both of the light emitting area PXA and the non-light emitting area NPXA. In this case, the light emitting layer EML may generate source light of white light or blue light. In addition, the light emitting layer EML may have a multilayered structure.
The display device 1000 (e.g., see
In another embodiment of the present disclosure, the light emitting layer EML may be disposed in (e.g., only in) an area corresponding to the opening OP. In this case, the light emitting layer EML may be provided in a plurality, and the plurality of light emitting layers EML may be separately provided in the plurality of pixels PX. The light emitting layers EML may generate the source light of white light or blue light. As another example, some of the light emitting layers EML may generate red light, others may generate green light, and the others may generate blue light. However, the present disclosure is not limited thereto, and some of the light emitting layers EML may generate mixed-color light, for example, such as magenta light, yellow light, or cyan light.
An electron control layer ECL is disposed on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and an electron injection layer. The cathode CE of the light emitting element ED is disposed on the electron control layer ECL. The electron control layer ECL and the cathode CE are commonly disposed in the plurality of pixels PX.
The encapsulation layer 140 is disposed on the cathode CE. The encapsulation layer 140 may cover the plurality of pixels PX. In an embodiment, the encapsulation layer 140 may directly cover the cathode CE. In an embodiment of the present disclosure, the display panel 100 may further include a capping layer directly covering the cathode CE. In an embodiment of the present disclosure, the light emitting element ED may also have a laminate structure that is vertically inverted from the structure shown in
The encapsulation layer 140 may be disposed on the element layer 130. The encapsulation layer 140 includes at least an inorganic layer or an organic layer. In an embodiment of the present disclosure, the encapsulation layer 140 may include two inorganic layers, and an organic layer interposed therebetween. In an embodiment of the present disclosure, a thin-film encapsulation layer may include a plurality of inorganic layers and a plurality of organic layers alternately disposed (e.g., alternately laminated) on each other.
The encapsulation organic layer protects the light emitting element ED from moisture/oxygen, and from foreign matters, such as dust particles. The encapsulation inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like, but is not particularly limited thereto. The encapsulation organic layer may include an acrylic-based inorganic layer, but is not particularly limited thereto.
Referring to
The first conductive layer ML1 may include a conductive material. The first conductive layer ML1 may have a lower resistance than those of the other layers (e.g., BL, ML2, and SL). The first conductive layer ML1 may have a resistance of 0.5Ω or lower. For example, the first conductive layer ML1 may include aluminum (Al), but is not limited thereto.
The conductivity of the first conductive layer ML1 may determine or substantially determine the conductivity of the conductive pattern G1. In other words, as the resistance of a material composing the first conductive material ML1 is lowered, the conductive pattern G1 having lower resistance characteristics may be provided. According to one or more embodiments of the present disclosure, through the low resistance characteristics of the conductive pattern G1, the display panel 100 (e.g., see
The second conductive layer ML2 includes a second material. The second material may be conductive. The second material may be different from the first material. The second material may have a higher rigidity than that of the first material. The second conductive layer ML2 may block an etching gas from contacting the first conductive layer ML1 in a dry etching process for providing a contact hole (e.g., CH1 in
The first conductive layer ML1 may have a first thickness d1. The second conductive layer ML2 may have a second thickness d2. The second thickness d2 may be thinner than the first thickness d1. The first thickness d1 may vary according to the resistance desired in the conductive pattern G1. The larger the first thickness d1, the smaller the resistance of the first conductive layer ML1. For example, when the first conductive layer ML1 includes aluminum, the first conductive layer ML1 may have a surface resistance of about 0.13 (ohm/sq) in a case where the first thickness d1 is about 2500 Å, and may have a surface resistance of about 0.08 (ohm/sq) in a case where the first thickness d1 is about 3500 Å.
An intermediate layer MM is disposed between the first conductive layer ML1 and the second conductive layer ML2. The intermediate layer MM may directly contact the bottom surface of the second conductive layer ML2. In addition, in the present embodiment, the boundary between the intermediate layer MM and the second conductive layer ML2 is shown as a straight line, but the present disclosure is not limited thereto. The boundary between the intermediate layer MM and the second conductive layer ML2 may appear to be indistinct from each other on a cross section (e.g., in a cross-sectional view).
During heat treatment, the second conductive layer ML2 may diffuse for a material composing the first conductive layer ML1. The intermediate layer MM may be provided by diffusion of the second conductive layer ML2. Accordingly, the intermediate layer MM may include the first material composing the first conductive layer ML1, and the second material composing the second conductive material. The intermediate layer MM may include a third material that may be an alloy of the first material and the second material. For example, the intermediate layer MM may include an alloy of a metal composing the first conductive layer ML1 and a metal composing the second conductive layer ML2. In other words, the intermediate layer MM may include an aluminum and titanium alloy (e.g., an AITi alloy), but is not limited thereto.
The intermediate layer MM may have a third thickness d3. The third thickness d3 may be determined or substantially determined by the position of the blocking layer BL. During the heat treatment, the intermediate layer MM may be provided while a material composing the second conductive layer ML2 diffuses to the blocking layer BL. In other words, the third thickness d3 may be determined by a separation distance from the second conductive layer ML2 to the blocking layer BL, which will be described in more detail below. The third thickness d3 may be a factor for increasing the resistance of the conductive pattern G1, and may be designed to be smaller than at least the first thickness d1. Accordingly, the influence of the intermediate layer MM to the conductivity of the conductive pattern G1 may be reduced.
The blocking layer BL is disposed between the first conductive layer ML1 and the intermediate layer MM. Although shown as directly contacting the first conductive layer ML1 and the intermediate layer MM, the blocking layer BL only needs to be positioned between the first conductive layer ML1 and the intermediate layer MM, and is not limited to any particular embodiment.
The blocking layer BL may include a suitable material having a small change due to heat. For example, the blocking layer BL may include a stable material, the physical characteristics of which, such as the crystal structure, do not change at a temperature of about 600 degrees or lower. The blocking layer BL may include a nitride of the second material. For example, the blocking layer BL may include titanium nitride, but is not limited thereto.
The blocking layer BL has a fourth thickness d4. The fourth thickness may be relatively thinner than the first thickness d1 and/or the third thickness d3. For example, the fourth thickness d4 may be satisfactory to prevent or substantially prevent an extension of the intermediate layer MM to the first conductive layer ML1. For example, the fourth thickness d4 may be several hundreds A, for example, such as about 100 Å to about 1000 Å, but is not limited thereto.
The shielding layer SL may be disposed on the second conductive layer ML2. The shielding layer SL may be the uppermost layer of the conductive pattern G1. The shielding layer SL may include a material having a higher rigidity than that of the first conductive layer ML1. The shielding layer SL may protect the first conductive layer ML1 and/or the second conductive layer ML2 in dry etching processes. Accordingly, the shielding layer SL may include a material having a relatively higher anti-corrosiveness against a fluorine-based etching gas.
In addition, the shielding layer SL may have a lower light transmittance than that of the second conductive layer ML2. According to one or more embodiments of the present disclosure, when the conductive pattern G1 includes the shielding layer, the possibility of detecting a pseudo defect may be reduced in an optical inspection where the pseudo defect may be generated due to the surfaces of the layers ML1, ML2, BL, and MM disposed under the shielding layer SL being uneven. In other words, the shielding layer may improve the possibility of detecting the pseudo defect when the pseudo defect occurs. Accordingly, the detection process may be rapidly completed, and the reliability of the detection result may be improved.
The shielding layer SL may be provided with a suitable material, the transmittance of which changes through heat treatment (e.g., prescribed or predetermined heat treatment). For example, the shielding layer SL may include amorphous carbon. The amorphous carbon in an optically transparent state (e.g., soft-amorphous carbon) may be heat-treated to be in a transmittance-reduced state (e.g., hard-amorphous carbon). The hard-amorphous carbon has a high anti-corrosiveness against the fluorine-based gas to protect the first conductive layer ML1 in the dry etching process, which will be described in more detail below.
Referring to
While
Referring to
Referring to
The semiconductor layer SCL is disposed on the base substrate BS. The semiconductor layer SCL may be provided by depositing and patterning a semiconductor material. The semiconductor layer SCL may include silicon. The semiconductor layer SCL may include amorphous silicon (a-Si). In the present embodiment, the semiconductor layer SCL may correspond to the semiconductor pattern of the first transistor T1 shown in
The insulation layer INS is disposed on the base substrate BS to cover the semiconductor layer SCL. The insulation layer INS may be provided by depositing or coating an insulation material. In the present embodiment, the insulation layer INS may correspond to the first insulation layer 10 shown in
The first layer MLL1 is disposed on the insulation layer INS. The first layer MLL1 may include a conductive material. The first layer MLL1 may include a low resistive material. For example, the first layer MLL1 may include a material having a low resistance of 0.5 ohm or lower, for example, such as aluminum, but the present disclosure is not limited thereto.
The second layer BLL is disposed on the first layer MLL1. The second layer BLL may have a smaller thickness than that of the first layer MLL1. The second layer BLL may include titanium nitride, but is not limited thereto.
The third layer MML is disposed on the second layer BLL. The third layer MML may include the same material as that of the first layer MLL1. For example, the third layer MML may include aluminum, but is not limited thereto.
Then, the fourth layer MLL2 is provided. The fourth layer MLL2 may be provided by contacting the third layer MML. The fourth layer MLL2 may be provided by depositing or coating a metal. The fourth layer MLL2 may include a material having a higher rigidity than that of the first layer MLL1. For example, the fourth layer MLL2 may include titanium, but is not limited thereto.
Then, the fifth layer SLL is provided on the fourth layer MLL2. In the present embodiment, the fifth layer SLL may be provided by depositing or coating a soft-amorphous carbon that has a light transmittance of about 90% or higher.
Referring to
Referring to
When the first heat treatment HT1 is applied to the first pattern PT1, the untreated intermediate layer MMa may change to the intermediate layer MM. The untreated intermediate layer MMa may have the same material as that of the first conductive layer ML1, and may be provided in the same or substantially the same manner to be in the same or substantially same state as that of the first conductive layer ML1. In other words, the intermediate layer MM may be the result of the untreated intermediate layer MMa that is changed by the first heat treatment HT1.
When the first heat treatment HT1 is performed, a portion of the second conductive layer ML2 may diffuse to the untreated intermediated layer MMa. Accordingly, an alloy of the metal constituting the second conductive layer ML2 and a metal constituting the untreated intermediate layer MMa may be provided. Accordingly, the intermediate layer MM includes the alloy.
When the untreated intermediate layer MMa includes aluminum, and the second conductive layer ML2 includes titanium, diffusion coefficients of the titanium for aluminum may exponentially increase over temperature. In other words, a diffusion speed of the second conductive layer ML2 for the untreated intermediate layer MMa may increase, as the temperature for the first heat treatment HT1 becomes higher. In the present embodiment, the first heat treatment HT1 may continue for 30 minutes at about 460 degrees, but the present disclosure is not limited thereto.
The diffusion of the second conductive layer ML2 through the untreated intermediate layer MMa may be blocked by the blocking layer BL. The blocking layer BL blocks the diffusion of the second conductive layer ML2 from extending to the first conductive layer ML1. The first conductive layer ML1 having the same material as that of the untreated intermediate layer MMa may not be influenced by the second conductive layer ML2 due to the blocking layer BL, even when the first heat treatment HT1 is performed. Accordingly, the first conductive layer ML1 may be stably heat-treated in the first heat treatment HT1.
According to one or more embodiments of the present disclosure, because the diffusion of the second conductive layer ML2 through the untreated intermediate layer MMa is blocked by the blocking layer BL, an area in which the intermediate layer MM is provided may be easily controlled through the position of the blocking layer BL. In addition, because the rear surface of the untreated intermediate layer MMa is the top surface of the blocking layer BL, the boundary of the diffusion area may be evenly set by the blocking layer BL in the cross section (e.g., in a cross-sectional view).
When the first heat treatment HT1 is performed, the untreated shielding layer SLL may change to the shielding layer SL. As described above, the untreated shielding layer SLL may include a suitable material such as a soft-amorphous carbon, and the transmittance of the material may change according to the first heat treatment HT1.
The soft-amorphous carbon has a light transmittance of about 90% with respect to light of about 550 nm. When heat-treated, the soft-amorphous carbon may change to a state where the light transmittance is reduced, such as a state of a hard-amorphous carbon, due to an increase of SP2 fractions. In other words, the untreated shielding layer SLL may include the soft-amorphous carbon, and the resulting shielding layer SL may include the hard-amorphous carbon.
Referring to
Referring to
The second pattern PT2 according to one or more embodiments of the present disclosure may include the intermediate layer MM contacting the second conductive layer ML2. The stress between the intermediate layer MM and the second conductive layer ML2 may decrease in comparison to the stress between the untreated intermediated layer MMa and the second conductive layer ML2. As the untreated intermediate layer MMa changes to the intermediate layer MM, the stress with the second conductive layer ML2 may decrease. When a line stress is high, a thermal void may be generated by the heat treatment. In an embodiment, the second pattern PT2 may include the intermediate layer MM, and thus, the void may not be generated during the second heat treatment HT2. Accordingly, a fault such as a cut line of the second pattern PT2, or a cut line of the additional layer ALD, may be prevented or substantially prevented from occurring.
In addition, in the second pattern PT2 according to one or more embodiments of the present disclosure, an area in which the second semiconductor layer ML2 diffuses may be easily controlled by including the blocking layer BL. Accordingly, the intermediate layer MM having a relatively high resistance may be prevented or substantially prevented from widely diffusing, and thus, the intermediate layer MM may be easily and stably controlled. In addition, the thickness of the intermediate layer MM may be uniformly or substantially uniformly controlled through the blocking layer BL. Accordingly, the second pattern PT2 may have a uniform or substantially uniform resistance.
In addition, the second pattern PT2 according to one or more embodiments of the present disclosure may include the shielding layer SL. As described above, the light transmittance of the shielding layer SL may be degraded. Accordingly, results of an optical inspection performed on the layers disposed under the shielding layer SL may not be influenced by the shielding layer SL.
Referring to
The first pattern PT1 may further include the blocking layer BL and the untreated shielding layer SLa, in comparison to the first comparison pattern PTC1. The first pattern PT1 may have a structure in which the blocking layer BL is further inserted into a portion of the thickness of the first metal layer ML of the first comparison pattern PTC1, and the untreated shielding layer SLa on the second metal layer CL of the first comparison pattern PTC1 to cover the second metal layer CL.
Referring to
In the second comparison pattern PTC2, the alloy layer ML-A is provided through the heat treatment, and accordingly, the line stress, which may be generated between the first metal layer ML and the second metal layer CL, may be reduced. When the line stress is high, a thermal void may be generated during the heat treatment, such as the activation process, and such a void may induce a fault, such as a cut line of the conductive pattern. The alloy layer ML-A of the second comparison pattern PTC2 may reduce such a thermal defect to improve the process reliability.
However, in the second comparison pattern PTC2, the boundary BD between the alloy layer ML-A and the first metal layer ML may not be even in the cross section (e.g., in a cross-sectional view). Because the alloy layer ML-A is provided while the second metal layer CL gradually diffuses from a top side of the first metal layer ML, it may be difficult to control the evenness in the cross section. The unevenness boundary BD may be detected as a defect during a later optical inspection. Such a pseudo defect may make it difficult to detect an actual defect, and be apt to lower the reliability of the optical inspection.
Referring to
In addition, by further including the shielding layer SL, the second pattern PT2 may stably protect the first conductive layer ML1 from an etching gas during dry etching processes for providing a contact hole later.
According to one or more embodiments of the present disclosure, the resistance of the lines may be reduced to improve the display characteristics of the display panel, and thus, a display panel having high resolution may be provided. Further, according to one or more embodiments of the present disclosure, power consumption of the display panel may also be reduced.
In addition, according to one or more embodiments of the present disclosure, a defect in the signal lines may be reduced to enhance the process reliability of the display panel.
Although some embodiments have been described, those skilled in the art will readily appreciate that various modifications are possible in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless otherwise described. Thus, as would be apparent to one of ordinary skill in the art, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments, as well as other example embodiments, are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims, and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0150620 | Nov 2022 | KR | national |
