Patent Application
20240136369
This application claims the benefit of priority to Japanese Patent Application Number 2022-168440 filed on Oct. 20, 2022. The entire contents of the above-identified application are hereby incorporated by reference.
The disclosure relates to a display panel, a defect correction method for a display panel, and a manufacturing method for a display panel.
An active matrix display panel including a thin film transistor (TFT) is used in display devices for various applications, such as mobile terminal and television applications.
Frame narrowing of an active matrix display panel is required from the viewpoint of reducing manufacturing costs and from the viewpoint of designability and functionality. By using a gate driver monolithic (GDM) technique in which a gate drive circuit (also referred to as a “gate driver”) is integrally formed on a TFT substrate, it is possible to reduce the cost for driver mounting and narrow the frame as compared to a case in which the gate drive circuit is mounted on the TFT substrate using chip on film (COF), chip on glass (COG), or the like. This GDM technique is sometimes referred to as gate on array (GOA). For example, WO 2011/104945 discloses a display device to which the GDM technique is applied.
The gate drive circuit includes a shift register including a plurality of stages corresponding to a plurality of pixel rows included in the display device. An output of each stage of the shift register is connected to a gate bus line (scanning wiring line) associated with each pixel row, and a scanning signal is supplied to the gate bus line. To improve an operation stability of the shift register, a dummy stage which does not contribute to display is sometimes further provided, and a dummy scanning line having the same wiring line resistance as that of the gate bus line is connected to the dummy stage (for example, JP 2002-214643 and US 2007/001,987).
Improvement of the manufacturing yield of a display device to which a GDM technique is applied is in demand. An object of the disclosure is to provide a display panel capable of suppressing a decrease in manufacturing yield, a defect correction method for such a display panel, and a manufacturing method for a display panel that uses the defect correction method.
According to embodiments of the disclosure, solutions described in the following items are provided.
A display panel includes a plurality of pixels arrayed in a matrix shape including a plurality of pixel rows and a plurality of pixel columns, a display region defined by the plurality of pixels, a peripheral region other than the display region, a gate drive circuit provided in the peripheral region and including a shift register including a plurality of stages and a dummy stage, the plurality of stages being respectively associated with the plurality of pixel rows, and a dummy capacitance portion provided in the peripheral region. The dummy capacitance portion includes a plurality of capacitance elements connected in parallel and connected to the dummy stage. Each of the plurality of capacitance elements includes a first capacitance electrode, a second capacitance electrode, and a dielectric layer positioned between the first capacitance electrode and the second capacitance electrode. The dummy capacitance portion further includes at least one first connection portion with two ends respectively connected to the first capacitance electrode of any one of the plurality of capacitance elements and to the first capacitance electrode of any other one of the plurality of capacitance elements.
In the display panel according to item 1, the dummy capacitance portion includes, for each of the first capacitance electrodes of the plurality of capacitance elements, two or more electrically conductive paths each extending from an input end to each of the first capacitance electrodes of the plurality of capacitance elements, the input end being configured to input a signal for applying a potential to the first capacitance electrode.
In the display panel according to item 1 or 2, the at least one first connection portion includes a plurality of first connection portions, the first capacitance electrode of each of the plurality of capacitance elements is connected to one end of each of any two or more of the plurality of first connection portions, and the other end of each of the any two or more of the plurality of first connection portions is connected to the first capacitance electrode of a different capacitance element among the plurality of capacitance elements, and the plurality of capacitance elements include two or more capacitance elements each including the first capacitance electrode connected to an input end without passing through the first capacitance electrode of any of the plurality of capacitance elements, the input end being configured to input a signal for applying a potential to the first capacitance electrode.
In the display panel according to any one of items 1 to 3, the second capacitance electrode is provided in common to the plurality of capacitance elements and includes at least one first opening overlapping the at least one first connection portion.
In the display panel according to any one of items 1 to 3, the dummy capacitance portion further includes at least one second connection portion with two ends respectively connected to the second capacitance electrode of any one of the plurality of capacitance elements and to the second capacitance electrode of any other one of the plurality of capacitance elements.
In the display panel according to item 5, the at least one second connection portion does not overlap the at least one first connection portion.
In the display panel according to item 5 or 6, the dummy capacitance portion includes, for each of the second capacitance electrodes of the plurality of capacitance elements, two or more electrically conductive paths each extending from an input end to each of the second capacitance electrodes of the plurality of capacitance elements, the input end being configured to input a signal for applying a potential to the second capacitance electrode.
In the display panel according to any one of items 5 to 7, the at least one second connection portion includes a plurality of second connection portions, the second capacitance electrode of each of the plurality of capacitance elements is connected to one end of each of any two or more of the plurality of second connection portions, and the other end of each of the any two or more of the plurality of second connection portions is connected to the second capacitance electrode of a different capacitance element among the plurality of capacitance elements, and the plurality of capacitance elements include two or more capacitance elements each including the second capacitance electrode connected to an input end without passing through the second capacitance electrode of any of the plurality of capacitance elements, the input end being configured to input a signal for applying a potential to the second capacitance electrode.
In the display panel according to any one of items 5 to 8, the dummy capacitance portion further includes a conductive layer facing each of the first capacitance electrodes of the plurality of capacitance elements with an insulating layer interposed therebetween, positioned on a side of the first capacitance electrodes opposite to the second capacitance electrodes, and electrically connected to the first capacitance electrodes. The conductive layer includes at least one second opening overlapping the at least one first connection portion and the at least one second connection portion.
In the display panel according to item 9, the conductive layer is formed of a transparent conductive material.
In the display panel according to item 9 or 10, the conductive layer is formed of the same conductive film as the pixel electrode provided to each of the plurality of pixels.
In the display panel according to any one of items 1 to 11, the first capacitance electrode is supplied with one signal among a signal for applying a low-level potential and a scanning signal for selecting any one of the plurality of pixel rows, and the second capacitance electrode is supplied with the other signal among the signal for applying a low-level potential and the scanning signal for selecting any one of the plurality of pixel rows.
The display panel according to any one of items 1 to 12 includes a substrate, a gate metal layer supported by the substrate, the dielectric layer covering the gate metal layer, and a source metal layer formed on the dielectric layer. Each of the first capacitance electrodes is included in one layer among the gate metal layer and the source metal layer, and each of the second capacitance electrodes is included in the other layer among the gate metal layer and the source metal layer.
A defect correction method for the display panel according to any one of items 1 to 13 includes, when a dielectric breakdown occurs in any one of the plurality of capacitance elements, disconnecting the first connection portion connected at one end to the first capacitance electrode of the capacitance element where the dielectric breakdown occurred.
A defect correction method for the display panel according to item 4 includes, when a dielectric breakdown occurs in any one of the plurality of capacitance elements, disconnecting a portion of the first connection portion connected at one end to the first capacitance electrode of the capacitance element where the dielectric breakdown occurred, the portion overlapping the first opening.
A defect correction method for the display panel according to anyone of item 5 to 8 includes, when a dielectric breakdown occurs in any one of the plurality of capacitance elements, disconnecting the first connection portion connected at one end to the first capacitance electrode of the capacitance element where the dielectric breakdown occurred, or disconnecting the second connection portion connected at one end to the second capacitance electrode of the capacitance element where the dielectric breakdown occurred.
A defect correction method for the display panel according to anyone of items 5 to 8 includes, when a dielectric breakdown occurs in any two of the plurality of capacitance elements, disconnecting the first connection portion connected at one end to the first capacitance electrode of one of the two capacitance elements where the dielectric breakdown occurred, and disconnecting the second connection portion connected at one end to the second capacitance electrode of the other of the two capacitance elements where the dielectric breakdown occurred.
A defect correction method for the display panel according to any one of items 9 to 11 includes, when a dielectric breakdown occurs in any one of the plurality of capacitance elements, disconnecting the first connection portion connected at one end to the first capacitance electrode of the capacitance element where the dielectric breakdown occurred.
A manufacturing method for a display panel includes correcting a defect of the display panel by the defect correction method according to any one of items 14 to 18.
According to an embodiment of the disclosure, a display panel that suppresses a decrease in manufacturing yield, a defect correction method for such a display panel, and a manufacturing method for a display panel that uses the defect correction method are provided.
The disclosure will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
Hereinafter, embodiments of the disclosure will be described with reference to the accompanying drawings. Note that, although a liquid crystal display panel will be described below as an example of a display panel according to an embodiment of the disclosure, the disclosure is not limited to the following embodiment and can be applied to an active matrix display panel of an organic electroluminescent (EL) display device, for example. In the following drawings, constituent elements having substantially the same functions may be denoted by common reference signs, and description thereof may be omitted.
A liquid crystal display panel 1000a and a liquid crystal display device 1100a including the liquid crystal display panel 1000a (hereinafter also referred to as “display panel 1000a” and “display device 1100a”) according to the present embodiment will be described with reference to
As illustrated in
In this example, a gate bus line GL is associated with each of the plurality of pixel rows, and a source bus line SL is associated with each of the plurality of pixel columns. The TFT 1 of each pixel P is supplied with a gate signal from the corresponding gate bus line GL, and is supplied with a source signal from the corresponding source bus line SL. The pixel rows may be referred to as a first row, a second row, . . . , and an rx-th row in order from the top, and the gate bus line associated with the r-th pixel row (1≤r≤rx) may be referred to as a gate bus line GL (r) (see
The display panel 1000a includes a gate drive circuit GD. Herein, the gate drive circuit GD is integrally formed on the TFT substrate 101 (gate driver monolithic). The gate drive circuit GD is provided in the first peripheral region NA1 of the display panel 1000a and includes a shift register 110 including a plurality of stages (also referred to as “drive stages”) respectively associated with the plurality of pixel rows. Outputs of each drive stage of the shift register 110 are connected to the gate bus lines GL respectively associated with the plurality of pixel rows. Typically, the shift register 110 includes rx drive stages and, given that the first stage, the second stage, . . . , and the rx-th stage are arranged in this order from the top, the output of the r-th stage (1≤r≤rx) is connected to the gate bus line GL (r). In addition to the rx drive stages, the shift register 110 further includes one or a plurality of dummy stages adjacent to the rx drive stages in the column direction and not contributing to display. In this example, a plurality of the dummy stages are provided on both upper and lower sides of the rx drive stages. The dummy stages provided on the upper side of the drive stages (that is, the stage before the first stage of the drive stages) are referred to as a u1 stage and a u2 stage in this order from the top, and the dummy stages provided on the lower side of the drive stages (that is, the stage after the last stage of the drive stages) are referred to as a d1 stage and a d2 stage in this order from the top. The shift register 110 is configured by cascade-connecting a plurality of unit circuits QC. Each stage (each drive stage and dummy stage) of the shift register 110 is configured by each unit circuit QC. The unit circuit QC constituting each stage of the shift register 110 includes at least one TFT. The drive stage of the r-th stage (1≤r≤rx) is constituted by the unit circuit QC (r), and the dummy stages of the u1 stage, the u2 stage, the d1 stage, and the d2 stage are constituted by the unit circuits QC (u1), QC (u2), QC (d1), QC (d2), respectively. The number of dummy stages included in the shift register 110 is not limited to the illustrated example, and may be changed as appropriate to a form in which at least one dummy stage is provided on the upper side of the drive stages (a stage before the first stage of the drive stages) and/or on the lower side of the drive stages (a stage after the last stage of the drive stages).
A plurality of capacitance elements 40 connected in parallel and included in a dummy capacitance portion CA provided in the peripheral region NA are respectively connected to, among the dummy stages of the shift register 110, the dummy stages provided on the upper side of the drive stages. Further, herein, a dummy bus line dL is connected to, among the dummy stages of the shift register 110, each of the dummy stages provided on the lower side of the drive stages. The dummy bus line dL has, for example, a wiring line resistance equivalent to that of the gate bus line GL. By connecting the dummy capacitance portion CA or the dummy bus line dL to each of the dummy stages, a capacitance equivalent to a parasitic capacitance formed by the gate bus line GL is connected to each of the dummy stages. A load of the unit circuit QC of the dummy stage is designed to be substantially equal to a load of the unit circuit QC of the drive stage. The load of the unit circuit QC of each stage of the shift register 110 is determined by the capacitance and the resistance of the wiring line connected to the unit circuit QC.
As illustrated in
The dummy capacitance portion CA further includes a plurality of first connection portions 46 (herein, four first connection portions 46). Two ends of each first connection portion 46 are respectively connected to the first capacitance electrode CE1s of any one of the four capacitance elements 40 and to the first capacitance electrode CE1s of any other one of the four capacitance elements 40. Herein, the two ends of each first connection portion 46 are respectively connected to the first capacitance electrodes CE1s of two adjacent capacitance elements 40. The first capacitance electrodes CE1s and the first connection portions 46 are formed of, for example, the same conductive film as that of the source bus line SL (that is, are included in the source metal layer). The second capacitance electrode CE2g is provided in common to the plurality of capacitance elements 40. For example, the second capacitance electrode CE2g at least partially overlaps each of the first capacitance electrodes CE1s of the plurality of capacitance elements 40. The second capacitance electrode CE2g includes a plurality of openings CHa (herein, three openings CHa) each of which overlaps any one of the four first connection portions 46 when viewed from a normal direction of the display panel 1000a (
A defect correction method for the display panel 1000a will now be described with reference to
The display panel 1000a, not requiring provision of a dummy bus line for connection to at least a portion of the dummy stage of the shift register 110 in the peripheral region, can contribute to frame narrowing.
Herein, the source metal layer is disposed on the gate metal layer. That is, the TFT substrate 101 of the display panel 1000a includes a substrate, a gate metal layer supported by the substrate, a dielectric layer (gate insulating layer) covering the gate metal layer, and a source metal layer formed on the dielectric layer. Although an example in which the first capacitance electrodes CE1s and the first connection portions 46 are included in the source metal layer, and the second capacitance electrode CE2g is included in the gate metal layer has been described herein, embodiments of the disclosure are not limited to this example. The first capacitance electrodes CE1s and the first connection portions 46 may be included in the gate metal layer, and the second capacitance electrode CE2g may be included in the source metal layer. In this case, for example, the scanning signal Gout supplied to the gate bus lines GL is supplied to the first capacitance electrodes CE1s and, for example, the signal for supplying the low-level potential VSS is supplied to the second capacitance electrode CE2g. Further, in such a defect correction method for a display panel, the portions of the first connection portions 46 (gate metal layer) overlapping the openings CHa of the second capacitance electrode CE2g (source metal layer) can be disconnected from above the gate insulating layer. From the viewpoint of reducing manufacturing costs, preferably the first capacitance electrodes CE1s are included in one of the gate metal layer and the source metal layer, and the second capacitance electrode CE2g is included in the other of the gate metal layer and the source metal layer.
Structures of the display panel 1000a and the display device 1100a will now be described in more detail.
As illustrated in
In the example of
The outer trunk line 122 and the inner trunk line 124 are for supplying, for example, a signal for applying a low-level potential (for example, VSS=−7 V) to the plurality of stages of the shift register 110. A signal for applying a fixed potential (for example, a signal for applying the low-level potential VSS) is supplied from the control circuit CNTL to the outer trunk line 122 connected via the outer trunk line terminal. With the outer trunk line 122 and the inner trunk line 124 being electrically connected via the branch wiring lines 140, and the inner trunk line 124 and the input (input terminal) of each stage of the shift register 110 being electrically connected via the wiring line 152, a signal for applying the low-level potential VSS is supplied to the input of each stage of the shift register 110.
The display panel 1000a may further include an additional trunk line 121 provided in the first peripheral region NA1, extending in the column direction, and supplying another common signal to the plurality of stages of the shift register 110. In this case, signals for applying two kinds of low-level potentials (for example, VSS1=−12 V and VSS2=−7 V) are supplied from the control circuit CNTL. The outer trunk line 122 and the inner trunk line 124 supply signals for applying the low-level potential VSS2 to the plurality of stages of the shift register 110, and the trunk line 121 supplies a signal for applying the low-level potential VSS1 to the plurality of stages of the shift register 110.
Note that the outer trunk line 122 and the inner trunk line 124 may be for supplying, for example, a signal VD for applying a high-level potential (which may be different from Vgh) to the plurality of stages of the shift register 110. The signal VD for applying a high-level potential may be supplied from the control circuit CNTL to the outer trunk line 122 connected via the outer trunk line terminal.
In this example, the inner trunk line 124 is disposed farther from the display region AA than the shift register 110, and the outer trunk line 122 is disposed farther from the display region AA than the inner trunk line 124. The eight clock trunk lines CKL1 to CKL8 are provided between the outer trunk line 122 and the inner trunk line 124. A width of the outer trunk line 122 in the row direction is typically larger than a width of the inner trunk line 124 in the row direction.
The display panel 1000a further includes a first trunk line 132 and a second trunk line 134 for supplying signals to each of the plurality of stages of the shift register 110. The first trunk line 132 and the second trunk line 134 are used to supply a clear signal (reset signal) to each stage of the shift register 110, for example. The gate start pulse signal GSP and/or the gate end pulse signal GEP may be used as the clear signal. The first trunk line 132 is provided in the first peripheral region NA1 and supplies a common signal to one or a plurality of first type stages included in the plurality of stages. The second trunk line 134 is provided between the first trunk line 132 and the display region AA, and supplies another common signal to one or a plurality of second type stages included in the plurality of stages. The first trunk line 132 and the second trunk line 134 extend in the column direction. The first trunk line 132 and the second trunk line 134 are electrically independent from each other, making it possible to supply signals different from each other to the first type stages and the second type stages.
A display panel 1000b and a defect correction method thereof according to the present embodiment will now be described with reference to
In the display panel 1000a, the second capacitance electrode CE2g is provided in common to the plurality of capacitance elements 40, but in the display panel 1000b, four second capacitance electrodes CE2g are provided correspondingly to the four capacitance elements 40. In the display panel 1000b, the dummy capacitance portion CA further includes a plurality of second connection portions 42 (herein, four second connection portions 42). Two ends of each second connection portion 42 are respectively connected to the second capacitance electrode CE2g of any one of the four capacitance elements 40 and to the second capacitance electrode CE2g of any other one of the four capacitance elements 40. Here, the two ends of each second connection portion 42 are connected to the second capacitance electrodes CE2g of two adjacent capacitance elements 40. Each of the second connection portions 42 does not overlap any of the first connection portions 46 when viewed from a normal direction of the display panel 1000b (
An example of the defect correction method for the display panel 1000b will now be described with reference to
Another example of the defect correction method for the display panel 1000b will be described with reference to
The display panel 1000b satisfies (1) and (2) below, making it possible to correct a defect when a dielectric breakdown occurs in any two capacitance elements 40 of the plurality of (herein, four) capacitance elements 40.
(1) For each of the four first capacitance electrodes CE1s, there are two or more electrically conductive paths each extending from an input end (tip of an arrow of “VSS” in the drawing), which is configured to input a signal for applying a potential to the first capacitance electrode CE1s, to each of the four first capacitance electrodes CE1s. Here, the “path” can also include other first capacitance electrodes CE1s in addition to the one or plurality of first connection portions 46.
(2) For each of the four second capacitance electrodes CE2g, there are two or more electrically conductive paths each extending from an input end (tip of an arrow of “Gout” in the drawing), which is configured to input a signal for applying a potential to the second capacitance electrode CE2g, to each of the four second capacitance electrodes CE2g. Here, the “path” can include other second capacitance electrodes CE2g in addition to the one or plurality of second connection portions 42.
Preferably, both (1) and (2) described above are satisfied, but only one may be satisfied. To satisfy (1) described above, preferably (3a) and (3b) below are satisfied and, to satisfy (2) described above, preferably (4a) and (4b) below are satisfied.
(3a) The first capacitance electrode CE1s of each of the four capacitance elements 40 is connected to one end of each of any two or more of the four first connection portions 46, and the other end of each of the any two or more of the four first connection portions 46 is connected to the first capacitance electrode CE1s of a different capacitance element among the four capacitance elements 40. In other words, the first capacitance electrode CE1s of each of the four capacitance elements 40 is connected to one end of two or more first connection portions 46, and the other ends of the two or more first connection portions 46 are connected to the first capacitance electrodes CE1s of the capacitance elements 40 different from each other.
(3b) The four capacitance elements 40 include two or more capacitance elements each including the first capacitance electrode CE1s connected to an input end (tip of an arrow of “VSS” in the drawing) without passing through the first capacitance electrode CE1s of another capacitance element, the input end being configured to input a signal for applying a potential to the first capacitance electrode CE1s. In the examples of
(4a) The second capacitance electrode CE2g of each of the four capacitance elements 40 is connected to one end of each of any two or more of the four second connection portions 42, and the other end of each of the any two or more of the four second connection portions 42 is connected to the second capacitance electrode CE2g of a different capacitance element among the four capacitance elements 40. In other words, the second capacitance electrode CE2g of each of the four capacitance elements 40 is connected to one end of two or more second connection portions 42, and the other ends of the two or more second connection portions 42 are connected to the second capacitance electrodes CE2g of the capacitance elements 40 different from each other.
(4b) The four capacitance elements 40 include two or more capacitance elements each including the second capacitance electrode CE2g connected to an input end (tip of an arrow of “Gout” in the drawing) without passing through the second capacitance electrode CE2g of another capacitance element, the input end being configured to input a signal for applying a potential to the second capacitance electrode CE2g. In the examples of
A display panel 1000b1 and a defect correction method thereof according to a modified example of the present embodiment will now be described with reference to
The display panel 1000b1 differs from the display panel 1000b in including six capacitance elements 40 connected in parallel in the dummy capacitance portion CA. The display panel 1000b1 satisfies both (1) and (2) described above, making it possible to correct a defect when a dielectric breakdown occurs in any two capacitance elements 40 of the six capacitance elements 40 using a method similar to the defect correction method described with reference to
A display panel 1000c and a defect correction method thereof according to the present embodiment will now be described with reference to
The display panel 1000c differs from the display panel 1000b in that the dummy capacitance portion CA further includes an interlayer insulating layer 15 covering the plurality of capacitance elements 40, and a transparent conductive layer 16 formed on the interlayer insulating layer 15. The transparent conductive layer 16 is electrically connected to the first capacitance electrodes CE1s at a contact portion CHc. The transparent conductive layer 16 includes openings CHb overlapping the first connection portions 46 and the second connection portions 42 when viewed from a normal direction of the display panel 1000c (
The defect correction method for the display panel 1000c will now be described with reference to
Although an example in which the first capacitance electrodes CE1s and the first connection portions 46 are included in the source metal layer and the second capacitance electrodes CE2g are included in the gate metal layer, that is, an example in which the first capacitance electrodes CE1s are disposed on the second capacitance electrodes CE2g, has been described herein, the second capacitance electrodes CE2g may be disposed on the first capacitance electrodes CE1s. In this case, the conductive layer electrically connected to the first capacitance electrodes CE1s faces the first capacitance electrodes CE1s with the insulating layer interposed therebetween, and is positioned on a side of the first capacitance electrodes CE1s opposite to the second capacitance electrodes CE2g. That is, the conductive layer is positioned below the first capacitance electrodes CE1s with the insulating layer interposed therebetween. Even in such a case, the same effects as those of the display panel 1000c can be obtained.
The display panel according to the embodiments of the disclosure is widely applied to active matrix display panels such as a liquid crystal display panel and an organic EL display panel. When the display panel according to the embodiment of the disclosure is applied, the manufacturing yield of the active matrix display panel can be improved. The defect correction method for a display panel according to an embodiment of the disclosure may be applied to a manufacturing method for a display panel.
While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-168440 | Oct 2022 | JP | national |
