Patent Application
20120242722
The present invention relates to a display panel drive device for driving a display panel. In particular, the present invention relates to a display panel drive device for applying a drive pulse to each of data lines of a display panel according to an input video signal. Further, the present invention relates to a semiconductor integrated device in which the display panel drive device is disposed, and an image data acquisition method in the display panel drive device.
In a display panel of a flat plane type such as a liquid crystal display panel, scanning lines in the number of n (n is an integer greater than two) are arranged to extend in a horizontal direction of a two-dimensional screen. Further, signal lines in the number of m (m is an integer greater than two) are arranged to extend in a vertical direction of the two-dimensional screen. Further, the signal lines are arranged such that the signal lines cross the scanning lines. Electrodes corresponding to pixels are disposed at crossing points between the signal lines and the scanning lines.
Further, the display panel includes a signal driver for applying a voltage corresponding to a brightness level indicated with an input video signal to each of the signal lines. Patent Reference has disclosed a conventional signal driver. The conventional signal driver disclosed in Patent Reference includes a first latch group, a second latch group, a D/A converter, and an output amplifier.
In the conventional signal driver disclosed in Patent Reference, the first latch group is provided for correlating the input video signal to each of the signal lines in the number of m, and for sequentially capturing the input video signal formed of a series of display data per pixel. The second latch group is provided for capturing each of the display data in the number of m captured with the first latch group. The D/A converter is provided for separately converting each of data pieces captured with the second latch group to analog drive voltages in the number of m. The output amplifier is provided for applying the analog drive voltages in the number of m supplied from the D/A converter to each of the signal lines.
In the conventional signal driver disclosed in Patent Reference, it is preferred that the output amplifier possesses a high output current performance. When that the output amplifier possesses a high output current performance, it is possible to increase a length of the signal lines associated with an increase in a size and a pixel density of the display panel.
In the conventional signal driver disclosed in Patent Reference, when the output amplifier possesses a high output current performance, a large current tends to instantly flow into the signal lines when a value of each of the display data captured with the second latch group is switched from a low level state to a high level state, or from a high level state to a low level state. When a large current instantly flows into the signal lines, a large noise may be generated.
In the conventional signal driver disclosed in Patent Reference, in order to reduce such a large noise, it is proposed that each of latches constituting the second latch group is configured to capture the display data at a capture timing, and the capture timing is forcibly delayed by various delay amounts. Accordingly, it is possible to spread the capture timings over a specific period of time. As a result, it is possible to reduce an amount of an electric current flowing at the same time, thereby reducing the large noise. It is noted that when the delay amounts increase, it is possible to prolong an interval of the capture timings thus spread, thereby further effectively reducing the large noise.
Recently, the size and the pixel density of the display panel have been increased. With the increase in the size and the pixel density of the display panel, a clock signal with a higher frequency is applied to each of the latches constituting the first latch group and the second latch group in a shorter cycle. Accordingly, when the delay amount is increased to suppress the noise, the capture timing of the latch in the second latch group may be overlapped with the capture timing of the latch in the first latch group for capturing subsequent display data. If the two capture timings are overlapped, the display data may be erroneously captured, thereby causing an erroneous operation.
In view of the problems described above, an object of the present invention is to provide a display panel drive device capable of solving the problems of the conventional display panel drive device. A further object of the present invention is to provide a semiconductor integrated device in which the display panel drive device is disposed, and an image data acquisition method in the display panel drive device. In the present invention, it is possible to reduce the noise associated with the instant flow of the large current without the erroneous operation.
Further objects and advantages of the invention will be apparent from the following description of the invention.
In order to attain the objects described above, according to a first aspect of the present invention, a display panel drive device is configured to apply a drive pulse to each of a plurality of data lines formed in a display panel according to a video signal.
According to the first aspect of the present invention, the display panel drive device includes a latch portion and an output amplifier. The latch portion is provided for capturing each of pixel data pieces for one horizontal scan per each pixel at a timing different from each other according to the video signal, and for outputting each of the pixel data pieces as a captured pixel data piece. The output amplifier is provided for applying the drive pulse corresponding to a brightness level indicated with each of the captured pixel data pieces to each of the data lines of the display panel.
According to the first aspect of the present invention, the latch portion includes a first latch section, a delay circuit, and a second latch section. The first latch section is provided for capturing the pixel data pieces when a load clock signal is in a first level state, and for retaining the pixel data pieces captured when the load clock signal is in the first level state when the load clock signal is in a second level state. The delay circuit is provided for generating a delayed load clock signal through delaying the load clock signal. The second latch section is provided for capturing the pixel data pieces when the delayed load clock signal is in a first level state, and for retaining the pixel data pieces captured when the delayed load clock signal is in the first level state when the delayed load clock signal is in a second level state.
According to the first aspect of the present invention, it is configured that the delayed load clock signal is transited to the first level state after a first delay time after the load clock signal is transited from the second level state to the first level state. Further, it is configured that the delayed load clock signal is transited to the second level state after a second delay time after the load clock signal is transited from the first level state to the second level state, and the first delay time is longer than the second delay time.
According to a second aspect of the present invention, a semiconductor integrated device is configured to generate a drive pulse to be applied to each of a plurality of data lines formed in a display panel according to a video signal.
According to the second aspect of the present invention, the display panel drive device includes a latch portion and an output amplifier. The latch portion is provided for capturing each of pixel data pieces for one horizontal scan per each pixel at a timing different from each other according to the video signal, and for outputting each of the pixel data pieces as a captured pixel data piece. The output amplifier is provided for applying the drive pulse corresponding to a brightness level indicated with each of the captured pixel data pieces to each of the data lines of the display panel.
According to the second aspect of the present invention, the latch portion includes a first latch section, a delay circuit, and a second latch section. The first latch section is provided for capturing the pixel data pieces when a load clock signal is in a first level state, and for retaining the pixel data pieces captured when the load clock signal is in the first level state when the load clock signal is in a second level state. The delay circuit is provided for generating a delayed load clock signal through delaying the load clock signal. The second latch section is provided for capturing the pixel data pieces when the delayed load clock signal is in a first level state, and for retaining the pixel data pieces captured when the delayed load clock signal is in the first level state when the delayed load clock signal is in a second level state.
According to the second aspect of the present invention, it is configured that the delayed load clock signal is transited to the first level state after a first delay time after the load clock signal is transited from the second level state to the first level state. Further, it is configured that the delayed load clock signal is transited to the second level state after a second delay time after the load clock signal is transited from the first level state to the second level state, and the first delay time is longer than the second delay time.
According to a third aspect of the present invention, an image data acquisition method is provided for a display panel drive device. The display panel drive device is configured to capture each of pixel data pieces for one horizontal scan per each pixel at a timing different from each other according to a video signal, and to apply a drive pulse to each of a plurality of data lines of a display panel according to the pixel data pieces thus captured.
According to the third aspect of the present invention, the image data acquisition method includes the steps of setting a first delay time for shifting a start timing for capturing each of the pixel data pieces so that the start timings are shifted with each other; and setting a second delay time for shifting a complete timing for completing the capturing of each of the pixel data pieces so that the complete timings are shifted with each other. The first delay time and the second delay time are set so that the first delay time is longer than the second delay time.
In the present invention, a plurality of latch sections is provided for capturing each of the pixel data pieces for one horizontal scan per each pixel at the timing different from each other according to the video signal. Further, the drive pulse is applied to each of the data lines of the display panel according to the pixel data pieces thus captured. At this moment, the first delay time is set for shifting the start timing for capturing each of the pixel data pieces so that the start timings are shifted with each other; and the second delay time is set for shifting the complete timing for completing the capturing of each of the pixel data pieces so that the complete timings are shifted with each other. The first delay time and the second delay time are set so that the first delay time is longer than the second delay time.
Accordingly, even when the first delay time for shifting the start timing for capturing each of the pixel data pieces so that the start timings are shifted with each other is prolonged, it is possible to prevent a period of data acquisition time of each of the latch sections from being overlapped with a supply timing of the pixel data for a subsequent horizontal scan. Accordingly, it is possible to spread an electric current flowing into each of the data lines of the display panel with a sufficient delay time without causing an erroneous operation. As a result, it is possible to effectively reduce a noise.
Hereunder, preferred embodiments of the present invention will be explained with reference to the accompanying drawings.
In a display panel drive device of the present invention, it is configured such that a latch portion of the display panel drive device is provided for capturing pixel data pieces for one horizontal scan per each pixel according to a video signal, so that the display panel drive device applies a drive pulse to each of a plurality of data lines of a display panel according to each of the pixel data pieces thus captured. The latch portion is configured to capture the pixel data pieces through the following process.
According to the present invention, the latch portion includes a first latch section and a second latch section configured to capture the pixel data pieces during a period of time when a clock signal supplied to a clock input terminal is in a first level state, and to retain the pixel data pieces captured when the clock signal is in the first level state when the clock signal is in a second level state. Further, a load clock signal is supplied to the clock input terminal of the first latch section, and a delayed load clock signal is supplied to the clock input terminal of the first latch section. The delayed load clock signal is obtained through delaying the load clock signal.
Further, according to the present invention, it is configured that the delayed load clock is transited to the first level state after a first delay time after the load clock signal is transited from the second level state to the first level state. Further, it is configured that the delayed load clock is transited to the second level state after a second delay time after the load clock signal is transited from the first level state to the second level state, and the first delay time is longer than the second delay time.
A first embodiment of the present invention will be explained.
As shown in
In the embodiment, the display panel drive device includes a drive control unit 10 for generating a scanning control signal according to an input video signal, so that a scanning pulse is sequentially applied to each of the scanning lines S1 to Sn. Further, the display panel drive device includes a scanning driver 11 and a data driver 12. The drive control unit 10 is configured to supply the scanning control signal to the scanning driver 11.
In the embodiment, as shown in
More specifically, the drive control unit 10 is configured to divide the pixel data PD1 to PDm per one horizontal scanning line into a first pixel data series Q1 including the pixel data PD1 to PDm/2 and a second pixel data series Q2 including the pixel data PD(1+m/2) to PDm. Further, as shown in
In the embodiment, after the drive control unit 10 transmits all of the first pixel data series Q1 and the second pixel data series Q2 in a first half portion of the one horizontal scanning period, the drive control unit 10 supplies the load clock signal LC to the data driver 12 in a second half portion of the one horizontal scanning period. As shown in
In the embodiment, the display panel drive device includes the scanning driver 11 for generating the scanning pulse according to the scanning control signal supplied from the drive control unit 10, and for sequentially and selectively applying the scanning pulse to each of the scanning lines S1 to Sn of the display panel 20.
In the embodiment, the display panel drive device includes the scanning driver 11 for capturing the pixel data PD in the first pixel data series Q1 and the second pixel data series Q2 according to the various control signals (the capture start pulse signal ST, the delayed load clock signal LD, and the reference clock signal CLK) supplied from the drive control unit 10. Further, every time after the data driver 12 completely captures the pixel data PD1 to PDm for one horizontal scanning line, the data driver 12 is configured to generate the drive pulse corresponding to each of the brightness levels indicated with each of the pixel data PD1 to PDm, and to apply the drive pulse to each of the data lines D1 to Dm of the display panel 20.
In the embodiment, it should be noted that each of the scanning driver 11 and the data driver 12 is disposed in one single semiconductor chip or a plurality of semiconductor chips.
As shown in
Through the process described above, each of the D latches FF1 to FF(m/2) captures the first pixel data series Q1 at the timing of the clock signals CK1 to CK(m/2) supplied to each of the D latches FF1 to FF(m/2). Further, each of the D latches FF1 to FF(m/2) supplies the value of the pixel data thus captured as the pixel data A1 to A(m/2) to the second latch portion 123.
More specifically, for example, the D latch FF1 captures the pixel data PD1 in the first pixel data series Q1 at the timing of the clock signal CK1 as shown in
As shown in
Through the process described above, each of the D latches FF(m/2)+1 to FFm captures the second pixel data series Q2 at the timing of the clock signals CK1 to CK(m/2) supplied to each of the D latches FF(m/2)+1 to FFm. Further, each of the D latches FF(m/2)+1 to FFm supplies the value of the pixel data thus captured as the pixel data A(m/2)+1 to Am to the second latch portion 123.
More specifically, for example, the D latch FF(m/2)+1 captures the pixel data PD(m/2)+1 in the second pixel data series Q2 at the timing of the clock signal CK(m/2)+1 as shown in
With the configuration described above, the first latch portion 122 sequentially captures each of the pixel data PD1 to PDm for one horizontal scanning line supplied from the drive control unit 10 in series into the D latches FF1 to FFm in the number of m. Then, the first latch portion 122 supplies the pixel data PD1 to PDm as the pixel data A1 to Am to the first latch portion 122 at the later stage.
In the embodiment, the second latch portion 123 is configured to capture each of the pixel data A1 to Am according to lc as shown in
In the embodiment, the output amplifier 124 is configured to generate the drive pulse having a voltage corresponding to the brightness level of each of the pixel data B1 to Bm. Afterward, the output amplifier 124 is configured to supply the drive pulse to the data lines D1 to Dm of the display panel 20. It is noted that the output amplifier 124 is configured such that the capture timing of each of the D latches is shifted. Accordingly, the peak currents flowing into the data lines D1 to Dm of the display panel 20 are spread with respect to a period of time.
As shown in
In the embodiment, when the clock signal supplied to the clock input terminal of each of the D latches FL1 to FLm is in the state of the logic level “0”, each of the D latches FL1 to FLm is configured to retain the pixel data A1 to Am captured during a period of time when the clock signal is in the state of the logic level “1”. Afterward, each of the D latches FL1 to FLm is configured to supply the pixel data A1 to Am to the output amplifier 124 as the pixel data B1 to Bm.
More specifically, as shown in
As shown in
In the embodiment, the delay circuit DL3 is configured to supply the delayed load clock signal LD4 obtained through delaying the delayed load clock signal LD3 by a specific period of time as the clock signal to the clock input terminal of each of the D latches FL4 and FLm−3. Further, the delay circuit DL(m/2)−1 is configured to supply the delayed load clock signal LDm/2 obtained through delaying the delayed load clock signal LD(m/2)−1 by a specific period of time as the clock signal to the clock input terminal of each of the D latches FLm/2 and FL(m/2)+1.
As described above, in the embodiment, the delay circuit DLk (k is 1 to (m/2)−1) is configured to supply the delayed load clock signal LDk+1 obtained through delaying the delayed load clock signal LDk supplied to the clock input terminal of the D latch FLk at the kth location by a specific period of time as the clock signal to the clock input terminal of each of the D latches FLk+1 and FLm−(k−1).
In the embodiment, as shown in
In the embodiment, the and gate AN of the delay circuit DL1 is provided for obtaining a logic product of the load clock signal LC and the delayed clock signal obtained with the inverters IV1 and IV2 through delaying the load clock signal LC. Accordingly, the and gate AN of the delay circuit DL1 generates the logic product as the delayed load clock signal LD2.
Similarly, the inverter IV1 of each of the delay circuits DL2 to DL(m/2)−1 is provided for supplying an inverted clock signal having an inverted logic level of that of the delayed load clock signal LDk (k is 2 to (m/2)-1) to the inverter IV2. The inverter IV2 of each of the delay circuits DL2 to DL(m/2)−1 is provided for supplying a signal having an inverted logic level of that of the inverted clock signal to the and gate AN. Further, the and gate AN of each of the delay circuits DL2 to DL(m/2)−1 is provided for obtaining a logic product of the delayed load clock signal LDk and the delayed clock signal obtained with the inverters IV1 and IV2 through delaying the delayed load clock signal LDk. Accordingly, the and gate AN of the delay circuit DL1 generates the logic product as the delayed load clock signal LDk+1.
In the embodiment, as shown in
With the configuration described above, the delayed load clock signals LD2 to DLm/2 are obtained through delaying the load clock signal LC with different delay amounts. Afterward, the delayed load clock signals LD2 to DLm/2 are supplied to the clock input terminals of the D latches FL2 to FLm/2 and the D latches FL(m/2)−1 to FLm.
Accordingly, in the embodiment, with respect to the rising edge of the load clock signal LC, at which the load clock signal LC is switched from the state of the logic level “0” to the state of the logic level “1”, each of the delayed load clock signals LD2 to DLm/2 has the rising edge at the timing as shown in
For example, as shown in
Accordingly, the D latches FL2 to FLm of the second latch portion 123 are configured to capture the pixel data A1 to Am supplied from the first latch portion 122 at the different timings. Afterward, as shown in
As described above, when the D latches FL2 to FLm of the second latch portion 123 capture the pixel data A1 to Am, the value of the pixel data retained in each of the D latches FL2 to FLm of the second latch portion 123 may be transited from the low level state to the high level state (or vice versa). In the embodiment, as shown in
Accordingly, when the drive pulse corresponding to each of the pixel data B1 to Bm is applied to each of the data lines D2 to Dm of the display panel 20, it is possible to minimize the total current amount flowing into the data lines D2 to Dm. As a result, it is possible to reduce the noise associated with the concurrent flow of the current into the data lines D2 to Dm.
In the embodiment, it is noted that the delay circuit DLk of the second latch portion 123 shown in
Accordingly, in the embodiment, each of the load clock signal LC and the delayed load clock signals LD2 to LDm/2 have the rising edge, or the data capture start timing of each of the D latches FL, at the different timings. Further, as shown in
Accordingly, in the embodiment, as shown in
Accordingly, in the embodiment, with the second latch portion 123 shown in
A second embodiment of the present invention will be explained next with reference to
In the second embodiment, as shown in
In the second embodiment, when the second latch portion 123 has the configuration shown in
In the second embodiment, the variable delay element IVC of each of the delay circuits DL1 to DL(m/2)−1 is configured to delay the load clock signal LC or the delayed load clock signal LD supplied from the front stage with the delay amount specified with the delay amount specifying data DC supplied from the drive control unit 10. Further, the variable delay element IVC of each of the delay circuits DL1 to DL(m/2)−1 is configured to supply a signal with an inverted logic level to the inverter IV2 thereof.
Accordingly, in the second latch portion 123 shown in
In the second embodiment, the second latch portion 123 includes the D latches FL1 to FLm, and the pixel data PD is captured during a period of time only when the clock signal supplied to the clock input terminal has the logic level “1”. Alternatively, it may be configured such that the pixel data PD is captured during a period of time only when the clock signal supplied to the clock input terminal has the logic level “0”. In other word, it is suffice that the D latches FL1 to FLm are configured to be the level sensitive type D latches such that the pixel data PD is captured during a period of time only when the clock signal supplied to the clock input terminal has the first level state or the second level state.
In the second embodiment, similar to the configuration shown in
In other words, it is suffice that the data capture completion timings of the D latches FL1 to FLm be different by the delay amount smaller than the delay amount for shifting the data capture start timings of the D latches FL1 to FLm. More specifically, the delay circuits DL1 to DL(m/2)−1 are configured such that the delay time from when the load clock signal LC is transited from the logic level “0” to the logic level “1” to when the delayed load clock signal LD is transited to the logic level “1” becomes shorter than the delay time from when the load clock signal LC is transited from the logic level “1” to the logic level “0” to when the delayed load clock signal LD is transited to the logic level “0”.
In the second embodiment, the data lines D2 to Dm of the display panel 20 are divided into the two groups. Further, it is configured such that the drive pulse is applied to each of the data lines D of each group in the number of m/2 at the different timing. Alternatively, it may be configured such that the drive pulse is applied to each of all of the data lines D2 to Dm of the display panel 20 at the different timing.
Further, in the second embodiment, the data driver 12 includes the four modules such as the shift register 121, the first latch portion 122, the second latch portion 123, and the output amplifier 124, and the data driver 12 is formed of one single semiconductor chip or a plurality of semiconductor chips. Alternatively, each of the modules may be formed of a semiconductor chip. Alternatively, two or three of the four modules may be integrated and formed of a semiconductor chip.
Further, in the second embodiment, in the second latch portion 123 shown in
A third embodiment of the present invention will be explained next with reference to
In the third embodiment, the operation of the D latches FL1 to FLm, the operation of the delay circuits DL1 to DL(m/2)−1 and the operation of the second latch portion 123 are similar to those in the first embodiment shown in
In the third embodiment, the second latch portion 123 includes a first delay circuit group DUT1 and a second delay circuit group DUT2, and the load clock signal LC is directly supplied to the clock input terminal of each of the D latches FL1 and FLm. Further, the delayed load clock signals LD2 to LDm/2 transmitted from the first delay circuit group DUT1 formed of the delay circuits DL1 to DL(m/2)−1 are supplied to the clock input terminals of the D latches FL1 to FLm, respectively. Further, similar to the first delay circuit group DUT1, the delayed load clock signals LD2 to LDm/2 transmitted from the second delay circuit group DUT2 formed of the delay circuits DL1 to DL(m/2)−1 are supplied to the clock input terminals of the D latches FLm−1 to FL(m/2)−1, respectively.
In the third embodiment, as shown in
The disclosure of Japanese Patent Application No. 2011-0065241, filed on Mar. 24, 2011, is incorporated in the application by reference.
While the invention has been explained with reference to the specific embodiments of the invention, the explanation is illustrative and the invention is limited only by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011-065241 | Mar 2011 | JP | national |
