DISPLAY PANEL, DRIVING CONTROL METHOD THEREOF, DRIVING CONTROL CIRCUIT, AND DISPLAY DEVICE

Abstract

There is provided a driving control method of a display panel. The driving control method includes: receiving a luminance parameter; determining a first waveform provided to a first shift register group for a frame period of a current frame according to the luminance parameter, the first waveform including a second level pulse controlling writing data voltage and at least one second level pulse thereafter for adjusting luminance; determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to the first waveform for a frame period of a previous frame and for the frame period of the current frame, where N≥k≥2 and k is an integer; and for the frame period of the current frame, providing the first waveform to the first shift register group, and providing the k-th waveform to the k-th shift register group.

Description

CROSS-REFERENCE TO RELATED APPLICATION

The present disclosure claims priority of the Chinese patent application No. 201910208916.9 filed on Mar. 19, 2019, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The disclosure relates to the field of display technology, and particularly, relates to a display panel, a driving control method of the display panel, a driving control circuit of the display panel and a display device.

BACKGROUND

A gate driver is usually provided on a side of an organic light emitting diode (OLED) display panel, and includes cascaded shift registers. Each of the shift registers supplies a light emission enable signal (also referred to as an EM signal) to a respective row of pixels, and all of the shift registers are cascaded. When the shift register outputs an inactive voltage, an operation of writing data voltage is performed on the respective row of pixels; and when the shift register outputs an active voltage, the respective row of pixels emit light. In this way, the operation of writing data voltage is sequentially performed on a first row of pixels to a last row of pixels, and then the first row of pixels to the last row of pixels emit light according to the written data voltage. When the OLED display panel is applied to a foldable display device and performs a partial screen display (for example, a half-screen display), all rows of the pixels are driven to display, in which rows of pixels, that are not required to display, display black. This may cause a waste of power consumption.

SUMMARY

An embodiment of the present disclosure provides a display panel including a display area having a plurality of rows of pixels, the display area being divided into N sub-display areas, N being equal to or greater than 2 and being an integer, the display panel further including a gate driver, the gate driver including N shift register groups in one-to-one correspondence with the N sub-display areas, each shift register group including a plurality of shift registers which are cascaded and in one-to-one correspondence with a plurality of rows of pixels within the corresponding sub-display area, each shift register being configured to output a waveform including a first level for controlling a row of pixels corresponding to the shift register to emit light and a second level for controlling the row of pixels corresponding to the shift register to not emit light.

In some embodiments, each of the sub-display areas includes a same number of rows of pixels.

In some embodiments, 2≤N≤4.

In some embodiments, N=2.

An embodiment of the present disclosure further provides a driving control method for the display panel described above. The driving control method includes steps of: receiving a luminance parameter; determining a first waveform provided to a first shift register group for a frame period of a current frame according to the luminance parameter, the first waveform including a second level pulse for controlling a writing of a data voltage and at least one second level pulse thereafter for adjusting luminance, and different luminance parameters corresponding to different first waveforms; determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, where and k is an integer; and for the frame period of the current frame, providing the determined first waveform to the first shift register group, and providing, from k=2 to k=N, the determined k-th waveform to the k-th shift register group.

In some embodiments, each frame period T includes Q row periods T1; and in each frame period, the second level pulse for controlling the writing of the data voltage is first provided to the first shift register group, and then, for each of the second to N-th shift register groups, when time m*T1 elapses from a beginning of providing the second level pulse for controlling the writing of the data voltage to a immediately previous shift register group with regard to the shift register group, the second level pulse for controlling the writing of the data voltage is provided to the shift register group, where m is the number of shift registers in the immediately previous shift register group with regard to the shift register group, and T1 is a delay from receiving a waveform to starting outputting the waveform for each shift register.

In some embodiments, the step of determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, includes: the k-th waveform including a first portion and a second portion following the first portion, the first portion of the k-th waveform being composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the previous frame, and the second portion of the k-th waveform being composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where p is the number of shift registers included in the first to (k−1)-th shift register groups.

In some embodiments, after determining a first waveform provided to a first shift register group for a frame period of a current frame according to the luminance parameter, the driving control method further includes steps of: determining whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame; if a result of the determining is negative, performing the step of determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame; and if the result of the determining is positive, determining the k-th waveform provided to the k-th shift register group for the frame period of the current frame, according to the first waveform provided to the first shift register group for the frame period of the current frame.

In some embodiments, the step of determining the k-th waveform provided to the k-th shift register group for the frame period of the current frame, according to the first waveform provided to the first shift register group for the frame period of the current frame, includes: the k-th waveform including a third portion and a fourth portion following the third portion, the third portion of the k-th waveform being composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the current frame, and the fourth portion of the k-th waveform being composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame.

An embodiment of the present disclosure further provides a driving control circuit for the display panel described above. The driving control circuit is configured to provide a driving control signal to the display panel. The driving control circuit includes: a first receiving sub-circuit configured to receive a luminance parameter; a first waveform determining sub-circuit configured to determine a first waveform provided to a first shift register group for a frame period of a current frame according to the luminance parameter, the first waveform including a second level pulse for controlling a writing of a data voltage and at least one second level pulse thereafter for adjusting luminance, and different luminance parameters corresponding to different first waveforms; a second waveform determining sub-circuit configured to determine a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, where N≥k≥2 and k is an integer; an output sub-circuit configured to, for the frame period of the current frame, provide the determined first waveform to the first shift register group, and provide, from k=2 to k=N, the determined k-th waveform to the k-th shift register group.

In some embodiments, the driving control circuit further includes a second receiving sub-circuit configured to receive a full-screen display mode instruction. The full-screen display mode instruction specifies that: each frame period T includes Q row periods T1; and in each frame period, the second level pulse for controlling the writing of the data voltage is first provided to the first shift register group, and then, for each of the second to N-th shift register groups, when time m*T1 elapses from a beginning of providing the second level pulse for controlling the writing of the data voltage to a immediately previous shift register group with regard to the shift register group, the second level pulse for controlling the writing of the data voltage is provided to the shift register group, where m is the number of shift registers in the immediately previous shift register group with regard to the shift register group, and T1 is a delay from receiving a waveform to starting outputting the waveform for each shift register.

In some embodiments, determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, includes: the k-th waveform including a first portion and a second portion following the first portion, the first portion of the k-th waveform being composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the previous frame, and the second portion of the k-th waveform being composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where p is the number of shift registers included in the first to (k−1)-th shift register groups.

In some embodiments, the second waveform determining sub-circuit is further configured to: determine whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame, if a result of the determining is negative, determine a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, and if the result of the determining is positive, determine the k-th waveform provided to the k-th shift register group for the frame period of the current frame, according to the first waveform provided to the first shift register group for the frame period of the current frame.

In some embodiments, determining the k-th waveform provided to the k-th shift register group for the frame period of the current frame, according to the first waveform provided to the first shift register group for the frame period of the current frame, includes: the k-th waveform including a third portion and a fourth portion following the third portion, the third portion of the k-th waveform being composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the current frame, and the fourth portion of the k-th waveform being composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame.

An embodiment of the present disclosure further provides a driving control method for the display panel described above. The driving control method includes: receiving a partial display mode instruction that specifies sub-display areas for displaying and sub-display areas for not displaying; sequentially providing second level pulses to shift register groups corresponding to the sub-display areas for displaying; and providing a continuous second level to shift register groups corresponding to the sub-display areas for not displaying.

An embodiment of the present disclosure further provides a driving control circuit for the display panel described above. The driving control circuit includes: a receiving sub-circuit configured to receive a partial display mode instruction that specifies sub-display areas for displaying and sub-display areas for not displaying; and an output sub-circuit configured to sequentially provide second level pulses to shift register groups corresponding to the sub-display areas for displaying, and to provide a continuous second level to shift register groups corresponding to the sub-display areas for not displaying.

An embodiment of the present disclosure further provides a display device including the display panel described above and the driving control circuit described above for providing a driving control signal to the display panel.

BRIEF DESCRIPTION OF THE FIGURES

In order to enable those skilled in the art to better understand technical solutions of the present disclosure, the present disclosure will be described in detail below with reference to accompanying drawings and specific implementations.

FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 2 illustrates a flowchart of a driving control method for a display panel according to an exemplary embodiment of the present disclosure;

FIG. 4 is a waveform diagram of a driving control signal for driving the display panel shown in FIG. 1 in a full-screen display;

FIG. 3 is a block diagram of a driving control circuit according to an embodiment of the present disclosure;

FIG. 5 is a waveform diagram of a conventional driving control signal for driving the display panel shown in FIG. 1;

FIG. 6 is a flowchart of a driving control method of a display panel according to an embodiment of the present disclosure;

FIG. 7 illustrates a flowchart of a step of determining whether a luminance parameter of a current frame is equal to a luminance parameter of a previous frame in the driving control method shown in FIG. 6;

FIG. 9 is a waveform diagram of a driving control signal for driving the display panel shown in FIG. 1 using the driving control method shown in FIG. 6;

FIG. 8 is a block diagram of a driving control circuit of a display panel according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

A display panel 1 is provided according to an embodiment of the present disclosure. In some embodiments, the display panel 1 is an OLED display panel.

In an embodiment of the present disclosure, the display panel 1 includes a display area having a plurality of rows of pixels, and the display area is divided into N sub-display areas, where N≥2 and N is an integer. Each of the N sub-display areas includes a plurality of rows of pixels, that is, an i-th sub-display area includes ni rows of pixels and Σ_i=1^N ni=Q, where 1≤i≤N and i is an integer, and ni and Q are both positive integers. It should be understood that Q indicates the total number of rows of pixels included in the display area of the display panel 1. The display panel 1 further includes a gate driver, and the gate driver includes N shift register groups that are in one-to-one correspondence with the sub-display areas, that is, first to N-th shift register groups are in one-to-one correspondence with first to N-th sub-display areas. Each of the N shift register groups includes a plurality of shift registers which are cascaded and in one-to-one correspondence with the rows of pixels within the corresponding sub-display area, that is, an i-th shift register group includes ni shift registers that are in one-to-one correspondence with the ni rows of pixels included in the i-th sub-display area and are cascaded. Each shift register is configured to output a first level indicating a row of pixels corresponding to the shift register to emit light, and output a second level indicating the row of pixels corresponding to the shift register to not emit light. The shift register groups are insulated from each other.

Herein, the first level refers to a voltage signal having a first level, and the second level refers to a voltage signal having a second level. It is understood that the first level is different from the second level.

It should be noted that, in an embodiment of the present disclosure, providing or outputting a waveform to a shift register group means providing a voltage signal conforming to the waveform to a first shift register of the shift register group.

In addition, the first shift register of the shift register group outputs a received waveform to the corresponding row of pixels with a delay of one row period, and then remaining shift registers in the shift register group each outputs the received waveform to a corresponding row of pixels with a sequential delay of one row period.

In an embodiment of the present disclosure, the first level is a low level, the second level is a high level, and the second level pulse is a high level pulse in which the first level is a reference voltage and the second level is a peak voltage, but the present disclosure is not limited thereto.

In some embodiments, each sub-display area includes a same number of rows of pixels, such that an arrangement of the display panel 1 is simpler and a driving algorithm for driving the display panel 1 may also be simpler. In some embodiments, the sub-display areas may include different numbers of rows of pixels, respectively.

In some embodiments, 2≤N≤4. If the number of the sub-display areas is too large, the complexity of the arrangement of the display panel 1 will increase. In some embodiments, N=2.

In an exemplary embodiment as described below, the display panel 1 includes a display area having 1000 rows of pixels, and the display area is divided into 2 sub-display areas.

As described above, FIG. 1 shows a case in which the display panel 1 includes the display area having 1000 rows of pixels, and the display area is divided into 2 sub-display areas. As shown in FIG. 1, the display area of the display panel 1 is divided into a first sub-display area 11 and a second sub-display area 12, and the first sub-display area 11 and the second sub-display area 12 each includes 500 rows of pixels. Further, as shown in FIG. 1, the gate driver of the display panel 1 includes a first shift register group 11a corresponding to the first sub-display area 11 and a second shift register group 12a corresponding to the second sub-display area 12. The first shift register group 11a includes 500 shift registers in one-to-one correspondence with the 500 rows of pixels included in the first sub-display area 11, and the second shift register group 12a includes 500 shift registers in one-to-one correspondence with the 500 rows of pixels included in the second sub-display area 12.

As described above, in the display panel 1 according to an embodiment of the present disclosure, the display area including a plurality of rows of pixels is divided into several sub-display areas, and each of the sub-display areas corresponds to one shift register group. In this case, when the display panel 1 is driven to perform display, for a sub-display area not required to display, it may causes the sub-display area not to perform display by not providing the second level pulse to the shift register group corresponding to the sub-display area while continuously outputting the second level by the shift register group corresponding to the sub-display area; and for sub-display areas required to display, it may causes the sub-display areas to display by sequentially providing second level pulses to the shift register groups corresponding to the sub-display areas required to display according to a scanning direction. In some embodiments, the process of sequentially providing second level pulses to the shift register groups follows that: after writing data for display to a last row of pixels of a sub-display area that displays earlier is completed, writing the data for display to a first row of pixels of a sub-display area that displays immediately later is started. In some embodiments, the process of sequentially providing second level pulses to the shift register groups follows at least that: after starting writing the data for display to a last row of pixels of a sub-display area that displays earlier, writing the data for display to a first row of pixels of a sub-display area that displays immediately later is started. Accordingly, during a period in which the second level pulses are received (or in a preceding portion of a period during which the second level pulses are received) by a row of pixels, data voltage indicating data for display is written to the row of pixels through a data line.

An embodiment according to the present disclosure provides a driving control method for the above-described display panel 1. FIG. 2 shows a flowchart of an example of the driving control method. The driving control method shown in FIG. 2 includes steps S11 to S13.

In step S11, a partial display mode instruction is received, and the partial display mode instruction specifies sub-display areas for displaying and sub-display areas for not displaying.

In step S12, the second level pulses are sequentially provided to shift register groups corresponding to the sub-display areas for displaying.

In step S13, a continuous second level is provided to shift register groups corresponding to the sub-display areas for not displaying.

An embodiment according to the present disclosure provides a driving control circuit for the above-described display panel 1. FIG. 3 shows a block diagram of an example of the driving control circuit.

As shown in FIG. 3, the driving control circuit includes: a receiving sub-circuit 1a configured to receive a partial display mode instruction that specifies sub-display areas for displaying and sub-display areas for not displaying, and an output sub-circuit 1b configured to sequentially provide second level pulses to shift register groups corresponding to the sub-display areas for displaying, and to provide a continuous second level to shift register groups corresponding to the sub-display areas for not displaying.

By driving the display panel according to the embodiment of the present disclosure using the driving control method or the driving control circuit as described above, when a sub-display area is not required to display, the second level pulses may be not provided to a shift register group corresponding to the sub-display area, and data voltage may be not written to the rows of pixels in the sub-display area, thereby reducing power consumption for display of the display panel.

The case shown in FIG. 1 is still taken as an example to describe the process of driving the display panel 1 below.

The scanning direction is from top to bottom according to the current view of FIG. 1. If only pixels in a upper half screen are required to display, the second level pulses are merely provided to the first shift register group 11a in each frame period, and accordingly, data voltage is provided to each row of pixels in the first sub-display area 11; and at the same time, the second shift register group 11b continuously outputs the second level, and data voltage is not provided to the rows of pixels in the second sub-display area 12. Therefore, the purpose of reducing the power consumption for display of the display panel can be achieved.

FIG. 4 is a waveform diagram illustrating a driving control signal for driving the display panel 1 by using the driving control method or the driving control circuit according to the embodiment of the present disclosure when the display panel 1 performs a full-screen display. In FIG. 4, a waveform provided to the first shift register group 11a is denoted as EM1, and a waveform provided to the second shift register group 11b is denoted as EM2. Also taking the case shown in FIG. 1 as an example, as shown in FIG. 4, one second level pulse is first provided to a first shift register of the first shift register group 11a at the beginning of one frame period, and the one second level pulse is transmitted to a next shift register of the first shift register group 11a every other row period. That is, when one row period elapses from the start of providing one second level pulse to the first shift register of the first shift register group 11a, the one second level pulse is provided to a second shift register of the first shift register group 11a, and when one row period elapses from the start of providing the one second level pulse to the second shift register, the one second level pulse is provided to a third shift register of the first shift register group 11a, and so on and so forth, until the one second level pulse is finally provided to a last shift register (i.e., the 500th shift register) of the first shift register group 11a. At the elapse of 500 row periods, the driving of the first shift register group 11a is completed, and the driving of the second shift register group 11b is started with reference to the method of driving the first shift register group 11a. That is, at the elapse of 500 row periods, one second level pulse is first provided to a first shift register of the second shift register group 11b, and the one second level pulse is transmitted to a next shift register of the second shift register group 11b every other row period. Similarly, when another 500 row periods elapse, the driving of the second shift register group 11b is completed, this frame period ends, and a next frame period starts. In each frame period for display, the first shift register group 11a and the second shift register group 11b are driven using the timing shown in FIG. 4. In addition, the display panel 1 performs an operation of writing the data voltage to each row of pixels during a period in which the second level pulse is outputted to the shift register corresponding to the row of pixels, thereby achieving the full-screen display of the display panel 1.

In the accompanying drawings of the present disclosure, the second level pulses (taking high level pulses as an example) which are marked with black dots each is a second level pulses controlling the writing of the data voltage to a row of pixels. An example of the driving control circuit or the driving control chip in the present disclosure is a timing controller.

When the display panel 1 performs full-screen display, the above display panel 1 according to the embodiments of the present disclosure is driven by a driving control signal generated using a conventional driving control circuit or driving control method, and a luminance parameter indicating display luminance of the display panel may be adjusted by adjusting the second level pulses. FIG. 5 shows a waveform diagram of a conventional driving control signal for driving the display panel 1, and the conventional driving control signal includes information indicating a luminance parameter.

For example, still taking the display panel 1 shown in FIG. 1 as an example, as shown in FIG. 5, the driving control signal includes a first waveform EM1 provided to the first shift register group 11a and a second waveform EM2 provided to the second shift register group 11b. As shown in FIG. 5, in each frame period, the first waveform EM1 provided to the first shift register group 11a and the second waveform EM2 provided to the second shift register group 11b each includes a plurality of second level pulses. The first second level pulse in the waveform output by each shift register controls to write a data voltage to a row of pixels corresponding to the shift register, and the second level pulses after the first second level pulse in the waveform is used for adjusting the display luminance of the sub-display area corresponding to the shift register group including the shift register, that is, for indicating the luminance parameter of the sub-display area. In some embodiments, in one frame period, the longer the total duration of the second level included in the second level pulse, the lower the display luminance (equivalently, a maximum luminance) of the sub-display area.

In addition, the conventional driving control circuit or driving control method can only configure waveforms provided to the shift register groups in one frame period.

For example, still taking the display panel 1 shown in FIG. 1 as an example, as shown in FIG. 5, in the conventional driving control circuit or driving control method, for each frame period, the first waveform EM1 including four second level pulses and having a total time length of one frame period is provided to the first shift register group 11a and the second waveform EM2 including four second level pulses and having a total time length of one frame period is provided to the second shift register group 11b, according to the received luminance parameter. The second waveform EM2 for each frame period is formed by the followings: one frame period for the display panel 1 shown in FIG. 1 includes 1000 row periods; and for each frame period, the last 500 row periods of the first waveform EM1, which includes 1000 row periods and is provided to the first shift register group 11a for the frame period, are taken as the first 500 row periods of the second waveform EM2 provided to the second shift register group 11b for the frame period, and the first 500 row periods of the first waveform EM1 provided to the first shift register group 11a for the frame period are taken as the last 500 row periods of the second waveform EM2 provided to the second shift register group 11b for the frame period. By doing so, the second waveform EM2 including 1000 row periods for each frame period is formed according to the first waveform EM1 for the frame period. In other words, for each frame period, the first waveform EM1 for the frame period is cyclically shifted by 500 row periods to form the second waveform EM2 for the frame period. In this case, the waveform provided to the second shift register group 11b and the waveform provided to the first shift register group 11a are always kept identical for a same frame period.

It should be noted that, since the shift register groups sequentially receive and output waveforms as described above, an actual frame period of one frame is different from the frame period of the frame for the shift register groups except the first shift register group. Taking the display panel 1 shown in FIG. 1 as an example, as shown in FIG. 5, for the first shift register group 11a, the frame period and the actual frame period of the first frame each is composed of 1000 row periods of the first frame (i.e., 1000 row periods defined by two leftmost vertical dashed lines corresponding to the first frame in FIG. 5). As shown in FIG. 5, for the second shift register group 11b, the frame period of the first frame is composed of 1000 row periods of the first frame, and the actual frame period of the first frame is composed of the last 500 row periods of the 1000 row periods of the first frame and the first 500 row periods of the second frame.

Therefore, according to the above manner of configuring the waveforms provided to the respective shift register groups, taking the display panel 1 shown in FIG. 1 as an example, when the luminance parameters of two adjacent frames (for example, the second the third frames in FIG. 5) of the display panel 1 remain unchanged, the waveform provided to the first shift register group 11a and the waveform provided to the second shift register group 11b for the frame periods of the two frames remain unchanged. Therefore, as shown in FIG. 5, the waveform provided to the first shift register group 11a for the actual frame period of the second frame of the first shift register group 11a is the same as the waveform provided to the second shift register group 11b for the actual frame period of the second frame of the second shift register group 11b. In this case, the first sub-display area 11 and the second sub-display area 12 of the display panel 1 have the same display luminance.

However, in a case where the luminance parameters of the two adjacent frames are different from each other, taking the first frame and the second frame in FIG. 5 as an example, the waveform provided to the first shift register group 11a for the actual frame period of the first frame of the first shift register group 11a includes four adjacent narrow pulses, and the waveform provided to the second shift register group 11b for the actual frame period of the first frame of the second shift register group 11b includes two adjacent narrow pulses and two adjacent wide pulses. Thus, it would result in that the display luminance of the first sub-display area 11 is different from that of the second sub-display area 12 for the same actual frame period.

In order to solve the technical problem of the difference in the display luminance of the sub-display areas described above, an embodiment of the present disclosure provides a driving control method for the display panel 1 according to an embodiment of the present disclosure, the driving control method includes the following steps S22 to S25 as shown in FIG. 6.

In step S22, a luminance parameter is received. Specifically, for example, when a user adjusts a luminance parameter of a mobile phone, a control circuit of the mobile phone sends the luminance parameter to the driving control circuit of the display panel 1.

In step S23, a first waveform provided to a first shift register group for a frame period of a current frame is determined according to the luminance parameter. The first waveform includes a second level pulse controlling writing of a data voltage and at least one second level pulse thereafter for adjusting luminance, and different luminance parameters corresponds to different first waveforms.

That is, the first waveform EM1 provided to the first shift register group is determined by the luminance parameter. In an embodiment of the present disclosure, the first waveform includes uniform continuous square wave pulses, but the present disclosure is not limited thereto. In addition, the number of the second level pulses and the duration of a second level pulse are not particularly limited, as long as the first waveform includes the second level pulse controlling writing of data for display and the second level pulse for adjusting the luminance.

In step S24, a k-th waveform provided to a k-th shift register group for the frame period of the current frame is determined according to the first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame. The k-th waveform includes a first portion and a second portion following the first portion, the first portion of the k-th waveform is composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the previous frame, and the second portion of the k-th waveform is composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where p is the number of shift registers included in the first to (k−1)-th shift register groups. It is understood that Q indicates the total number of rows of pixels included in the display area of the display panel 1, i.e., the number of shift registers in the display panel 1.

In step S25, for the frame period of the current frame, the determined first waveform is provided to the first shift register group, and the determined k-th waveform is provided to the k-th shift register group from k=2 to k=N.

In some embodiments, as shown in FIG. 6, the driving control method further includes step S21 before step S22. In step S21, a full-screen display mode instruction is received, and the full-screen display mode instruction specifies that: each frame period T includes Q row periods T1; and in each frame period, the second level pulse controlling the writing of the data voltage is first provided to the first shift register group, and then, for each of the second to N-th shift register groups, when time m*T1 elapses from the beginning of providing the second level pulse controlling the writing of the data voltage to a immediately previous shift register group with regard to the shift register group, the second level pulse controlling the writing of the data voltage is provided to the shift register group, where m is the number of shift registers in the immediately previous shift register group with regard to the shift register group, and T1 is a delay from receiving a waveform to starting outputting the waveform for each shift register of each shift register group. That is, the row period is always T1.

Taking the display panel 1 shown in FIG. 1 as an example, as described above, the luminance parameters of the first and second frames of the display panel 1 are different. In this case, as shown in FIG. 9, the first portion of the waveform provided to the second shift register group 11b for the frame period of the second frame is composed of the last ½ of the waveform provided to the first shift register group 11a for the frame period of the first frame, and the second portion of the waveform provided to the second shift register group 11b for the frame period of the second frame is composed of the first ½ of the waveform provided to the first shift register group 11a for the frame period of the second frame. Thus, starting from the actual frame period of the first frame in which the display panel performs display, the waveform EM2 received by the 501-th row of pixels as well as subsequent rows of pixels is the same as the waveform EM1 received by the first row of pixels. Therefore, the first sub-display area 11 and the second sub-display area 12 perform display in the same luminance during the actual frame period of a same frame.

In some embodiments, configuring the waveforms for the shift register groups according to the method shown in FIG. 6 for all of the frame periods may result in an excessive calculation amount. Therefore, in some embodiments, the driving control method further includes a step of determining whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame.

Specifically, as shown in FIG. 7, the driving control method further includes the following steps S31 to S33.

In step S31, it is determined whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame.

In step S32, if a result of the determining in step S31 is negative, the step of determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame is performed, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame. In this case, the k-th waveform includes a first portion and a second portion following the first portion, the first portion of the k-th waveform is composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the previous frame, and the second portion of the k-th waveform is composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where 2≤k≤N, and p is the number of shift registers included in the first to (k−1)-th shift register groups.

In step S33, if the result of the determining is positive, the k-th waveform provided to the k-th shift register group for the frame period of the current frame is determined according to the first waveform provided to the first shift register group for the frame period of the current frame. In this case, the k-th waveform includes a third portion and a fourth portion following the third portion, the third portion of the k-th waveform is composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the current frame, and the fourth portion of the k-th waveform is composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where 2≤k≤N, and p is the number of shift registers included in the first to (k−1)-th shift register groups.

Therefore, the calculation amount required for the driving control method can be greatly reduced, and the power consumption is reduced.

In addition, it is easy to understand that the driving control method is also applicable to a case in which the luminance parameters of two adjacent frames are the same.

It can be seen that, the driving control method can ensure that the luminance parameters of the sub-display areas are the same by only arranging the timing sequence in the frame period of the current frame.

An embodiment of the present disclosure further provides a driving control circuit for the above-described display panel 1. The driving control circuit is configured to provide a driving control signal to the display panel 1, and the driving control circuit is configured to implement the above-described driving control method. As shown in FIG. 8, the driving control circuit includes the following sub-circuits 22 to 25.

The second receiving sub-circuit 22 corresponds to step S22 in the driving control method and is configured to receive the luminance parameter.

The first waveform determining sub-circuit 23 is configured to determine the first waveform provided to the first shift register group for the frame period of the current frame according to the luminance parameter. The first waveform includes a second level pulse controlling the writing of the data voltage and at least one second level pulse thereafter for adjusting luminance, and different luminance parameters correspond to different first waveforms. The first waveform determining sub-circuit 23 corresponds to step S23 in the driving control method.

The second waveform determining sub-circuit 24 is configured to determine the k-th waveform provided to the k-th shift register group for the frame period of the current frame, according to the first waveform provided to the first shift register group for the frame period of the previous frame and the first waveform provided to the first shift register group for the frame period of the current frame. The k-th waveform includes a first portion and a second portion following the first portion, the first portion of the k-th waveform is composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the previous frame, and the second portion of the k-th waveform is composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where and p is the number of shift registers included in the first to (k−1)-th shift register groups. The second waveform determining sub-circuit 24 corresponds to step S24 in the driving control method.

The output sub-circuit 25 is configured to, for the frame period of the current frame, provide the determined first waveform to the first shift register group, and provide, from k=2 to k=N, the k-th waveform determined by the second waveform determining sub-circuit 24 to the k-th shift register group. That is, the output sub-circuit 25 realizes the outputting of the waveforms. The output sub-circuit 25 corresponds to step S25 in the driving control method.

In some embodiments, as shown in FIG. 8, the driving control circuit may further include a first receiving sub-circuit 21 configured to receive a full-screen display mode instruction. The full-screen display mode instruction specifies that: each frame period T includes Q row periods T1; and in each frame period, the second level pulse controlling the writing of the data voltage is first provided to the first shift register group, and then, for each of the second to N-th shift register groups, when time m*T1 elapses from the beginning of providing the second level pulse controlling the writing of the data voltage to a immediately previous shift register group with regard to the shift register group, the second level pulse controlling the writing of the data voltage is provided to the shift register group, where m is the number of shift registers in the immediately previous shift register group with regard to the shift register group, and T1 is a delay from receiving a waveform to starting outputting the waveform for each shift register of each shift register group. The first reception sub-circuit 21 corresponds to step S21 in the driving control method shown in FIG. 6.

In some embodiments, the second waveform determining sub-circuit 24 may be further configured to determine whether the luminance parameters of two adjacent frames are the same.

In particular, in some embodiments, the second waveform determining sub-circuit 24 is configured to: determine whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame, and if a result of the determining is negative, perform the step of determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame. In this case, the k-th waveform includes a first portion and a second portion following the first portion, the first portion of the k-th waveform is composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the previous frame, and the second portion of the k-th waveform is composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where and p is the number of shift registers included in the first to (k−1)-th shift register groups.

The second waveform determining sub-circuit 24 is further configured to, if the result of the determining is positive, determine the k-th waveform provided to the k-th shift register group for the frame period of the current frame according to the first waveform provided to the first shift register group for the frame period of the current frame. In this case, the k-th waveform includes a third portion and a fourth portion following the third portion, the third portion of the k-th waveform is composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the current frame, and the fourth portion of the k-th waveform is composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where and p is the number of shift registers included in the first to (k−1)-th shift register groups.

In some embodiments, a register may be provided in the driving control circuit. The register is configured to set parameters of the waveform provided to the shift register group. Taking the first waveform and the second waveform (each of which includes four second level pulses for one frame period) shown in FIG. 9 as an example, as shown in FIG. 9, for one frame period, the first waveform EM1 provided to the first shift register group 11a is determined by the following three parameters: a first pulse period prid1 (which indicates a period of a first second level pulse provided to the first shift register group 11a during the frame period), a first preceding duration ofst1 (which indicates a duration from the start of the frame period to a rising edge of the first second level pulse provided to the first shift register group 11a), a first subsequent duration wid1 (which indicates a duration from a falling edge of the first second level pulse provided to the first shift register group 11a to the end of the period of the first second level pulse provided to the first shift register group 11a). The first waveform provided to the first shift register group 11a and corresponding to a luminance parameter is determined by the three above parameters no matter how the luminance parameter changes. In this case, the second level pulses of the first waveform may have identical parameters.

As shown in FIG. 9, if the luminance parameters of two adjacent frames remain unchanged, the second waveform EM2 provided to the second shift register group 11b for the latter frame of the two adjacent frames is determined by the following three parameters: a second pulse period prid2 (which indicates a period of a first second level pulse provided to the second shift register group 11b during the frame period of the frame), a second preceding duration ofst2 (which indicates a duration from the start of the frame period of the frame to a rising edge of the first second level pulse provided to the second shift register group 11b), a second subsequent duration wid2 (which indicates a duration from a falling edge of the first second level pulse provided to the second shift register group 11b to the end of the period of the first second level pulse provided to the second shift register group 11b). In this case, the second level pulses of the second waveform may have identical parameters.

As shown in FIG. 9, if the luminance parameters of two adjacent frames are different from each other, the waveform provided to the second shift register group 11b for the latter frame of the two adjacent frames is determined by the following six parameters: a third pulse period prid2f (which indicates a period of each of the first two second level pulses provided to the second shift register group 11b during the frame period of the frame), a third preceding duration ofst2f (which indicates a duration from the start of the frame period of the frame to a rising edge of a first second level pulse provided to the second shift register group 11b), a third subsequent duration wid2f (which indicates a duration from a falling edge of the first second level pulse provided to the second shift register group 11b to the end of the period of the first second level pulse provided to the second shift register group 11b), and a fourth pulse period prid2b (which indicates a period of each of the last two second level pulses provided to the second shift register group 11b during the frame period of the frame), a fourth preceding duration ofst2b (which indicates a duration from the end of the period of a second second level pulse provided to the second shift register group 11b to a rising edge of a third second level pulse provided to the second shift register group 11b), a fourth subsequent duration wid2b (which indicates a duration from a falling edge of the third second level pulse provided to the second shift register group 11b to the end of the period of the third second level pulse provided to the second shift register group 11b). In this case, the first two second level pulses provided to the second shift register group 11b may have identical parameters, and the last two second level pulses provided to the second shift register group 11b may have identical parameters.

A case where four second level pulses are included in one frame period is illustrated in the embodiment of the present disclosure (e.g., as shown in FIG. 9), but the present disclosure is not limited thereto. In some embodiments, one frame period may include more than four second level pulses or less than four second level pulses.

In the case where the display panel according to the embodiments of the present disclosure is driven to perform a full-screen display by using the driving control circuit or the driving control method according to the embodiments of the present disclosure, the luminance parameters of the sub-display areas can be always identical in the actual frame period of a same frame for the sub-display areas even if the luminance parameters change for different frame periods.

An embodiment of the present disclosure provide a display device including the display panel according to embodiments of the present disclosure and the driving control circuit according to embodiments of the present disclosure.

In some embodiments, the display device may include an OLED display sub-circuit, a foldable mobile phone, a foldable tablet, and the like.

It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to those ordinarily skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these changes and modifications are considered within the scope of the disclosure.

Claims

1-17. (canceled)

18. A driving control method of a display panel, the display panel comprising a display area having a plurality of rows of pixels, the display area being divided into N sub-display areas, N being equal to or greater than 2 and being an integer, the display panel further comprising a gate driver, the gate driver comprising N shift register groups in one-to-one correspondence with the N sub-display areas, each shift register group comprising a plurality of shift registers which are cascaded and in one-to-one correspondence with a plurality of rows of pixels within the corresponding sub-display area, each shift register being configured to output a waveform comprising a first level for controlling a row of pixels corresponding to the shift register to emit light and a second level for controlling the row of pixels corresponding to the shift register to not emit light, wherein the driving control method comprises steps of:receiving a luminance parameter;determining a first waveform provided to a first shift register group for a frame period of a current frame according to the luminance parameter, the first waveform comprising a second level pulse for controlling a writing of a data voltage and at least one second level pulse thereafter for adjusting luminance, and different luminance parameters corresponding to different first waveforms;determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, where N≥k≥2 and k is an integer; andfor the frame period of the current frame, providing the determined first waveform to the first shift register group, and providing, from k=2 to k=N, the determined k-th waveform to the k-th shift register group.

19. The driving control method according to claim 18, wherein each frame period includes Q row periods T1, andin each frame period, the second level pulse for controlling the writing of the data voltage is first provided to the first shift register group, and then, for each of the second to N-th shift register groups, when time m*T1 elapses from a beginning of providing the second level pulse for controlling the writing of the data voltage to a immediately previous shift register group with regard to the shift register group, the second level pulse for controlling the writing of the data voltage is provided to the shift register group,where m is the number of shift registers in the immediately previous shift register group with regard to the shift register group, and T1 is a delay from receiving a waveform to starting outputting the waveform for each shift register.

20. The driving control method according to claim 19, wherein the step of determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, comprises: the k-th waveform comprising a first portion and a second portion following the first portion, the first portion of the k-th waveform being composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the previous frame, and the second portion of the k-th waveform being composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where p is the number of shift registers comprised in the first to (k−1)-th shift register groups.

21. The driving control method according to claim 20, further comprising steps of, after the step of determining a first waveform provided to a first shift register group for a frame period of a current frame according to the luminance parameter: determining whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame,if a result of the determining is negative, performing the step of determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, andif the result of the determining is positive, determining the k-th waveform provided to the k-th shift register group for the frame period of the current frame, according to the first waveform provided to the first shift register group for the frame period of the current frame.

22. The driving control method according to claim 21, wherein the step of determining the k-th waveform provided to the k-th shift register group for the frame period of the current frame, according to the first waveform provided to the first shift register group for the frame period of the current frame, comprises: the k-th waveform comprising a third portion and a fourth portion following the third portion, the third portion of the k-th waveform being composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the current frame, and the fourth portion of the k-th waveform being composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame.

23. The driving control method according to claim 18, further comprising steps of: receiving a partial display mode instruction that specifies sub-display areas for displaying and sub-display areas for not displaying;sequentially providing second level pulses to shift register groups corresponding to the sub-display areas for displaying; andproviding a continuous second level to shift register groups corresponding to the sub-display areas for not displaying.

24. A driving control circuit of a display panel, the display panel comprising a display area having a plurality of rows of pixels, the display area being divided into N sub-display areas, N being equal to or greater than 2 and being an integer, the display panel further comprising a gate driver, the gate driver comprising N shift register groups in one-to-one correspondence with the N sub-display areas, each shift register group comprising a plurality of shift registers which are cascaded and in one-to-one correspondence with a plurality of rows of pixels within the corresponding sub-display area, each shift register being configured to output a waveform comprising a first level for controlling a row of pixels corresponding to the shift register to emit light and a second level for controlling the row of pixels corresponding to the shift register to not emit light, wherein the driving control circuit is configured to provide a driving control signal to the display panel, and the driving control circuit comprises:a first receiving sub-circuit configured to receive a luminance parameter;a first waveform determining sub-circuit configured to determine a first waveform provided to a first shift register group for a frame period of a current frame according to the luminance parameter, the first waveform comprising a second level pulse for controlling a writing of a data voltage and at least one second level pulse thereafter for adjusting luminance, and different luminance parameters corresponding to different first waveforms;a second waveform determining sub-circuit configured to determine a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, where N≥k≥2 and k is an integer;an output sub-circuit configured to, for the frame period of the current frame, provide the determined first waveform to the first shift register group, and provide, from k=2 to k=N, the determined k-th waveform to the k-th shift register group.

25. The driving control circuit according to claim 24, further comprising a second receiving sub-circuit configured to receive a full-screen display mode instruction, wherein the full-screen display mode instruction specifies that: each frame period comprises Q row periods T1, andin each frame period, the second level pulse for controlling the writing of the data voltage is first provided to the first shift register group, and then, for each of the second to N-th shift register group, in this order, when time m*T1 elapses from a beginning of providing the second level pulse for controlling the writing of the data voltage to a immediately previous shift register group with regard to the shift register group, the second level pulse for controlling the writing of the data voltage is provided to the shift register group,where m is the number of shift registers in the immediately previous shift register group with regard to the shift register group, and T1 is a delay from receiving a waveform to starting outputting the waveform for each shift register.

26. The driving control circuit according to claim 25, wherein determining a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, comprises: the k-th waveform comprising a first portion and a second portion following the first portion, the first portion of the k-th waveform being composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the previous frame, and the second portion of the k-th waveform being composed of a first (1−p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame, where p is the number of shift registers included in the first to (k−1)-th shift register groups.

27. The driving control circuit according to claim 26, wherein the second waveform determining sub-circuit is further configured to: determine whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame,if a result of the determining is negative, determine a k-th waveform provided to a k-th shift register group for the frame period of the current frame, according to a first waveform provided to the first shift register group for a frame period of a previous frame and the first waveform provided to the first shift register group for the frame period of the current frame, andif the result of the determining is positive, determine the k-th waveform provided to the k-th shift register group for the frame period of the current frame, according to the first waveform provided to the first shift register group for the frame period of the current frame.

28. The driving control circuit according to claim 27, wherein determining the k-th waveform provided to the k-th shift register group for the frame period of the current frame, according to the first waveform provided to the first shift register group for the frame period of the current frame, comprises: the k-th waveform comprising a third portion and a fourth portion following the third portion, the third portion of the k-th waveform being composed of a last p/Q of the first waveform provided to the first shift register group for the frame period of the current frame, and the fourth portion of the k-th waveform being composed of a first (1-p/Q) of the first waveform provided to the first shift register group for the frame period of the current frame.

29. The driving control circuit according to claim 24, further comprising: a third receiving sub-circuit configured to receive a partial display mode instruction that specifies sub-display areas for displaying and sub-display areas for not displaying, andwherein the output sub-circuit is further configured to sequentially provide second level pulses to shift register groups corresponding to the sub-display areas for displaying, and to provide a continuous second level to shift register groups corresponding to the sub-display areas for not displaying.

30. A display panel comprising a display area having a plurality of rows of pixels, the display area being divided into N sub-display areas, N being equal to or greater than 2 and being an integer, the display panel further comprising a gate driver, the gate driver comprising N shift register groups in one-to-one correspondence with the N sub-display areas, each shift register group comprising a plurality of shift registers which are cascaded and in one-to-one correspondence with a plurality of rows of pixels within the corresponding sub-display area, each shift register being configured to output a waveform comprising a first level for controlling a row of pixels corresponding to the shift register to emit light and a second level for controlling the row of pixels corresponding to the shift register to not emit light.

31. The display panel according to claim 30, wherein each of the sub-display areas comprises a same number of rows of pixels.

32. The display panel according to claim 30, wherein 2≤N≤4.

33. The display panel according to claim 32, wherein N=2.

34. The display panel according to claim 31, wherein 2≤N≤4.

35. The display panel according to claim 34, wherein N=2.

36. A display device comprising the display panel according to claim 30 and a driving control circuit providing a driving control signal to the display panel.

37. A display device comprising a display panel and the driving control circuit according to claim 24, wherein the driving control circuit provides the driving control signal to the display panel.