Patent Grant
12131694
The disclosure relates to the field of display technology, and particularly, relates to a display panel, a driving control method of the display panel, a driving control circuit of the display panel and a display device.
A gate driver is usually provided on a side of an organic light emitting diode (OLED) display panel, and includes cascaded shift registers. Each of the shift registers supplies a light emission enable signal (also referred to as an EM signal) to a respective row of pixels, and all of the shift registers are cascaded. When the shift register outputs an inactive voltage, an operation of writing data voltage is performed on the respective row of pixels; and when the shift register outputs an active voltage, the respective row of pixels emit light. In this way, the operation of writing data voltage is sequentially performed on a first row of pixels to a last row of pixels, and then the first row of pixels to the last row of pixels emit light according to the written data voltage. When the OLED display panel is applied to a foldable display device and performs a partial screen display (for example, a half-screen display), all rows of the pixels are driven to display, in which rows of pixels, that are not required to display, display black. This may cause a waste of power consumption.
The present disclosure can at least partially solve the problem of waste of power consumption when a conventional OLED display panel performs a partial display, and provides a display panel, a driving control method of the display panel, a driving control circuit, and a display device.
According to a first aspect of the present disclosure, a display panel is provided. The display panel is an OLED display panel, includes a plurality of rows of pixels and is divided into N sub-display areas, where N≥2. An i-th sub-display area includes ni rows of pixels, where 1≤i≤N. The display panel further includes a gate driver, the gate driver includes N shift register groups that are in one-to-one correspondence with the sub-display areas, each of the shift register groups includes a plurality of shift registers which are cascaded and in one-to-one correspondence with the rows of pixels within the corresponding sub-display area, each shift register outputs a first level for controlling a row of pixels corresponding to the shift register to emit light, and outputs a second level for controlling the row of pixels corresponding to the shift register to not emit light, and the shift register groups are insulated from each other.
Optionally, each of the sub-display areas includes a same number of rows of pixels.
Optionally, 2≤N≤4.
Optionally, N=2.
According to a second aspect of the present disclosure, a driving control method of a display panel is provided. The display panel is the display panel according to the first aspect of the present disclosure, and the driving control method includes steps of:
According to a third aspect of the present disclosure, a driving control circuit of a display panel is provided. The display panel is the display panel according to the first aspect of the present disclosure, and the driving control circuit includes: a receiving sub-circuit configured to receive a partial display mode instruction that specifies sub-display areas for displaying and sub-display areas for not displaying; and an output sub-circuit configured to sequentially provide second level pulses to shift register groups corresponding to the sub-display areas for displaying, and to provide a continuous second level to shift register groups corresponding to the sub-display areas for not displaying.
According to a fourth aspect of the present disclosure, a driving control method of a display panel is provided. The display panel is the display panel according to the first aspect of the present disclosure, and the driving control method includes steps of: receiving a full-screen display mode instruction, wherein the full-screen display mode instruction specifies that: each frame period T includes Q row periods T1; and in each frame period, a second level pulse for controlling writing of data voltage is first provided to a first shift register group, and then, for each of second to N-th shift register groups, when time m*T1 elapses from a beginning of providing an initial edge of the second level pulse for controlling the writing of the data voltage to a immediately previous shift register group with regard to the shift register group, the second level pulse for controlling the writing of the data voltage is provided to the shift register group, where m is a number of shift registers in the immediately previous shift register group with regard to the shift register group, and T1 is a delay from receiving a waveform to starting outputting the waveform for each shift register of each shift register group;
Optionally, after the step of determining a first waveform provided to the first shift register group for a current frame according to the luminance parameter, the driving control method further includes:
According to a fifth aspect of the present disclosure, a driving control circuit of a display panel is provided, and the driving control circuit is configured to provide a driving control signal to the display panel. The display panel is the display panel according to the first aspect of the present disclosure, and the driving control circuit includes:
Optionally, the second waveform determining sub-circuit is further configured to:
According to a sixth aspect of the present disclosure, a display device including a display panel and a driving control circuit for providing a driving control signal to the display panel is provided. The display panel is the display panel according to the first aspect of the present disclosure, and the driving control circuit is the driving control circuit according to the third or fourth aspect of the present disclosure.
Reference symbols are as follows: 1: a display panel; 11: a first sub-display area; 12: a second sub-display area; 11a: a first shift register group; 11b: a second shift register group; 21: a first receiving sub-circuit; 22: a second receiving sub-circuit; 23: a first waveform determining sub-circuit; 24: a second waveform determining sub-circuit; 25: an output sub-circuit.
To improve understanding of the technical solution of the present disclosure for those skilled in the art, the present disclosure will now be described in detail with the help of accompanying drawings and specific embodiments.
The present embodiment provides a display panel 1. The display panel 1 is an OLED display panel 1. The display panel 1 includes a plurality of rows of pixels, and is divided into N sub-display areas, where N≥2. An i-th sub-display area includes ni rows of pixels, where 1≤i≤N and Σi=1N ni=Q. The display panel 1 further includes a gate driver, and the gate driver includes N shift register groups that are in one-to-one correspondence with the sub-display areas. Each of the shift register groups includes a plurality of shift registers which are cascaded and in one-to-one correspondence with the rows of pixels within the corresponding sub-display area. Each shift register is configured to output a first level for controlling a row of pixels corresponding to the shift register to emit light, and output a second level for controlling the row of pixels corresponding to the shift register to not emit light. The shift register groups are insulated from each other.
It should be noted that, in the present disclosure, providing or outputting a waveform to a shift register group means providing a voltage signal conforming to the waveform to a first shift register of the shift register group. In the present disclosure, for example, the second level is a high level, and the second level pulse is a high level pulse.
According to the structure described above, the plurality of rows of pixels are divided into several sub-display areas, and each of the sub-display areas corresponds to one shift register group. In this case, when the display panel 1 is driven to perform display, for a sub-display area not required to display, the second level pulse is not provided to the shift register group corresponding to the sub-display area while continuously outputting the second level by the shift register group corresponding to the sub-display area; and for sub-display areas required to display, second level pulses may be sequentially provided to the shift register groups in a scanning direction at a certain time interval. The time interval ensures that: after the writing of data for display to a last row of pixels of a sub-display area that performs display earlier is completed, the writing of the data for display to a first row of pixels of a sub-display area, that performs display immediately following the sub-display area performing display earlier, is started; or the time interval ensures that: after starting the writing of the data for display to a last row of pixels of a sub-display area that performs display earlier, the writing of the data for display to a first row of pixels of a sub-display area, that performs display immediately following the sub-display area performing display earlier, is started. Accordingly, during a period in which the second level pulses are received (or in a preceding portion of a period during which the second level pulses are received) by a row of pixels, data voltage is written to the row of pixels through a data line.
It should be noted that, the first shift register of the shift register group outputs a received waveform to the corresponding row of pixels with a delay of one row period, and then remaining shift registers in the shift register group each outputs the received waveform to a corresponding row of pixels with a sequential delay of one row period. This section is prior art and is not specifically described herein.
That is, a driving control is performed as follows: a partial display mode instruction is received, and the partial display mode instruction specifies sub-display areas for displaying and sub-display areas for not displaying; the second level pulses are sequentially provided to shift register groups corresponding to the sub-display areas for displaying; a continuous second level is provided to shift register groups corresponding to the sub-display areas for not displaying.
Correspondingly, as shown in
In this way, when a sub-display area is not required to display, the second level pulses may be not provided to a shift register group corresponding to the sub-display area, and data voltage may be not written to the rows of pixels in the sub-display area, thereby achieving the purpose of reducing power consumption.
Optionally, each sub-display area includes a same number of rows of pixels, such that an arrangement of the display panel 1 is simpler and a driving algorithm for driving the display panel 1 may also be simpler. The display panel 1 may be non-equally divided into the sub-display areas.
Optionally, 2≤N≤4. If the number of the sub-display areas is too large, the complexity of the arrangement of the display panel 1 will increase.
Optionally, N=2.
In this way, the purpose of reducing the power consumption can be achieved.
It should be noted that, in the accompanying drawings of the present disclosure, the second level pulses (taking high level pulses as an example) which are marked with black dots each is a second level pulse for controlling the writing of the data voltage. An example of the driving control circuit or a driving control chip in the present disclosure is a timing controller.
When a conventional driving control chip provides a driving control signal to such a display panel 1, a luminance parameter for display may be adjusted by adjusting the second level pulses. Referring to
The present embodiment provides a driving control method for the display panel 1 of Embodiment 1 of the present disclosure. Referring to
In step S1, a full-screen display mode instruction is received, and the full-screen display mode instruction specifies that: each frame period T includes Q row periods T1; and in each frame period, the second level pulse for controlling the writing of the data voltage is first provided to the first shift register group, and then, for each of the second to N-th shift register groups, when time m*T1 elapses from the beginning of providing an initial edge of the second level pulse for controlling the writing of the data voltage to a immediately previous shift register group with regard to the shift register group, the second level pulse for controlling the writing of the data voltage is provided to the shift register group, where m is the number of shift registers in the immediately previous shift register group with regard to the shift register group, and T1 is a delay from receiving a waveform to starting outputting the waveform for each shift register of each shift register group. That is, the row period is always T1.
Specifically, for example, the second level pulse is indicated by a black dot in
The dotted lines in the timing diagrams indicate the initial rising edge of a frame start signal Vsync.
In step S2, a luminance parameter is received. Specifically, for example, when a user adjusts a luminance parameter of a mobile phone, a control circuit of the mobile phone sends the luminance parameter to the driving control chip of the display panel 1.
In step S3, a first waveform provided to the first shift register group for a current frame is determined according to the luminance parameter. The first waveform includes the second level pulse for controlling the writing of the data voltage and at least one second level pulse thereafter for adjusting luminance, and different luminance parameters correspond to different first waveforms.
That is, the first waveform EM1 provided to the first shift register group is determined by the luminance parameter. For most driving control chips, the first waveform includes uniform consecutive square wave pulses for the purpose of system simplification. In addition, the number of the second level pulses and the duration of a second level pulse are not particularly limited, as long as the first waveform includes the second level pulse for controlling the writing of data for display and the second level pulse for adjusting the luminance.
In step S4, a second waveform provided to a k-th shift register group for the current frame is determined according to the first waveform provided to the first shift register group for a previous frame and the first waveform provided to the first shift register group for the current frame. The second waveform is formed by concatenating a second portion to a first portion, the first portion of the second waveform is a portion of the first waveform provided to the first shift register group for the previous frame corresponding to a last p*T1 of the previous frame, and the second portion of the second waveform is a portion of the first waveform provided to the first shift register group for the current frame corresponding to a first (T−p*T1) of the current frame, where 2≤k≤N, p is the number of shift registers included in the first to (k−1)-th shift register groups.
In step S5, for the current frame, the determined first waveform is provided to the first shift register group, and each of remaining shift register groups is provided with a corresponding determined second waveform.
Taking the first and second frames shown in
In an implementation, the second waveform is configured in the above manner for all of the frame periods. However, this may result in an excessive calculation of the driving circuit.
The present disclosure further provides an implementation including a step of determining whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame.
Specifically, it is determined whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame.
If it is determined that the luminance parameter of the current frame is not equal to the luminance parameter of the previous frame, the second waveform provided to the k-th shift register group for the current frame is determined according to the first waveform provided to the first shift register group for the previous frame and the first waveform provided to the first shift register group for the current frame. The second waveform is formed by concatenating a second portion to a first portion, the first portion of the second waveform is a portion of the first waveform provided to the first shift register group for the previous frame corresponding to a last p*T1 of the previous frame, and the second portion of the second waveform is a portion of the first waveform provided to the first shift register group for the current frame corresponding to a first (T−p*T1) of the current frame, where 2≤k≤N, p is the number of shift registers included in the first to (k−1)-th shift register groups.
If it is determined that the luminance parameter of the current frame is equal to the luminance parameter of the previous frame, the second waveform provided to the k-th shift register group for the current frame is determined according to the first waveform provided to the first shift register group for the current frame. In this case, the second waveform is formed by concatenating a fourth portion to a third portion, the third portion of the second waveform is a portion of the first waveform provided to the first shift register group for the current frame corresponding to a last p*T1 of the current frame, and the fourth portion of the second waveform is a portion of the first waveform provided to the first shift register group for the current frame corresponding to a first (T−p*T1) of the current frame.
Therefore, the calculation amount required for the driving control circuit can be greatly reduced, and the power consumption is reduced.
Taking the second and third frames shown in
The above two implementations can achieve, by only arranging the timing sequence in the frame period of the current frame, that the luminance parameters of the sub-display areas are the same in the process of adjusting the luminance parameter.
Referring to
A first receiving sub-circuit 21 is configured to receive a full-screen display mode instruction and a luminance parameter. The full-screen display mode instruction specifies that: each frame period T includes Q row periods T1; and in each frame period, the second level pulse for controlling the writing of the data voltage is first provided to the first shift register group, and then, for each of the second to N-th shift register groups, when time m*T1 elapses from the beginning of providing an initial edge of the second level pulse for controlling the writing of the data voltage to a immediately previous shift register group with regard to the shift register group, the second level pulse for controlling the writing of the data voltage is provided to the shift register group, where m is the number of shift registers in the immediately previous shift register group with regard to the shift register group, and T1 is a delay from receiving a waveform to starting outputting the waveform for each shift register of each shift register group. The first receiving sub-circuit 21 corresponds to step S1 in Embodiment 2.
A second receiving sub-circuit 22 corresponds to step S2 in Embodiment 2 and is configured to receive the luminance parameter.
A first waveform determining sub-circuit 23 is configured to determine the first waveform provided to the first shift register group for the current frame according to the luminance parameter. The first waveform includes a second level pulse for controlling the writing of the data voltage and at least one second level pulse thereafter for adjusting luminance, and different luminance parameters correspond to different first waveforms. The first waveform determining sub-circuit 23 corresponds to step S3 in Embodiment 2.
A second waveform determining sub-circuit 24 is configured to determine a second waveform provided to a k-th shift register group for the current frame according to the first waveform provided to the first shift register group for a previous frame and the first waveform provided to the first shift register group for the current frame. The second waveform is formed by concatenating a second portion to a first portion, the first portion of the second waveform is a portion of the first waveform provided to the first shift register group for the previous frame corresponding to a last p*T1 of the previous frame, and the second portion of the second waveform is a portion of the first waveform provided to the first shift register group for the current frame corresponding to a first (T−p*T1) of the current frame, where 2≤k≤N, p is the number of shift registers included in the first to (k−1)-th shift register groups. The second waveform determining sub-circuit 24 corresponds to step S4 in Embodiment 2.
An output sub-circuit 25 is configured to, for the current frame, provide the determined first waveform to the first shift register group, and provide each of remaining shift register groups with a corresponding determined second waveform. The output sub-circuit 25 implements the outputting of the waveforms.
The second waveform determining sub-circuit 24 may be further configured to determine whether the luminance parameters of two adjacent frames are the same, or configured to not determine whether the luminance parameters of two adjacent frames are the same. As a preferred implementation, the second waveform determining sub-circuit 24 is configured to determine whether the luminance parameter of the current frame is equal to the luminance parameter of the previous frame. If it is determined that the luminance parameter of the current frame is not equal to the luminance parameter of the previous frame, the second waveform determining sub-circuit 24 is configured to determine the second waveform provided to the k-th shift register group for the current frame according to the first waveform provided to the first shift register group for the previous frame and the first waveform provided to the first shift register group for the current frame. The second waveform is formed by concatenating a second portion to a first portion, the first portion of the second waveform is a portion of the first waveform provided to the first shift register group for the previous frame corresponding to a last p*T1 of the previous frame, and the second portion of the second waveform is a portion of the first waveform provided to the first shift register group for the current frame corresponding to a first (T−p*T1) of the current frame, where 2≤k≤N, p is the number of shift registers included in the first to (k−1)-th shift register groups. If it is determined that the luminance parameter of the current frame is equal to the luminance parameter of the previous frame, the second waveform determining sub-circuit 24 is configured to determine the second waveform provided to the k-th shift register group for the current frame according to the first waveform provided to the first shift register group for the current frame. In this case, the second waveform is formed by concatenating a fourth portion to a third portion, the third portion of the second waveform is a portion of the first waveform provided to the first shift register group for the current frame corresponding to a last p*T1 of the current frame, and the fourth portion of the second waveform is a portion of the first waveform provided to the first shift register group for the current frame corresponding to a first (T−p*T1) of the current frame.
Specifically, a register may be provided in the driving control chip. The register is configured to set parameters of the waveform provided to the shift register group. Providing four uniform second level pulses to each shift register group in the process of adjusting the luminance parameter is taken as an example. The waveform provided to the first shift register group 11a is determined by the following three parameters: a period prid1 (which indicates a period of a second level pulse), a before-pulse duration ofst1 (which indicates an interval between a rising edge of a first second level pulse provided to the first shift register group 11a and a rising edge of the frame start signal Vsync of the current frame), and an after-pulse duration wid1 (which indicates a duration of a portion of the current period after a falling edge of the first second level pulse provided to the first shift register group 11a). The waveform provided to the first shift register group 11a is determined by the three above parameters no matter how the luminance parameter changes.
If the luminance parameters of two adjacent frames remain unchanged, the waveform provided to the second shift register group 11b for the latter frame of the two adjacent frames is determined by only the following three parameters: a period prid2 (which indicates a period of a second level pulse), a before-pulse duration ofst2 (which indicates an interval between a rising edge of a first second level pulse provided to the second shift register group 11b and a rising edge of the frame start signal Vsync of the current frame), and an after-pulse duration wid2 (which indicates a duration of a portion of the current period after a falling edge of the first second level pulse provided to the second shift register group 11b).
If the luminance parameters of two adjacent frames are different from each other, the waveform provided to the second shift register group 11b for the latter frame of the two adjacent frames is determined by the following six parameters: a first period prid2f (which indicates a period of each of first two second level pulses), a before-pulse duration ofst2f (which indicates an interval between a rising edge of a first second level pulse provided to the second shift register group 11b and a rising edge of the frame start signal Vsync of the current frame), and an after-pulse duration wid2f (which indicates a duration of a portion of the first period after a falling edge of the first second level pulse provided to the second shift register group 11b), and a second period prid2b (which indicates a period of each of last two second level pulses), a before-pulse duration ofst2b (which indicates an interval between a rising edge of a third second level pulse provided to the second shift register group 11b and an intermediate point in time of the current frame), and an after-pulse duration wid2b (which indicates a duration of a portion of the current period after a falling edge of the fourth second level pulse provided to the second shift register group 11b).
The meaning of the above parameters may be understood in conjunction with the reference symbols in
In this way, when the display panel 1 is driven to perform a full-screen display, the luminance parameters of the sub-display areas can be always identical in a same frame even if the luminance parameters change continuously.
The present embodiment provides a display device including a display panel 1 and a driving control circuit for providing a driving control signal to the display panel 1. The display panel 1 is the display panel 1 of Embodiment 1 of the present disclosure, and the driving control circuit is the driving control circuit of Embodiment 3 of the present disclosure.
Specifically, the display device may include any product or component with a display function, such as an Organic Light Emitting Diode (OLED) display circuit, a foldable mobile phone, a foldable tablet, and the like.
It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to those ordinarily skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these changes and modifications are considered within the scope of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201910208916.9 | Mar 2019 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2019/126284 | 12/18/2019 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2020/186849 | 9/24/2020 | WO | A |
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| 20090179875 | Li | Jul 2009 | A1 |
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| 20200051496 | Kang | Feb 2020 | A1 |
| 20200082762 | Takasugi | Mar 2020 | A1 |
| 20200082768 | Oh | Mar 2020 | A1 |
| 20200193911 | Lim | Jun 2020 | A1 |
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| 103208250 | Jul 2013 | CN |
| 105609045 | May 2016 | CN |
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| Entry |
|---|
| Office Action dated Jun. 3, 2020 issued in corresponding Chinese Application No. 201910208916.9. |
| Number | Date | Country | |
|---|---|---|---|
| 20210225276 A1 | Jul 2021 | US |
