Patent Application
20250209961
This application claims priority to Taiwan Application Serial Number 112150161, filed Dec. 21, 2023, which is herein incorporated by reference in its entirety.
The present disclosure relates to the control and driving of pixel circuits, especially a display panel, a driving controller and a pixel circuit driving method.
In various consumer electronic products, “reflective display device” is widely used in display screens, such as electronic paper display device. The reflective display device uses incident light to illuminate a display medium layer to achieve a display effect, and therefore save power. However, in order to balance the display capability and production cost of the reflective display device, there are still many parts that can be improved in the internal circuit structure and signal processing of the reflective display device.
One aspect of the present disclosure is a pixel circuit driving method, comprising: receiving an image signal by a control circuit, wherein the image signal comprises a plurality of pixel values; using a first lookup table to obtain a plurality of first voltage data corresponding to the plurality of pixel values in a first original frame; using a second lookup table to generate a plurality of first voltage combinations according to the plurality of first voltage data, wherein each of the plurality of first voltage combinations comprises a plurality of update voltages, and the plurality of first voltage combinations correspond to a plurality of first update frames; generating the plurality of update voltages to a plurality of driving multiplexing circuits according to each of the plurality of first voltage combinations by a plurality of power generating circuits; and using the plurality of update voltages as a plurality of driving voltages to provided to a plurality of pixel circuits by the plurality of power generating circuits.
Another aspect of the present disclosure is a driving controller, comprising a control circuit, a memory, multiple power generating circuits and multiple driving multiplexing circuits. The control circuit is configured to receive an image signal. The image signal comprises multiple pixel values. The memory is coupled to the control circuit, and records a first lookup table and a second lookup table. The first lookup table records a corresponding relationship between the pixel values and multiple voltage data. The control circuit is configured to use the first lookup table to obtain multiple first voltage data corresponding to the pixel values in a first original frame. The control circuit is configured to use the second lookup table to generate multiple first voltage combinations according to the multiple first voltage data. Each of the multiple first voltage combinations comprise multiple update voltages, and the multiple first voltage combinations correspond to multiple first update frames. The power generating circuits are coupled to the control circuit, and are configured to generate the update voltages according to each of the multiple first voltage combinations. The driving multiplexing circuits are coupled to the power generating circuits and multiple pixel circuits, and are configured to use the multiple update voltages generated by the multiple power generating circuits as multiple driving voltages to provided to the multiple pixel circuits.
Another aspect of the present disclosure is a display panel, comprising multiple pixel circuits and a driving controller. The driving controller is coupled to the multiple pixel circuits, and is configured to receive an image signal. The image signal comprises multiple pixel values, and the multiple pixel values corresponding to multiple voltage data in a first original frame. The driving controller is configured to convert the multiple voltage data into multiple voltage combinations in multiple update frames, and is configured to generate multiple driving voltages according to the multiple voltage combinations to drive the multiple pixel circuits.
Another aspect of the present disclosure is a display panel, comprising multiple pixel circuits and a driving controller. The driving controller is coupled to the multiple pixel circuits, and is configured to receive an image signal, wherein the image signal comprises multiple pixel values. The driving controller is configured to generate multiple driving voltages to drive the multiple pixel circuits in multiple update frames. At a same one of the multiple update frames, the multiple driving voltages provided by the driving controller comprises a reference voltage value and multiple symmetrical voltage groups. Each group of the plurality of symmetrical voltage groups comprises two voltage that have a same value but are positive and negative to each other.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
For the embodiment below is described in detail with the accompanying drawings, embodiments are not provided to limit the scope of the present disclosure. Moreover, the operation of the described structure is not for limiting the order of implementation. Any device with equivalent functions that is produced from a structure formed by a recombination of elements is all covered by the scope of the present disclosure. Drawings are for the purpose of illustration only, and not plotted in accordance with the original size.
It will be understood that when an element is referred to as being “connected to” or “coupled to”, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element to another element is referred to as being “directly connected” or “directly coupled,” there are no intervening elements present. As used herein, the term “and/or” includes an associated listed items or any and all combinations of more.
In one embodiment, the driving controller 100 is arranged in the display panel 200, and includes a control circuit 110, a memory 120, multiple power generating circuits 130 and multiple driving multiplexing circuits 140. The control circuit 110 can be a kind of timing controller, and is coupled to the receiving circuit 150 to receive the image signal. The image signal is configured to record data of static images or dynamic images, and includes multiple pixel values (e.g., grayscale value, between 0-255) corresponding to pixel circuits P. For ease of explanation, “image signal” described in subsequent paragraphs represents the image data used by the display panel 200 in an update period. The update period can be divided into one or more original frames. The image signal includes multiple pixel values corresponding to the pixel circuits P, and each pixel value corresponds to require voltage data in one or more original frames (e.g., voltage value, or a voltage code corresponding to the voltage value).
In one embodiment, the image signal can be transmitted by a host device (not shown in figure, such as computer, phone or server) to the driving controller 100. In other embodiments, the image signal can be generated by a processor of the reflective display device (e.g., electronic paper reader), and is transmitted to the receiving circuit 150.
The memory 120 is coupled to the control circuit 110, and the memory 120 includes a first lookup table TB1 and a second lookup table TB2. The first lookup table TB1 is configured to record a corresponding relationship between each pixel value and multiple voltage data, wherein “voltage data” may includes voltage value or voltage code. After the control circuit 110 receives the image signal, the control circuit 110 may obtain the voltage data corresponding to each pixel value according to the first lookup table TB1.
For example, the control circuit 110 convert the pixel value “150” into multiple voltage codes “010, 001, 000” (the combination of multiple voltage codes is called an “original encoding sequence”). This voltage codes corresponding to multiple original frames in sequence, such as “010, 001, 000”, and it means that the pixel circuit P must be applied with three different levels of voltage such as “3V, −3V, 0V” in the three original frames. The voltage code is a code used for identification, and its coding rules can be adjusted according to needs.
The second lookup table TB2 is configured to record a corresponding relationship between the voltage data (e.g., voltage code, voltage value or original encoding sequence) and multiple update encoding sequences. The update encoding sequence includes multiple converted voltage data, and corresponds to multiple update frames.
For example, one of the voltage code “010” in the above original encoding sequence “010, 001, 000” can be convert into three new voltage codes to represent, such as “000, 010, 000” (i.e., an update encoding sequence). The two other voltage codes in the original encoding sequence can be respectively converted into two update encoding sequences. Each update encoding sequence corresponds to one update frame. Therefore, the control circuit 110 converts each original encoding sequence into multiple update encoding sequences, and each original frame will correspond to multiple update frames. The detailed conversion method will be detailed in the subsequent paragraphs.
On the other hand, the process of “converting multiple original encoding sequences corresponding to multiple pixel values into multiple update encoding sequences by the driving controller 100” can be regard as the driving controller 100 converts voltage data corresponding to multiple pixel values into multiple voltage combinations corresponding to multiple update frames. Each voltage combination represents voltages with different levels (referred to here as “update voltages”) corresponding to a same update frame. In other words, the driving controller 100 uses multiple voltage codes corresponding to a same update frame in multiple update encoding sequence as one voltage combination, so as to drive pixel circuits P sequentially.
For example, after the control circuit 110 obtain the image signal, the control circuit 110 generates multiple voltage combinations according to multiple voltage data (e.g., multiple original encoding sequences) of the first original frame. Each voltage combination includes multiple update voltages, and respectively corresponds to one update frame.
The power generating circuit 130 is coupled to the control circuit 110, and is configured to generate multiple update voltages Vd1-Vd3 (e.g., three voltages) according to each voltage combination generated by the control circuit 110, so as to drive pixel circuits P. In one embodiment, a number of the power generating circuits 130 is equal to a number of voltage codes in the voltage combination, but less than a number of voltage codes in the same original frame.
The driving multiplexing circuit 140 is coupled to the power generating circuit 130 and the pixel circuits P, and is configured to use the update voltages Vd1-Vdn generated by the power generating circuit 130 as driving voltages Vs1-Vsn and apply to pixel circuits P. In one embodiment, during multiple update frames, each driving multiplexing circuit 140 receives the update voltages Vd1-Vdn generated by the power generating circuit 130. The driving multiplexing circuit 140 selects one of the update voltages as a driving voltage, and outputs the driving voltage (the selected update voltage) to the corresponding pixel circuit P.
Since the pixel value of each the pixel circuit P are not exactly the same, the required voltages are also different, in the common method, to complete the update in the original frame, the driving controller 100 needed to generate different levels of the driving voltages by a large number of power generating circuits 130. However, this will require configuring a large number of the power generating circuits 130, so the cost and size of the driving controller 100 will be difficult to control.
The present disclosure divides an original frame into multiple update frames, so the driving controller 100 can generate a less number of voltages in each update frame. Accordingly, there is no need to configure a large number of the power generating circuits 130. For example, in the common method, the image signal indicates that “one original frame need seven different driving voltages”, and thus it needs to arrange seven power generating circuits. In one embodiment of the present disclosure, the original frame is divided multiple update frames (e.g., three), so each update frame can only generate a few update voltages (e.g., three). Accordingly, during multiple update frames, this power generating circuits 130 sequentially updates seven pixel values corresponding to different driving voltages.
In other words, each update frame corresponds to one voltage combination, and each voltage combination includes multiple update voltages (e.g., three). The update voltage in each voltage combination are not exactly the same, but can be partly the same (e.g., all includes a reference voltage“0V”). Therefore, the number of the update voltage is equal to the number of the power generating circuits 130, but is less than the number of driving voltages corresponding to all pixel values (e.g., seven) in the same original frame.
In addition, during each update frame, the control circuit 110 is further configured to sequentially output multiple driving selection signals SA1-SAn to the driving multiplexing circuits according to the update encoding sequence corresponding to each pixel value (pixel circuit P), so that each driving multiplexing circuit 140 selectively uses one of the update voltage as the driving voltage according to the received driving selection signals SA1-SAn, and provides the driving voltage to the pixel circuit P.
For ease of understanding, the description of subsequent embodiments will be based on two methods of driving the pixel circuits P according to “original frame” of the common method, and driving the pixel circuits P according to “update frame” of the present disclosure.
Both of “voltage code” or “voltage value” can be used to the above voltage data. In some embodiments, although the driving controller 100 internally uses the voltage code as a signal for transmission, in other embodiments, the driving controller 100 may directly use the voltage value as a signal for transmission.
Similarly, taking the pixel value “85” as an example, the display panel finds the corresponding multiple voltage codes “001, 101, 000” (original encoding sequence) according to the first lookup table TB1 shown in
Similarly, taking the pixel value “6” as an example, the display panel finds the corresponding multiple voltage codes “011, 100, 000” (original encoding sequence) according to the first lookup table TB1 shown in
As mentioned in the previous embodiment, in order to simultaneously update the pixel values of multiple pixel circuits P, in the first original frame F01, the driving controller 100 must simultaneously provide multiple different levels of the driving voltage “3V, 2V, 1V”. In practical applications, hundreds or thousands of the pixel circuits P need to be updated in each original frame. Therefore, more driving voltages are required in each original frame. As a result, a large number of the power generating circuits 130 will be required, resulting in the cost of the display panel 200 being too high.
On the other hand, the control circuit 110 uses the second lookup table TB2 to convert each original encoding sequence into multiple update encoding sequences in multiple update frame, so as to control the power generating circuit 130 to sequentially generate the update voltage according to each update frame. In other word, the original encoding sequence in the same original frame will be converted to multiple update encoding sequences in multiple update frames.
For example, as shown in
Similarly, the voltage code “001” (corresponding to −3V) in the original frame F02 will be converted into an update encoding sequence “000, 001, 000” corresponding to multiple update frames F2A-F2C, such as voltage value “0V, −3V, 0V”. The voltage code “000” (corresponding to 0V) in the original frame F03 will be converted to an update encoding sequence “000, 000, 000” corresponding to multiple update frames F3A-F3C, such as update voltage “0V, 0V, 0V”.
Similarly, as shown in
For ease of understanding, the driving voltages required for the two methods of “driving according to original frames” and “driving according to update frames” is listed in a table as follows.
The following is the corresponding relationship between the pixel values and the voltage data when driving according to original frames. In one embodiment, the image signal is configured to indicate to update/display pixel values of multiple pixel circuits P (there are only four pixel values listed in the table).
The following is the corresponding relationship between the pixel values and the voltage data when driving according to update frames. In one embodiment, the image signal is configured to indicate to update/display pixel values of multiple pixel circuits P (there are only four pixel values listed in the table).
As mentioned above, the second lookup table TB2 includes a conversion relationship between the voltage data (e.g., the voltage code, the voltage value or the original encoding sequence) and multiple update encoding sequences. In one embodiment, “conversion relationship” can be a conversion formula or a conversion rule. For example, when converting the voltage values (or the voltage codes) corresponding to the same original frame into the voltage values corresponding to the update frames F1A-F1C, in addition to setting one of the voltage values to correspond to one of the update frames (e.g., 3V corresponds to the update frame F1A), other update frames are set to a reference voltage value (e.g., 0V corresponds to the update frames F1B, F1C). The number of voltage values corresponding to the same update frame must be equal to or less than “the number of the power generating circuits 130 in the driving controller 100”. In addition, the conversion rules may include an update encoding sequence, or a provided sequence of voltage values in the voltage combination. For example, in multiple update frames F1A-F1C, the required voltage values are arranged from high to low (e.g., 3V is generated during the update frame F1A, 2V is generated during the update frame F1B, and 1V is generated during the update frame F1C). The conversion relationship or conversion rules recorded by the second lookup table TB2 can be adjusted according to needs and are not limited to the above embodiment.
The present disclosure converts an original frame into multiple update frames, so the number of the update voltages Vd1-Vdn (or the driving voltages Vs1-Vsn) required in the same update frame will be reduced. Referring to
In the aforementioned embodiment, the common driving method of “original frame” needs to generate three driving voltages at the same time, while the driving method of “update frame” needs to generate two driving voltages at the same time. However, the foregoing embodiments are only simplified examples. In fact, the common driving method of “original frame” may require 5-10 or even more driving voltages in the same original frame. The driving method of “update frame” can provide only three driving voltages in the same update frame.
In one embodiment, in the update frame, the driving voltages Vs1-Vsn provided by the driving controller 100 includes a reference voltage value and multiple symmetrical voltage groups. Each group of symmetrical voltage groups comprises two voltages that have a same value but are positive and negative to each other. For example, the symmetrical voltage group corresponding to the update frame F1A includes “3V, 0V, −3V” (
In one embodiment, the control circuit 110 uses a part of “the voltage data corresponding to the same original frame” as the update voltages Vd1-Vdn to generate the driving voltages Vs1-Vsn, and a number of this part of the plurality of first voltage data is equal to a number of the plurality of power generating circuits 130 in the driving controller 100. As shown in the aforementioned table, the control circuit 110 selects “3V, 0V” from the voltage data “3V, 2V, 1V, 0V . . . ” corresponding to the original frame F01 as the update voltages corresponding to the update frame F1A. Similarly, the control circuit 110 further selects “2V, 0V” from the voltage data “3V, 2V, 1V, 0V . . . ” as the update voltages corresponding to the update frame F1B.
As mentioned above, in the same update frame, the voltage combination may not include voltages required by all pixel circuits P. Therefore, the driving controller 100 uses a reference voltage of the pixel circuits P as one of the update voltages.
For example, in the original frame F01, the driving voltage required for the pixel circuits P corresponding to the pixel value “85” is 2V. However, after the original frame F01 is converted into multiple update frames F1A-F1C, the driving controller 100 do not provide the update voltage of 2V during the update frame F1A. At this time, the driving controller 100 provides the reference voltage (i.e., 0V) to the pixel circuits P corresponding to the pixel value “85”. In other words, each voltage combination can include the reference voltage “0V”.
In one embodiment, the number (e.g., two) of the update voltages in each update frame is equal to the number of the power generating circuits 130, but this number is less than the number of the driving voltages required in the same original frame (as in the previous table, the driving voltages corresponding to the original frame F01 have four different levels “3V, 2V, 1V, 0V”).
Referring to
In some embodiments, the control circuit 110 further includes a sequential circuit 111, a data multiplexing circuit 112 and a shift register circuit 113. The sequential circuit 111 is coupled to the memory 120 and the receiving circuit 150, and is configured to obtain original encoding sequences corresponding to the pixel value, update encoding sequence and the voltage combination corresponding to each update frame according to the first lookup table TB1 and the second lookup table TB2. The sequential circuit 111 is further configured to sequentially generate multiple timing selection signals SB1-SBn according to the update encoding sequence during the update frames F1A-F3C. The timing selection signals SB1-SBn is configured to cause the driving multiplexing circuit 140 selectively outputs anyone of the driving voltage Vs1-Vs3 (i.e., outputs one of the update voltages Vd1-Vdn as the driving voltage) to the corresponding pixel circuit P.
The data multiplexing circuit 112 is coupled to the sequential circuit 111. During the update frames F1A-F3C, a selective terminal of the data multiplexing circuit 112 is configured to sequentially receive the timing selection signals SB1-SBn, and the input terminal of the data multiplexing circuit 112 receives the voltage combination corresponding to the current update frame (or receives all voltage values or all voltage codes corresponding to the original frame). The data multiplexing circuit 112 outputs multiple driving selection signals SA1-San according to the timing selection signals SB1-SBn. Each of the driving selection signals SA1-San corresponds to each of the driving multiplexing circuits 140. As shown in
The shift register circuit 113 (e.g., a shift register) is coupled to the data multiplexing circuit 112 and the driving multiplexing circuit 140, and is configured to allocate multiple driving selection signals SA1-SAn to the corresponding driving multiplexing circuit 140 respectively. During the update frames F1A-F1C, the driving multiplexing circuit 140 sequentially receives the update voltages generated by all power generating circuits 130, and uses one of the update voltages as the driving voltage according to the driving selection signals SA1-SAn to output the corresponding driving voltage to the corresponding pixel circuit P.
For example, during the first update frame F1A, the update voltage required by the pixel circuits P is 3V, and the update voltage provided by the power generating circuits 130 is 3V and 0V. The driving multiplexing circuit 140 receives all update voltages (3V, 0V) at the same time, but will only output an update voltage “3V” corresponding to the update encoding sequence according to the driving selection signals SA1-SAn.
In step S602, the sequential circuit 111 of the control circuit 110 uses the first lookup table TB1 to obtain multiple voltage data corresponding to the pixel values in each original frame, wherein each original frame corresponds to multiple voltage data. The first lookup table TB1 records a corresponding relationship between each pixel value and the voltage data, as shown in the previous table, the voltage data corresponding to the pixel value “120” in the original frame F01 can be a voltage code “010” or a voltage value “3V”.
In step S603, after obtaining the voltage data, the sequential circuit 111 of the control circuit 110 uses the second lookup table TB2 to generate multiple voltage combinations corresponding to multiple update frames according to the voltage data, and generate multiple update encoding sequences corresponding to multiple update frames according to each original encoding sequence. Each voltage combination includes multiple update voltages, and corresponds to multiple update frames.
“Generating the voltage combination” and “generating the updated encoding sequence” are two actions in one. In one embodiment, the sequential circuit 111 first generates the voltage combination corresponding to multiple update frames according to the original encoding sequence, then forms the update encoding sequence according to the update voltages corresponding to the same pixel value in multiple voltage combinations. In another embodiment, the sequential circuit 111 can first convert each original encoding sequence into multiple update encoding sequences respectively, and then use the update voltages corresponding to the same update frame in the update encoding sequences as the voltage combination. The update encoding sequences is configured to cause the power generating circuits generates the update voltages.
Specifically, in the step 602, the sequential circuit 111 first obtains multiple original encoding sequences corresponding to multiple pixel values, then uses a part of the original encoding sequences (i.e., the voltage codes corresponding to the same original frame) as the voltage data, so as to generate the voltage combination in the subsequent step S603. As shown in the previous table, the sequential circuit 111 uses multiple voltage codes or voltage values (e.g., “3V, 2V, 1V, 0V”) corresponding to the original frame F01 as the voltage data, so as to generate a voltage combination corresponding to the update frames F1A-F1C.
As mentioned above, the sequential circuit 111 uses a part of the voltage data as the update voltage, and a number of this part is equal to a number of the power generating circuits in the driving controller 100. As shown in the previous table, among the multiple driving voltages corresponding to the original frame F01, the driving controller 100 will use “3V, 0V” as the update voltage corresponding to the update frame F1A, and the update voltage includes the reference voltage of the pixel circuit P. The reference voltage is not limited to “0V”, it can also be other levels of voltage according to product requirements, such as 1V or 2V. Additionally, in one embodiment, all voltage combinations corresponding to all update frames F1A-F3C include the reference voltage value. In other words, update voltages in each of multiple first voltage combinations includes the reference voltage value.
In step S604, during the update frame, the sequential circuit 111 of the control circuit 110 generates multiple timing selection signals SB1-SBn to the selective terminal of the data multiplexing circuit 112 according to the update encoding sequence, and provides the voltage combination corresponding to the current update frame (or all voltage values or the voltage codes corresponding to the original frame) to the input terminal of the data multiplexing circuit 112, so that the data multiplexing circuit 112 generates the driving selection signals SA1-SAn. Each of driving selection signals SA1-San correspond to each of driving multiplexing circuits 140, and is configured to indicate that each driving multiplexing circuit 140 to select the required driving voltage according to each update encoding sequence during each update frame.
In step S605, the data multiplexing circuit 112 transmits the driving selection signals SA1-SAn to the corresponding driving multiplexing circuit 140 through the shift register circuit 113. The power generating circuit 130 generates the update voltage according to each voltage combination, and provides the update voltage to the driving multiplexing circuits 140. The driving multiplexing circuit 140 selectively uses one of the received update voltages as the driving voltage according to the driving selection signals SA1-San, and outputs the driving voltage to the corresponding pixel circuit P. At the same time, the driving controller 100 transmits the scanning signal to the control line GL through the scanning controller GD to turn on the corresponding pixel circuit. Accordingly, the pixel circuits P can sequentially receive the driving voltages during the update frames and can display the pixel value expected by the image signal.
The elements, method steps, or technical features in the foregoing embodiments may be combined with each other, and are not limited to the order of the specification description or the order of the drawings in the present disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this present disclosure provided they fall within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112150161 | Dec 2023 | TW | national |
