Patent Application
20210295788
The present invention relates to a display panel driving method and a display panel driving circuit, and more particularly, to a display panel driving method and a display panel driving circuit so as to eliminate flicker or line afterimage and ensure high display quality.
Different alignments of liquid crystals result in different polarization and refraction effects on light passing through the liquid crystals. Thus, light transmission ratios may be controlled in a liquid crystal display device by adjusting the alignments of the liquid crystals. On the other hand, each liquid crystal must be driven by a subpixel voltage of a periodically alternating voltage polarity, which is the so-called voltage polarity inversion driving, so as to avoid permanently damages on the liquid crystals due to deformation and effects of ion trapping and direct current residue.
In a liquid crystal display device, although a common voltage is in the middle of a voltage range between a data signal with negative voltage polarity and a data signal with positive voltage polarity, the difference between a subpixel voltage with negative voltage polarity for a subpixel and the common voltage differs from the difference between a subpixel voltage with positive voltage polarity for the subpixel and the common voltage due to the occurrence of feed through phenomenon. The subpixel voltage of the subpixel may shift from the data signal by a feed through voltage. Flickering occurs and causes deterioration in display quality when the subpixel is subject to the subpixel voltage periodically alternating between positive voltage polarity and negative voltage polarity but the common voltage is not equal to the average of the subpixel voltage with positive voltage polarity and subpixel voltage with negative voltage polarity.
Manufacture processes may cause different feed through voltages of the subpixels at different positions. As the feed through voltages vary from one subpixel to another, it may be difficult to eliminate flicker. Even if the common voltage for all the subpixels equals the average of the subpixel voltage with positive voltage polarity and the subpixel voltage with negative voltage polarity of the subpixel at the center of the liquid crystal display device, the feed through phenomenon cannot be cancelled out uniformly within the liquid crystal display device. The display quality in other areas may be worse than that in the middle area, leading to unevenness in display quality.
Besides, Please refer to
In order to solve aforementioned problem(s), the present invention provides a display panel driving method and a display panel driving circuit of high display quality so as to eliminate flicker or line afterimage and ensure high display quality.
The present invention discloses a display panel driving circuit for driving a plurality of subpixels of a display panel. The display panel driving circuit includes a compensation circuit. The compensation circuit is configured to convert a first input gray level data into a first output gray level data corresponding to a first data signal for a first subpixel of the plurality of subpixels. The first subpixel is located in a first zone of a plurality of zones of the display panel. A first difference between the first input gray level data and the first output gray level data is associated with a first voltage polarity of the first data signal or the first zone.
The present invention discloses a display panel driving method for driving a plurality of subpixels of a display panel. The display panel driving method includes converting a first input gray level data into a first output gray level data corresponding to a first data signal for a first subpixel of the plurality of subpixels. The first subpixel is located in a first zone of a plurality of zones of the display panel. A first difference between the first input gray level data and the first output gray level data is associated with a first voltage polarity of the first data signal or the first zone.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the following description and claims to refer to particular components. Manufacturers may refer to a component by different names as one skilled in the art may appreciate. Therefore, components shall be distinguished according to function instead of name. In the following description and claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, the connection may belong to a direct electrical connection or an indirect electrical connection via other devices and connections.
Please refer to
The driving circuit 120 for driving the subpixels PX11-PXnm may include a timing controller 122, a gate driving circuit 124 and a data driving circuit 126. The timing controller 122 is coupled to the gate driving circuit 124 and the data driving circuit 126. The timing controller 122 is configured to provide operation signals (such as a polarity signal and timing signals) to the gate driving circuit 124 and the data driving circuit 126 so as to control operations of the gate driving circuit 124 and the data driving circuit 126. The gate driving circuit 124 is configured to generate a plurality of gate driving signals G1-Gn according to part of the operation signals and transmit the gate driving signals G1-Gn to the gate lines GL1-GLn so as to enable the transistors TRS of the subpixels PX11-PXnm row by row. The data driving circuit 126 is configured to send data signals D1-Dm to the data lines DL1-DLm according to part of the operation signals so as to transmit the data signals D1-Dm to the corresponding subpixels PX11-PXnm.
Please refer to
Step 300: Start.
Step 302: Convert a first input gray level data into a first output gray level data corresponding to a first data signal for a first subpixel of the plurality of subpixels, wherein the first subpixel is located in a first zone of a plurality of zones of the display panel, wherein a first difference between the first input gray level data and the first output gray level data is associated with a first voltage polarity of the first data signal or the first zone.
Step 304: End.
Briefly, the timing controller 122 may include a compensation circuit 1221, which is configured to convert an input gray level data DgI1 into an output gray level data DgO1, which corresponds to a data signal (for example, the data signal D1) for a subpixel (for example, the subpixels PX21) located in a zone (for example, the zone ZN11) of the display panel 100. A difference (also referred to as a compensation difference) between the input gray level data DgI1 and the output gray level data DgO1 is associated with a voltage polarity of the data signal (namely, the data signal D1 with negative or positive voltage polarity) or the zone (namely, the zone ZN11). In other words, compensation differences for the subpixels PX11-PXnm are functions of the locations of the subpixels PX11-PXnm respectively. The compensation differences for a subpixel (for example, the subpixels PX21) vary according to whether the data signal (for example, the data signal D1) for the subpixel (for example, the subpixels PX21) has negative or positive voltage polarity.
Please refer to
Take the subpixel PX21 as an example. The data line DL1 transmits the data signal D1 of a gray-level voltage Vp1 from the data driving circuit 126 to the subpixels PX11-PXn1 during the frame period FP1a. The gray-level voltage Vp1 is higher than the common voltage VCOM so that the voltage polarity of the data signal D1 is positive. The subpixels PX21-PX2m connected to the gate lines GL2 are simultaneously turned on when the gate line GL2 is selected with the gate driving signal G2 during a time interval TT1a. A subpixel voltage Vpx21 of the subpixel PX21 reaches the gray-level voltage Vp1 during the time interval TT1a, but drops to a gray-level voltage Vp2 after the time interval TT1a due to the feed through phenomenon. Similarly, the data line DL1 transmits the data signal D1 of a gray-level voltage Vn1 from the data driving circuit 126 to the subpixels PX11-PXn1 during the frame period FP2a. The gray-level voltage Vn1 is lower than the common voltage VCOM so that the voltage polarity of the data signal D1 is negative. The subpixels PX21-PX2m connected to the gate lines GL2 are simultaneously turned on when the gate line GL2 is selected with the gate driving signal G2 during a time interval TT2a. The subpixel voltage Vpx21 of the subpixel PX21 reaches the gray-level voltage Vn1 during the time interval TT2a, but drops to a gray-level voltage Vn2 after the time interval TT2a due to the feed through phenomenon.
In terms of the subpixel voltage Vpx21 shown in
The (first) input gray level data involves a gray level corresponds to a data signal to be adjusted (for example, the data signal D1 without compensation) or a subpixel voltage after adjustments (for example, the subpixel voltage Vpx21) by the compensation circuit 1221. The (first) output gray level data involves a gray level corresponds to a data signal after adjustments (namely, the current gray-level voltage of the data signal D1) by the compensation circuit 1221. When the data signal D1 with positive voltage polarity is changed from the gray-level voltage Vp2 to the gray-level voltage Vp1, the gray level rises. Correspondingly, the (first) input gray level data is increased to the (first) output gray level data. Likewise, the (second) input gray level data involves a gray level corresponds to a data signal to be adjusted (for example, the data signal D1) or a subpixel voltage after compensation (for example, the subpixel voltage Vpx21) by the compensation circuit 1221. The (second) output gray level data involves a gray level corresponds to a data signal after compensation (namely, the current gray-level voltage of the data signal D1) by the compensation circuit 1221. Nevertheless, when the data signal D1 with negative voltage polarity rises from the gray-level voltage Vn2 to the gray-level voltage Vn1, the gray level drops. Correspondingly, the (second) input gray level data is decreased to the (second) output gray level data. The first input gray level data may equal the second input gray level data; however, the first output gray level data and the second output gray level data are compensated individually.
That is to say, as the voltage polarity of the data signal D1 of the gray-level voltage Vp1 (regarded as a first data signal), which corresponds to the (first) output gray level data, is opposite to the voltage polarity of the data signal D1 of the gray-level voltage Vn1 (regarded as a second data signal), which corresponds to the (second) output gray level data, the (first) compensation difference between the (first) input gray level data and the (first) output gray level data corresponding to positive voltage polarity is different from the (second) compensation difference between the (second) input gray level data and the (second) output gray level data corresponding to negative voltage polarity. Accordingly, the (first) compensation difference or/and the (second) compensation difference is/are associated with the voltage polarity of the data signal D1, thereby improving display quality.
It should be noted that the driving method 30 is an exemplary embodiment of the present invention, and those skilled in the art may readily make different alternations and modifications. For instance, the (first) compensation difference corresponding to positive voltage polarity or/and the (second) compensation difference corresponding to negative voltage polarity may be associated with the current (gray-level) voltage (namely, the gray-level voltage Vp1 or Vn1) of the data signal (namely, the data signal D1). It is because current gray level has an influence on the feed through voltage. Therefore, a data signal (for example, the data signal D1) may be modified according to its current (gray-level) voltage, such that the average of the subpixel voltage (for example, the gray-level voltage Vp2) of a subpixel (for example, the subpixel PX21) with positive voltage polarity and the subpixel voltage (for example, the gray-level voltage Vn2) of the subpixel (namely, the subpixel PX21) with negative voltage polarity for each gray level is equal to that for another gray level (namely, the average of the subpixel voltage of the subpixel with positive voltage polarity and the subpixel voltage of the subpixel with negative voltage polarity for another gray level) after the compensation of the compensation circuit 1221. No matter which gray level a subpixel (for example, the subpixel PX21) is at, the (first) output gray level data or the (second) output gray level data, which is/are associated with a current (gray-level) voltage (for example, the gray-level voltage Vp1 or Vn1) of a data signal (for example, the data signal D1), is converted from the (first) input gray level data or the (second) input gray level data according to the current (gray-level) voltage (namely, the gray-level voltage Vp1 or Vn1) of the data signal (namely, the data signal D1), thereby improving display quality.
In some embodiments, the (first) compensation difference(s) corresponding to positive voltage polarity or/and the (second) compensation difference(s) corresponding to negative voltage polarity may be associated with a zone (for example, the zone ZN11) in which a subpixel (for example, the subpixel PX21) is located. Please refer to
In
If waveforms of the subpixel voltages of all the subpixels PX11-PXnm are to be symmetric or balanced with respect to the common voltage VCOM, the compensation circuit 1221 must convert input gray level data (for example, the input gray level data DgI1), which may correspond to the subpixel voltages of the subpixels PX11-PXnm, into output gray level data (for example, the output gray level data DgO1), which corresponds to the data signals for all the subpixels PX11-PXnm. Since manufacturing process may cause feed through voltages of the subpixels PX11-PXnm vary from one to another, the (first) compensation difference(s) corresponding to positive voltage polarity or/and the (second) compensation difference(s) corresponding to negative voltage polarity may be associated with the zones ZN11-ZNij in which the subpixels PX11-PXnm are located.
For instance, if a zone ZNkc is located in (or near) a center of the display panel 100, the (first) compensation difference(s) corresponding to positive voltage polarity or/and the (second) compensation difference(s) corresponding to negative voltage polarity for the zone ZNkc may be equal or close to zero. It is because the common voltage VCOM for all the subpixels PX11-PXnm is moved to the middle of the subpixel voltage with positive voltage polarity and subpixel voltage with negative voltage polarity of the subpixel (s) in the zone ZNkc. In
On the other hand, if a zone (for example, the zone ZN11 or ZNij) is located near four outermost sides of the display panel 100, the (first) compensation difference(s) corresponding to positive voltage polarity or/and the (second) compensation difference(s) corresponding to negative voltage polarity may be nonzero. In
In some embodiments, the timing controller 122 is modified for the compensation of the compensation circuit 1221. Please refer to
In some embodiments, the look-up table LUT may store a (first) compensation difference of a data signal (for example, the data signal D1) with positive voltage polarity and a (second) compensation difference of the data signal (namely, the data signal D1) with negative voltage polarity. Correspondingly, exact values of compensation differences CDF(0)-CDF(255) listed in Table 1 and exact values of compensation differences CDR(0)-CDR(224) listed in Table 2 may be determined according to voltage polarity. In some embodiments, the look-up table LUT may store (first) compensation differences of the data signal (namely, the data signal D1) with positive voltage polarity but different gray levels, and store (second) compensation differences of the data signal (namely, the data signal D1) with negative voltage polarity but different gray levels. Correspondingly, the exact values of the compensation differences CDF(0)-CDF(255) listed in the second row of Table 1 may be determined according to input gray level data listed in the first row of Table 1. The gray levels may be 256 gradations for display module 10 to render images, but is not limited thereto. In some embodiments, the look-up table LUT may store (first) compensation differences of the data signal (namely, the data signal D1) with positive voltage polarity but different gray level ranges such as 0-31, 32-63, . . . , 224-255, and store (second) compensation differences of the data signal (namely, the data signal D1) with negative voltage polarity but different gray level ranges such as 0-31, 32-63, . . . , 224-255. Correspondingly, the exact values of the compensation differences CDR(0)-CDR(224) listed in the second row of Table 2 may be determined according to gray level ranges of the input gray level data listed in the first row of Table 2.
In some embodiments, the look-up table LUT may store the (first) compensation differences and the (second) compensation differences for all the zones ZN11-ZNij. Correspondingly, the exact values of the compensation differences CDF(0)-CDF(255) listed in Table 1 and the exact values of the compensation differences CDR(0)-CDR(224) listed in Table 2 may be determined according to a zone (for example, the zone ZN11) in which a subpixel (for example, the subpixel PX21) is located. In some embodiments, the timing controller 122 is able to recognize which zone each of the subpixels PX11-PXnm is located in and which voltage polarity each of the subpixels PX11-PXnm corresponds to according to the operation signals (such as the polarity signal Sp1 and the timing signals). In some embodiments, the (first) input gray level data is converted into the (first) output gray level data according to one of positive compensation lookup tables of the look-up table LUT for positive voltage polarity. The (second) input gray level data is converted into the (second) output gray level data according to one of negative compensation lookup tables of the look-up table LUT for negative voltage polarity. One of the negative compensation lookup tables and one of the positive compensation lookup tables are associated with one of the zones ZN11-ZNij.
As the (first) input gray level data or the (second) input gray level data is converted to the (first) output gray level data or the (second) output gray level data according to the look-up table LUT, flicker disappears.
To eliminate line afterimage, in some embodiments, the look-up table LUT may store the (first) compensation differences and the (second) compensation differences corresponding to a previous input gray level data. In other words, the (first) compensation difference (s) corresponding to positive voltage polarity or/and the (second) compensation difference(s) corresponding to negative voltage polarity may be associated with a previous (gray-level) voltage of the data signal (for example, the data signal D1). Please refer to Table 3 and Table 4. Table 3 and Table 4 list possible elements of a look-up table LUT respectively. Exact values of compensation differences CDF(0,0)-CDF(255,255) listed in Table 3 may be determined according to the next input gray level data listed in the topmost row of Table 3 and the previous input gray level data listed in the leftmost column of Table 3. Exact values of compensation differences CDR(0,0)-CDR(224,224) listed in Table 4 may be determined according to gray level ranges of the next input gray level data listed in the topmost row of Table 4 and gray level ranges of the previous input gray level data listed in the leftmost column of Table 4. As set forth above, the exact values of the compensation differences CDF(0,0)-CDF (255, 255) listed in Table 3 and the exact values of the compensation differences CDR (0, 0)-CDR (224, 224) listed in Table 2 may be determined according to voltage polarity.
In addition, the exact values of the compensation differences CDF(0,0)-CDF(255,255) listed in Table 3 and the exact values of the compensation differences CDR(0,0)-CDR(224,224) listed in Table 4 may be determined according to a zone (for example, the zone ZN11) in which a subpixel (for example, the subpixel PX21) is located. Specifically, please refer to
As shown in
Likewise, the data signals D1-Dm sent to the subpixels PX21-PX2m decreases from the gray-level voltage Vn1 (also referred to as a previous voltage) for the adjacent subpixels PX11-PX1m to a gray-level voltage Vnh (also referred to as a current voltage) during the time interval TT2b of the frame period FP2b—for instance, from black to white. Since the subpixel voltage Vpx21 of the subpixel PX21 reaches the gray-level voltage Vnh during the time interval TT2b and ensures the brightness of the subpixel PX21 as expected, there is no need to compensate the subpixel voltage Vpx21. That is to say, considering the zone ZN11 in which the subpixel PX21 is located and the previous gray-level voltage Vn1 of the data signal D1, the (second) compensation difference between the (second) input gray level data and the (second) output gray level data, which corresponds to the current gray-level voltage Vnh of the data signal D1, with negative voltage polarity may be equal or close to zero. Alternatively, the compensation circuit 1221 may not convert the (second) input gray level data into the (second) output gray level data.
As shown in
On the other hand, the data signals D1-Dm sent to the subpixels PXx1-PXxm decreases from the gray-level voltage Vn1 (also referred to as a previous voltage) for the adjacent subpixels PX11-PX (x−1)m to a gray-level voltage (also referred to as a current voltage) higher than the gray-level voltage Vnh during the time interval TT2c of the frame period FP2b. Compared to the subpixels PX21-PX2m, the subpixels PXx1-PXxm are disposed far from the data driving circuit 126. As shown in
As shown in
On the other hand, the data signals D1-Dm sent to the subpixels PX(n−1)1-PX(n−1)m decreases from the gray-level voltage Vn1 (also referred to as a previous voltage) for the adjacent subpixels PX11-PX(n−2)m to a gray-level voltage (also referred to as a current voltage) much higher than the gray-level voltage Vnh during the time interval TT2d of the frame period FP2b. Compared to the subpixels PX21-PX2m, the subpixels PX(n−1)1-PX(n−1)m are disposed far from the data driving circuit 126. As shown in
To sum up, the compensation differences for a subpixel may be functions of the location of the subpixel. The compensation differences fora subpixel may be affected by the current (gray-level) voltage of the data signal for the subpixel. The compensation differences for the subpixel may vary according to whether the data signal for the subpixel has negative or positive voltage polarity in order to eliminate flicker. The compensation differences for the subpixel may be associated with a previous (gray-level) voltage of the data signal for another adjacent subpixel in order to eliminate line afterimage.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
