Display panel driving method

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for driving a plasma display panel in a matrix display scheme.

[0003] 2. Description of the Related Art

[0004] At present, as thin display devices, AC (alternate current discharge) type plasma display panels (hereinafter referred to as the “PDP”) are commercially available in the market.

[0005] The AC type PDP comprises a plurality of column electrodes and a plurality of pairs of row electrodes which are arranged orthogonal to the column electrodes and form respective scanning lines in pair. The respective row electrode pairs and column electrodes are covered with a dielectric material defining a discharge space, and are constructed to form a discharge cell corresponding to one pixel at the intersection of each row electrode pair and each column electrode. In this event, since the PDP utilizes a discharge phenomenon, the discharge cells only have two states, i.e., a “light emission” state and a “non-light emission” state. Thus, a subfield method is typically employed to realize gradation luminance representations in the PDP.

[0006] In the subfield method, one field display period is made up of N subfields each of which corresponds to each of N bits in pixel data corresponding to an input video signal. Each of these N subfields is allocated a number of times of light emission (a light emission period) corresponding to a weighting for each bit digit in the pixel data to drive each discharge cell to emit light.

[0007]
FIG. 1 is a diagram generally illustrating the configuration of a plasma display device which employs the subfield method as mentioned to drive the PDP in gradation representation.

[0008] In FIG. 1, a driver 100 converts an input video signal to digital pixel data corresponding to each of pixels, and applies pixel data pulses corresponding to the pixel data to column electrodes D1-Dm of a PDP 10 which is employed as a plasma display panel. The driver 100 further applies a variety of driving pulses as described below to row electrodes X1-Xn and Y1-Yn. One display line of the PDP 10 is comprised of a pair of row electrodes X, Y which are formed to intersect the column electrodes D1-Dm, respectively. These column electrodes and row electrodes are formed with a dielectric material, not shown, interposed therebetween, and one pixel cell is formed at an intersection of a column electrode with a row electrode pair.

[0009]
FIG. 2 is a diagram illustrating an example of a light emission driving format with which the driver 100 drives the DPD in one field period.

[0010] In the light emission driving format illustrated in FIG. 2, one field display period is divided into four subfields SF1-SF4. Then, in each of the subfields, a simultaneous reset process Rc, a pixel data writing process Wc, a light emission sustaining process Ic, and an erasure process E are performed, respectively.

[0011]
FIG. 3 illustrates application timings (within one subfield) at which the driver 100 applies the column electrodes and row electrode pairs of the PDP 10 with a variety of driving pulses for performing each of the processes.

[0012] First, in the simultaneous reset process Rc, the driver 100 simultaneously applies a reset pulse RPX of negative polarity and a reset pulse RPY of positive polarity to the row electrodes X1-XN and Y1-YN, respectively. In response to the applied reset pulses RPX and RPY, all discharge cells in the PDP 10 are discharged or reset to uniformly form a wall charge of a predetermined amount within the respective discharge cells. In this way, all the discharge cells are once initialized to “light emitting cells.”

[0013] Next, in the pixel data writing process Wc, the driver 100 first converts an input video signal to 4-bit pixel data. The first bit of the pixel data is used in the pixel data writing process Wc in the subfield SF1; the second bit in SF2; the third bit in SF3; and the fourth bit in SF4, respectively, and the following processing is performed. For example, in the pixel data writing process Wc in the subfield SF1, a pixel data pulse at a high voltage is generated when the first bit of pixel data is at logical level “1”, and the pixel data pulse at a low voltage (zero volt) is generated when the first bit is at logical level “0.” Then, the driver 100 sequentially applies the column electrodes D1-Dm as illustrated in FIG. 3 with a group of pixel data pulses PD1, PD2, PD3, . . . , PDn, each of which is comprised of m pixel data pulses, each corresponding to the first to n-th display lines in the PDP 10. Further, the driver 100 generates a scanning pulse SP of negative polarity as illustrated in FIG. 3 and sequentially applies the scanning pulse SP to the row electrodes Y1-Yn at the same timing at which the group of pixel data pulses DP are each applied. Here, a discharge occurs only in discharge cells at intersections of the “rows” applied with the scanning pulse SP with the “columns” applied with the pixel data pulses at the high voltage (selective erasure discharge), thereby selectively erasing the wall charges which have remained in the discharge cells. The selective erasure discharge as mentioned causes the discharge cells initialized to “light emission cells” in the simultaneous reset process Rc to transition to “non-light emitting cells.” On the other hand, the selective erasure discharge does not occur in discharge cells which has been applied with the pixel data pulse at the low voltage simultaneously with the scanning pulse SP, so that these cells maintain the state of “light emitting cells.”

[0014] Next, in the light emission sustain process Ic, the driver 100 alternately applies the row electrodes X1-Xn and Y1-Yn with sustain pulses IPX and IPY as illustrated in FIG. 3. Here, the number of times (period) the sustain pulses IPX and IPY are applied in each light emission sustaining process Ic has been set corresponding to a weighting factor allocated to each subfield.

[0015] For example, as illustrated in FIG. 2, the driver 100 repeatedly applies the row electrodes X1-Xn and Y1-Yn with the sustain pulses IPX and IPY the following number of times (period) in continuation:

[0016] SF1: 1

[0017] SF2: 2

[0018] SF3: 4

[0019] SF4: 8

[0020] In this event, only discharge cells in which the wall charges remain after the end of the pixel data writing process Wc, i.e., the “light emitting cells” discharge to emit light each time they are applied with the sustain pulses IPX and IPY to sustain the light emitting state the number of times (period) as mentioned above.

[0021] Next, in the erasure process E, the driver 100 applies the row electrodes X1-Xn with an erasure pulse EP as illustrated in FIG. 3 to simultaneously discharge all the discharge cells for erasure, thereby erasing the wall charges remaining in the respective discharge cells.

[0022]
FIG. 4 is a table showing all possible patterns of light emission driving performed within one field period in a gradation driving mode which utilizes the subfield method.

[0023] For example, when a video signal corresponding to luminance “5” (corresponding to pixel data “0101”) is supplied, light is emitted in subfields SF1 and SF3 within SF1-SF4 as illustrated in FIG. 4. In this way, light is emitted once in SF1 and four times in SF3, i.e., a total of five times, so that an intermediate luminance corresponding to the luminance “5” is viewed. In other words, an intermediate luminance display at 16 gradation levels is implemented in a luminance range from luminance “0” to luminance “15” as shown in FIG. 4 by the gradation driving mode using the four subfields SF1-SF4, as described above.

[0024] In this event, as one field display period is divided into an increased number of subfields, a display image of higher quality is provided. Also, as the number of times the sustain pulses are applied is increased generally in each light emission sustain process Ic, a higher luminance display can be achieved.

[0025] However, since one field display period is regulated, it is not possible to thoughtlessly increase the number of times the sustain pulses are applied in each light emission sustain process Ic and the number of subfields into which one field display period is divided.

OBJECT AND SUMMARY OF THE INVENTION

[0026] It is an object of the present invention to provide a method of driving a plasma display panel which is capable of increasing the number of gradation levels or the luminance in driving the plasma display panel to display in gradation representation using the subfield method.

[0027] A display panel driving method according to the present invention is provided for driving a display panel having pixel cells formed at each of intersections of a plurality of row electrodes corresponding to display lines with a plurality of column electrodes arranged to intersect the row electrodes to provide a display in gradation representation in accordance with a video signal. The method performs, in each of a plurality of divided display periods of a unit display period in the video signal, a pixel data writing process for setting each of the pixel cells to either a light emitting cell or a non-light emitting cell in accordance with pixel data corresponding to the video signal to write the pixel data, and a light emission sustain process for causing only the light emission cells to emit light a number of times of light emission allocated thereto corresponding to a weighting factor applied to each of the divided display periods. The pixel data of every display line is sequentially written into each of the pixel cells on display lines belonging to a first display region in a display screen on the display panel, whereas for each of the pixel cells on display lines belonging to a second display region in the display screen, the writing of the pixel data is stopped, or the pixel cells are simultaneously set into the non-light emitting cell state.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]
FIG. 1 is a schematic diagram generally illustrating the configuration of a plasma display device;

[0029]
FIG. 2 is a diagram illustrating an example of a light emission driving format based on a subfield method;

[0030]
FIG. 3 is a waveform diagram showing exemplary application timings at which driving pulses are applied to a PDP 10;

[0031]
FIG. 4 is a table showing exemplary light emission driving patterns in accordance with the subfield method;

[0032]
FIG. 5 is a block diagram illustrating the configuration of a plasma display device which drives a plasma display panel in accordance with a driving method according to the present invention;

[0033]
FIG. 6 is a diagram showing flag registers FR1-FRn;

[0034]
FIGS. 7 and 8 are diagrams illustrating a first light emission driving format and a second light emission driving format, respectively, based on the driving method according to the present invention;

[0035]
FIG. 9 is a waveform diagram showing application timings at which a variety of driving pulses are applied to the PDP 10 in accordance with the first light emission driving format;

[0036]
FIG. 10 is a table showing a correspondence of light emission patterns in accordance with pixel data PD to intermediate luminance levels generated by the respective light emission patterns;

[0037]
FIG. 11 is a waveform chart showing application timings at which a variety of driving pulses are applied to the PDP 10 in accordance with the second light emission driving format;

[0038]
FIGS. 12 and 13 are diagrams illustrating a first light emission driving format and a second light emission driving format, respectively, when a selective erasure address method is employed;

[0039]
FIG. 14 is a waveform diagram showing application timings at which a variety of driving pulses are applied to the PDP 10 in accordance with the first light emission driving format illustrated in FIG. 12;

[0040]
FIG. 15 is a waveform diagram showing application timings at which a variety of driving pulses are applied to the PDP 10 in accordance with the second light emission driving format illustrated in FIG. 13;

[0041]
FIG. 16 is a block diagram illustrating another configuration of a plasma display device for driving a plasma display panel based on the driving method according to the present invention;

[0042]
FIG. 17 is a block diagram illustrating the internal configuration of a data converting circuit 50;

[0043]
FIG. 18 is a diagram showing a conversion table for a data converting circuit 51 and intermediate luminance levels which are generated for the respective light emission driving patterns;

[0044]
FIG. 19 is a diagram showing a conversion table for a data converting circuit 53 and intermediate luminance levels which are generated for the respective light emission driving patterns;

[0045] FIGS. 20 to 22 are diagrams illustrating a first light emission driving format to a third light emission driving format used in the plasma display device illustrated in FIG. 16;

[0046]
FIG. 23 is a waveform diagram showing application timings at which a variety of driving pulses are applied to the PDP 10 in accordance with the first light emission driving format illustrated in FIG. 20;

[0047]
FIG. 24 is a waveform diagram showing application timings at which a variety of driving pulses are applied to the PDP 10′ in accordance with the second light emission driving format illustrated in FIG. 20 and the third light emission driving format illustrated in FIG. 22;

[0048]
FIG. 25 is a diagram showing an upper display region GUP and a lower display region GDW in which low gradation number driving is performed, and a central display region GCN in which high gradation number driving is performed; and

[0049]
FIG. 26 is a waveform diagram showing an exemplary modification to the driving scheme shown in FIG. 25.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] In the following, embodiments of the present invention will be described with reference to the accompanying drawings.

[0051]
FIG. 5 is a block diagram illustrating the configuration of a plasma display device which drives a plasma display panel in gradation representation in accordance with a driving method according to the present invention.

[0052] As illustrated in FIG. 5, the plasma display device comprises a PDP 10 as a plasma display panel and a variety of functional modules for driving the PDP 10.

[0053] The PDP 10 comprises m column electrodes D1-Dm as address electrodes, and n row electrodes X1-Xn and row electrodes Y1-Yn which are arranged to intersect these column electrodes. In the PDP 10, a row electrode for one line of the screen is formed of a pair of a row electrode X and a row electrode Y. The column electrode D and the low electrode pairs X, Y are covered with a dielectric layer defining a discharge space, and a discharge cell corresponding to one pixel is formed at an intersection of each row electrode pair with each column electrode.

[0054] A synchronization detector circuit 1 generates a vertical synchronization detecting signal V when it detects a vertical synchronization signal from an input video signal, and supplies the signal V to a drive control circuit 2. Further, the synchronization detector circuit 1 generates a horizontal synchronization detecting signal H when it detects a horizontal synchronization signal from the input video signal, and supplies the signal H to each of the drive control circuit 2 and a black display line detector circuit 30.

[0055] An A/D converter 3 samples the input video signal for conversion to a 4-bit pixel data PD, for example, representative of a luminance level for each pixel, and supplies the pixel data PD to each of the black display line detector circuit 30 and a memory 4.

[0056] The black display line detector circuit 30 accumulates the pixel data PD every display line, and determines that a display line has a luminance level “0,” i.e., a black display line when the result of accumulation for the display line is “0.” Then, the black display line detector circuit 30 supplies the drive control circuit 2 with a black display line signal LZ indicative of the number of a display line which is determined as a black display line.

[0057] The drive control circuit 2 is equipped with flag registers FR1-FRn corresponding to first to n-th display lines, respectively, in the PDP 10, as shown in FIG. 6. These flag registers FR1-FRn, store logical level “0” as an initial value. When the drive control circuit 2 is supplied with the black display line signal LZ as mentioned above from the black display line detector circuit 30, the drive control circuit 2 rewrites the contents of the flag register RF corresponding to a display line indicated by the supplied black display line signal LZ to logical level “1.” The drive control circuit 2 initializes the contents stored in each of the flag registers FR1-FRn to logical level “0” each time an update operation for the flag registers FR1-FRn, is completed for the pixel data PD of one screen.

[0058] Further, the drive control circuit 2 supplies the memory 4 with a write signal for writing the pixel data PD, and also supplies the memory 4 with a read address and a read signal for sequentially reading pixel data written into the memory 4 from those belonging to a first display line to those belonging to an n-th display line. However, if any of the flag registers FR1-FRn, stores logical level “1,” the drive control circuit 2 does not generate a read address for reading pixel data belonging to a display line corresponding to the flag register. In other words, the drive control circuit 2 inhibits pixel data corresponding to a display line determined as displaying a black image at luminance level “0” from being read from the memory 4.

[0059] The memory 4 sequentially stores the pixel data PD supplied from the A/D converter 3 in response to the write signal supplied from the drive control circuit 2. Then, the memory 4 performs a read operation as described below when it finishes writing one screen of pixel data, i.e., (nxm) pixel data PD from pixel data PD11 corresponding to a pixel at the first row, first column to pixel data PDnm corresponding to a pixel at an n-th row, m-th column.

[0060] First, the memory 4 regards the first bit of each pixel data PD11-PDnm as a drive pixel data bit DB111-DBnm, and reads these drive pixel data bits on a display line basis in accordance with the read address supplied from the drive control circuit 2, and supplies the drive pixel data bits to an address driver 6. Next, the memory 4 regards the second bit of each pixel data PD11-PDnm as a drive pixel data bit DB211-DB2nm, and reads these drive pixel data bits on a display line basis in accordance with the read address supplied from the drive control circuit 2, and supplies the drive pixel data bits to an address driver 6. Next, the memory 4 regards the third bit of each pixel data PD11-PDnm as a drive pixel data bit DB311-DB3nm, and reads these drive pixel data bits on a display line basis in accordance with the read address supplied from the drive control circuit 2, and supplies the drive pixel data bits to an address driver 6. Then, the memory 4 regards the fourth bit of each pixel data PD11-PDnm as a drive pixel data bit DB411-DB4nm, and reads these drive pixel data bits on a display line basis in accordance with the read address supplied from the drive control circuit 2, and supplies the drive pixel data bits to an address driver 6.

[0061] It should be noted that during the foregoing operation, the memory 4 does not read a drive pixel data bit DB which belongs to a display line, the read address of which is not specified by the drive control circuit 2.

[0062] The drive control circuit 2 employs an appropriate light emission driving format in accordance with the positions and number of black display lines on one screen indicated by the flag registers RF1-FRn, and generates a variety of timing signals for driving the PDP 10 to display in gradation representation in conformity to the employed format. Then, the drive control circuit 2 supplies a variety of timing signals to each of the address driver 6, a first sustain driver 7 and a second sustain driver 8. Each of the address driver 6, first sustain driver 7 and second sustain driver 8 applies a variety of driving pulses to the column electrodes D and the row electrodes X, Y in response to the variety of timing signals supplied from the drive control circuit 2.

[0063]
FIG. 7 is a diagram illustrating a first light emission driving format employed by the drive control circuit 2 when a video signal corresponding to an image free of black display lines is supplied, for example, as represented by an image PC1.

[0064] In the first light emission driving format as illustrated, one field display period is divided into four subfields comprised of SF1-SF4. Then, in each of the subfields, a simultaneous reset process Rc, a pixel data writing process Wc, a light emission sustaining process Ic, and an erasure process E are performed, respectively.

[0065]
FIG. 9 is a waveform chart showing application timings at which each of the address driver 6, first sustain driver 7 and second sustain driver 8 applies a variety of driving pulses to the column electrodes and row electrode pairs of the PDP 10 in accordance with the first light emission driving format illustrated in FIG. 7.

[0066] It should be noted that FIG. 9 only shows application timings of driving pulses within one subfield extracted from the first light emission driving format.

[0067] As shown in FIG. 9, in the simultaneous reset process Rc, the first sustain driver 7 generates the reset pulse RPx of negative polarity, while the second sustain driver 8 generates the reset pulse RPy of positive polarity. These reset pulses are simultaneously applied to the row electrodes X, Y of the PDP 10, respectively. This causes all the discharge cells in the PDP 10 to be reset or discharged to forcedly form a uniform wall charge in each of the discharge cells. Immediately after that, the second sustain driver 8 simultaneously applies the row electrodes X1-Xn, of the PDP 10 with the erase pulse EP having a shorter pulse width and negative polarity to erase the wall charges formed in all the discharge cells. Such an operation initializes all the discharge cells in the PDP 10 to a “non-light emitting cell” state.

[0068] In the pixel data writing process Wc, the address driver 6 generates a pixel data pulse having a voltage corresponding to a logical level of the drive pixel data bit DB supplied from the memory 4. In this event, when the plasma display device is supplied with a video signal corresponding to an image which does not include any black display line, as represented by the image PC1, the drive pixel data bits DB belonging to each of the first to n-th display lines are all read from the memory 4. Then, the address driver 6 groups the pixel data pulses every display line into pixel data pulse groups DP1-DPn, and sequentially applies the column electrodes D1-Dm with pixel data pulse groups DP1-DPn from those belonging to the first display line to those belonging to the n-th display line. Assume herein that the address driver 6 generates a pixel data pulse at a high voltage when the drive pixel data bit DB is at logical level “1” and generates the pixel data pulse at a low voltage (zero volt) when the drive pixel data bit DB is at logical level “0.”

[0069] Further, in the pixel data writing process Wc, the drive control circuit 2 supplies the second sustain driver 8 with a timing signal for applying the scanning pulse SP only to those display lines that correspond to flag registers RF at logical level “0.” In this event, since no black display line exists within one screen in the image PC1, the contents stored in the flag registers FR1-FRn, are all logical level “0.” Thus, the second sustain driver 8 sequentially applies the scanning pulse SP of negative polarity to the row electrodes Y1-Yn at the same timing at which each pixel data pulse group DP is applied, as shown in FIG. 9.

[0070] In the pixel data writing process Wc, the discharge (selective writing discharge) occurs only in discharge cells at intersections of “rows” applied with the scanning pulse SP with “columns” applied with the pixel data pulse at the high voltage, so that wall charges are formed selectively in these discharge cells. This selective writing discharge as described causes the discharge cells initialized to the “non-light emitting cell” state in the simultaneous reset process Rc to transition to the “light emitting cells.” On the other hand, the selective writing discharge as described above does not occur in discharge cells which have been applied with the pixel data pulse at the low voltage, so that these discharge cells are maintained in the state initialized in the simultaneous reset process Rc, i.e., the “non-light emitting cell” state.

[0071] In other words, the pixel data writing process Wc sets each of the discharge cells in the PDP 10 into the “light emitting cell” or the “non-light emitting cell” state in accordance with the pixel data.

[0072] In the next light emission sustain process Ic, the first sustain driver 7 and the second sustain driver 8 alternately apply the sustain pulses IPX, IPY of positive polarity to the row electrodes X1-Xn, and Y1-Yn as illustrated in FIG. 9. In this event, the number of times the sustain pulses IP should be applied in the light emission sustain process Ic in each subfield SF1-SF4 illustrated in FIG. 7 are as follows:

[0073] SF1: 1

[0074] SF2: 2

[0075] SF3: 4

[0076] SF4: 8

[0077] In this way, the discharge cells in which the wall charges remain, i.e., the “light emitting cells” discharge each time the sustain pulses IPX, IPY are applied thereto to sustain the light emitting state associated with the sustain discharges for the number of times (period) the sustain pulses are applied.

[0078] Then, in the erasure process E at the end of each subfield, the second sustain driver 8 applies the row electrodes Y1-Yn with the erasure pulse EP as illustrated in FIG. 8 to simultaneously discharge all the discharge cells for erasure. This results in complete extinction of wall charges which have remained in the respective discharge cells.

[0079] A sequence of operations involved in the simultaneous reset process Rc, pixel data writing process Wc, light emission sustain process Ic and erasure process E are performed similarly for the other subfields. As described above, when the plasma display device is supplied with a video signal corresponding to an image which does not include any black display line, the PDP 10 is set to a gradation driving mode (hereinafter referred to as the “driving mode A”) as illustrated in FIGS. 7 and 9. According to the driving mode A, an intermediate luminance display at 16 gradation levels is performed for a luminance range from “0” to “15” based on 16 light emission patterns in accordance with the respective pixel data PD as shown in FIG. 10.

[0080] On the other hand, when the plasma display device is supplied with a video signal corresponding to an image which includes black display lines, the plasma display device of FIG. 5 performs gradation driving based on a driving mode B which employs the light emission driving format as illustrated in FIG. 8. It should be noted that an image PC2 which includes black display lines illustrated in FIG. 8 is, for example, an image of a CinemaScope or vista size in which each of the first to (i−1)th display lines and j-th to n-th display line is a black display line, as indicated by hatching in the figure.

[0081] As the plasma display device is supplied with a video signal corresponding to the image PC2, logical level “1” is written into each of flag registers FR1-FR(i−1) and FR(j+1)-FRn within the flag registers FR1-FRn, while the contents stored in the remaining flag registers are logical level “0.”

[0082] The drive control circuit 2 employs the second light emission driving format illustrated in FIG. 8 based on the contents stored in these flag registers FR1-FRn. Then, the drive control circuit 2 supplies each of the address driver 6, first sustain driver 7 and second sustain driver 8 with a variety of timing signals for performing the gradation driving in accordance with the second light emission driving format. The second light emission driving format is identical to the first light emission driving format illustrated in FIG. 7 in that the simultaneous reset process Rc, pixel data writing process Wc, light emission sustain process Ic and erasure process E are performed in each of four subfields SF1-SF4. However, the second light emission driving format differs from the first light emission driving format in the operations performed in each of the pixel data writing process Wc and the light emission sustain process Ic.

[0083]
FIG. 11 shows application timings at which each of the address driver 6, first sustain driver 7 and second sustain driver 8 applies a variety of driving pulses to the column electrodes and the row electrode pairs of the PDP 10 in accordance with the second light emission driving format illustrated in FIG. 8.

[0084] It should be noted that FIG. 11 only shows application timings of driving pulses within one subfield extracted from the second light emission driving format.

[0085] As shown in FIG. 11, in the simultaneous reset process Rc, the first sustain driver 7 generates the reset pulse RPX of negative polarity, while the second sustain driver 8 generates the reset pulse RPY of positive polarity. These reset pulses are simultaneously applied to the row electrodes X, Y of the PDP 10, respectively. This causes all the discharge cells in the PDP 10 to be reset or discharged to forcedly form a wall charge in each of the discharge cells. Immediately after that, the second sustain driver 8 simultaneously applies the row electrodes X1-Xn, of the PDP 10 with the erase pulse EP having a shorter pulse width and negative polarity to erase the wall charges formed in all the discharge cells. Such an operation initializes all the discharge cells in the PDP 10 to “non-light emitting cell” state.

[0086] In the pixel data writing process Wc, the address driver 6 generates a pixel data pulse having a voltage corresponding to a logical level of the drive pixel data bit DB supplied from the memory 4. In this event, when the plasma display device is supplied with a video signal corresponding to an image which includes black display lines, as represented by the image PC2, the drive pixel data bits DB belonging to each of the first to j-th display lines are only read from the memory 4. In other words, the drive pixel data bits DB belonging to each of the remaining first to (i−1)th display lines and (j+1)th to n-th display lines are not read from the memory 4. Therefore, the address driver 6 applies the column electrodes D1-Dm with a pixel data pulse group DPi belonging to an i-th display line to a pixel data pulse group DPj belonging to a j-th display line sequentially every display line, as illustrated in FIG. 11. The address driver 6 generates a pixel data pulse at a high voltage when the drive pixel data bit DB is at logical level “1” and generates the pixel data pulse at a low voltage (zero volt) when the drive pixel data bit DB is at logical level “0.”

[0087] Further, in the pixel data writing process Wc, the drive control circuit 2 supplies the second sustain driver 8 with a timing signal for applying the scanning pulse SP only to those display lines that correspond to flag registers RF at logical level “0.” In this event, each of the first to (i−1)th display lines and the (j+1)th to n-th display lines in one screen is a black display line, as indicated by the hatchings in the image PC2. Thus, in this event, logical level “1” is stored in the flag registers FR1-FR(i−1) and FR(j+1)-FRn within the flag registers FR1RFn, and logical level “0” is stored in the remaining flag registers FRi-FRj. Thus, the second sustain driver 8 sequentially applies the scanning pulse SP of negative polarity only to the low electrodes Y1-Yj within the row electrodes Y1-Yn, as shown in FIG. 11.

[0088] In the pixel data writing process Wc, the discharge (selective writing discharge) occurs only in discharge cells at intersections of “rows” applied with the scanning pulse SP with “columns” applied with the pixel data pulse at the high voltage, so that wall charges are formed selectively in these discharge cells. This selective writing discharge as described causes the discharge cells initialized to the “non-light emitting cell” state in the simultaneous reset process Rc to transition to the “light emitting cells.” On the other hand, the selective writing discharge as described above does not occur in discharge cells which have been applied with the pixel data pulse at the low voltage, so that these discharge cells are maintained in the state initialized in the simultaneous reset process Rc, i.e., the “non-light emitting cell” state.

[0089] In other words, the pixel data writing process Wc sets each of the discharge cells in the PDP 10 into the “light emitting cell” or the “non-light emitting cell” state in accordance with pixel data as shown in FIG. 11.

[0090] In the next light emission sustain process Ic, the first sustain driver 7 and the second sustain driver 8 alternately apply the sustain pulses IPX, IPy of positive polarity to the row electrodes X1-Xn and Y1-Yn. In this event, the number of times the sustain pulses IP should be applied in the light emission sustain process Ic in each subfield SF1-SF4 illustrated in FIG. 8 are as follows:

[0091] SF1: 2

[0092] SF2: 4

[0093] SF3: 8

[0094] SF4: 16

[0095] In this way, the discharge cells in which the wall charges remain, i.e., the “light emitting cells” discharge each time the sustain pulses IPX, IPY are applied thereto to sustain the light emitting state associated with the sustain discharges for the number of times (period) the sustain pulses are applied.

[0096] Then, in the erasure process E at the end of each subfield, the second sustain driver 8 applies the row electrodes Y1-Yn with the erasure pulse EP as illustrated in FIG. 11 to simultaneously discharge all the discharge cells for erasure. This results in complete extinction of wall charges which have remained in the respective discharge cells.

[0097] As described above, when the plasma display device is supplied with a video signal corresponding to an image which includes black display lines as represented by the image PC2, the PDP 10 is set to the driving mode B as illustrated in FIGS. 8 and 11. The driving mode B thus performed provides an intermediate luminance display at 16 gradation levels for a luminance range from “0” to “30,” higher than the driving mode A, as shown in FIG. 10.

[0098] Specifically, when a black display line exists in one screen, the application of the scanning pulse SP and a pixel data pulse group DP for the black display line are stopped to reduce a time required for performing each pixel data writing process Wc. Stated another way, since discharge cells corresponding to the black display line, which has a luminance level “0,” may be fixed in the non-light emitting state without even taking into account their pixel data, writing of pixel data into the black display line is stopped. Then, a light emitting period (number of times) allocated to the light emission sustain process Ic within each subfield is increased by the reduction in time for the pixel data writing process Wc as mentioned above, thereby increasing the display luminance of the overall image.

[0099] The foregoing embodiment has been described for the so-called selective writing address method which is employed as a method of writing pixel data, wherein each of discharge cells is selectively discharged (selective writing discharge) in accordance with pixel data to form wall charges within the discharge cells to write pixel data.

[0100] The present invention, however, is similarly applicable to the so-called selective erasure address method which may be employed as a method of writing pixel data, wherein a wall discharge formed in each of discharge cells is selectively erased in accordance with pixel data.

[0101]
FIG. 12 is a diagram illustrating a first light emission driving format employed by the drive control circuit 2 when the selective erasure address method is employed as a method of writing pixel data. Specifically, FIG. 12 illustrates a light emission driving format which is employed when the plasma display device is supplied with a video signal corresponding to an image which does not include any black lines, for example, as represented by an image PC1. In this event, the illustrated light emission driving format is identical to those illustrated in FIGS. 7 and 8 in that the simultaneous reset process Rc, pixel data writing process Wc, light emission sustain process Ic and erasure process E are performed in each of four subfields SF1-SF4.

[0102]
FIG. 14 is a waveform chart showing application timings at which each of the first sustain driver 7 and second sustain driver 8 applies a variety of driving pulses to the column electrodes and the row electrode pairs in the PDP 10 in accordance with the first light emission driving format illustrated in FIG. 12. It should be noted that FIG. 14 only shows application timings of driving pulses within one subfield extracted from the first light emission driving format illustrated in FIG. 12.

[0103] In FIG. 14, in the simultaneous reset process Rc, the first sustain driver 7 generates the reset pulse RPX of negative polarity, while the second sustain driver 8 generates the reset pulse RPY of positive polarity. These reset pulses are simultaneously applied to the row electrodes X, Y of the PDP 10, respectively. This causes all the discharge cells in the PDP 10 to be reset or discharged to forcedly form a wall charge in each of the discharge cells. Such an operation initializes all the discharge cells in the PDP 10 to a “light emitting cell” state.

[0104] In the pixel data writing process Wc, the address driver 6 generates a pixel data pulse having a voltage corresponding to a logical level of the drive pixel data bit DB supplied from the memory 4. In this event, when the plasma display device is supplied with a video signal corresponding to an image which does not include any black display line, as represented by the image PC1, the drive pixel data bits DB belonging to each of the first to n-th display lines are all read from the memory 4. Then, the address driver 6 groups the pixel data pulses every display line into pixel data pulse groups DP1-DPn, and sequentially applies the column electrodes D1-Dm with pixel data pulse groups DP1-DPn from those belonging to the first display line to those belonging to the n-th display line. Assume herein that the address driver 6 generates a pixel data pulse at a high voltage when the drive pixel data bit DB is at logical level “1” and generates the pixel data pulse at a low voltage (zero volt) when the drive pixel data bit DB is at logical level “0.”

[0105] Further, in the pixel data writing process Wc, the drive control circuit 2 supplies the second sustain driver 8 with a timing signal for applying the scanning pulse SP only to those display lines that correspond to flag registers RF at logical level “0.” In this event, since no black display line exists within one image in the image PC1, the contents stored in the flag registers FR1-FRn are all logical level “0.” Thus, the second sustain driver 8 sequentially applies the scanning pulse SP of negative polarity to the row electrodes Y1-Yn at the same timing at which each pixel data pulse group DP is applied, as shown in FIG. 14.

[0106] In the pixel data writing process Wc, the discharge (selective writing discharge) occurs only in discharge cells at intersections of “rows” applied with the scanning pulse SP with “columns” applied with the pixel data pulse at the high voltage to extinguish the wall charges formed in the discharge cells. This selective writing discharge as described causes the discharge cells initialized to the “light emitting cell” state in the simultaneous reset process Rc to transition to the “non-light emitting cells.” On the other hand, the selective writing discharge as described above does not occur in discharge cells which have been applied with the pixel data pulse at the low voltage, so that these discharge cells are maintained in the initialized state in the simultaneous reset process Rc, i.e., the “light emitting cell” state.

[0107] In the next light emission sustain process Ic, the first sustain driver 7 and the second sustain driver 8 alternately apply the sustain pulses IPX, IPY of positive polarity to the row electrodes X1-Xn and Y1-Yn, as illustrated in FIG. 14. In this event, as shown in FIG. 12, the number of times the sustain pulses IP should be applied in the light emission sustain process Ic in each subfield SF1-SF4 are as follows:

[0108] SF1: 1

[0109] SF2: 2

[0110] SF3: 4

[0111] SF4: 8

[0112] In this way, the discharge cells in which the wall charges remain, i.e., the “light emitting cells” discharge each time the sustain pulses IPx, IPY are applied thereto to sustain the light emitting state associated with the sustain discharges for the number of times (period) the sustain pulses are applied.

[0113] Then, in the erasure process E at the end of each subfield, the second sustain driver 8 applies the row electrodes Y1-Yn with the erasure pulse EP as illustrated in FIG. 8 to simultaneously discharge all the discharge cells for erasure. This results in complete extinction of wall charges which have remained in the respective discharge cells.

[0114] A sequence of operations involved in the simultaneous reset process Rc, pixel data writing process Wc, light emission sustain process Ic and erasure process E are performed similarly for the other subfields.

[0115] As described above, when the plasma display device is supplied with a video signal corresponding to an image which does not include any black display line as represented by the image PC1, the PDP 10 is set to a gradation driving mode (hereinafter referred to as the “driving mode A”) as illustrated in FIGS. 12 and 14. Consequently, an intermediate luminance display at 16 gradation levels is performed for a luminance range from “0” to “15” as is the case where the aforementioned selective writing address method is employed.

[0116] On the other hand, when the plasma display device is supplied with a video signal corresponding to an image of, for example, a vista size or a CinemaScope size, which includes black display lines, as represented by an image PC2, a gradation driving mode is performed as described below.

[0117] In this event, as the plasma display device is supplied with a video signal corresponding to the image PC2, logical level “1” is written into each of flag registers FR1-FR(i−1) and FR(j+1)-FRn within the flag registers FR1-FRn, while the contents stored in the remaining flag registers are logical level “0.”

[0118] The drive control circuit 2 employs the second light emission driving format illustrated in FIG. 13 based on the contents stored in these flag registers FR1-FRn. Then, the drive control circuit 2 supplies each of the address driver 6, first sustain driver 7 and second sustain driver 8 with a variety of timing signals for performing the gradation driving in accordance with the second light emission driving format. The second light emission driving format is identical to the first light emission driving format illustrated in FIG. 12 in that the simultaneous reset process Rc, pixel data writing process Wc, light emission sustain process Ic and erasure process E are performed in each of the four subfields SF1-SF4. However, the second light emission driving format differs from the first light emission driving format in the operations performed in each of the pixel data writing process Wc and the light emission sustain process Ic.

[0119]
FIG. 15 shows application timings at which each of the address driver 6, first sustain driver 7 and second sustain driver 8 applies a variety of driving pulses to the column electrodes and the row electrode pairs of the PDP 10 in accordance with the second light emission driving format illustrated in FIG. 13. It should be noted that FIG. 15 only shows application timings of driving pulses within one subfield extracted from the second light emission driving format illustrated in FIG. 13.

[0120] In FIG. 15, in the simultaneous reset process Rc, the first sustain driver 7 generates the reset pulse RPX of negative polarity, while the second sustain driver 8 generates the reset pulse RPY of positive polarity. These reset pulses are simultaneously applied to the row electrodes X, Y of the PDP 10, respectively. This causes all the discharge cells in the PDP 10 to be reset or discharged to forcedly form a wall charge in each of the discharge cells. Such an operation initializes all the discharge cells in the PDP 10 to a “light emitting cell” state.

[0121] In the pixel data writing process Wc, the address driver 6 applies the column electrodes D1-Dm with a pixel data pulse group DP0 comprised of m pixel data pulses each having a high voltage. In this event, at the same timing at which the pixel data pulse group DP0 is applied, the second sustain driver 8 simultaneously applies the scanning pulse SP of negative polarity to each of the row electrodes Y1-Yi−1 and Yj+1-Yn, as shown in FIG. 15. In response to the simultaneous application of these pixel data pulse group DP0 and scanning pulse SP, an erasure discharge occurs in all discharge cells belonging to each of the first display line to the (i−1)th display line and the (j+1)th display line to the n-th display line of the PDP 10. This results in extinction of the wall charges formed in all the discharge cells belonging to each of the first display line to the (i−1)th display line and the (j+1)th display line to the n-th display line, causing each of these discharge cells to transition to a “non-light emitting cell.” After the application of the pixel data pulse group DPO, the address driver 6 generates a pixel data pulse having a voltage corresponding to a logical level of the drive pixel data bit DB supplied from the memory 4. In this event, when the plasma display device is supplied with a video signal corresponding to an image which includes black display lines, as represented by the image PC2, the drive pixel data bits DB belonging to each of the first to j-th display lines are only read from the memory 4. Therefore, the address driver 6 sequentially applies the column electrodes D1-Dm with a pixel data pulse group DPi belonging to an i-th display line to a pixel data pulse group PDjJ belonging to a j-th display line every display line, as illustrated in FIG. 15. The address driver 6 generates a pixel data pulse at a high voltage when the drive pixel data bit DB is at logical level “1” and generates the pixel data pulse at a low voltage (zero volt) when the drive pixel data bit DB is at logical level “0.” Then, at the timing at which each of the pixel data pulse group DPi to the pixel data pulse group Pj is applied, the second sustain driver 8 sequentially applies the scanning pulse SP of negative polarity only to the row electrodes Yi-Yj within the row electrodes Y1-Yn. Consequently, the discharge (selective writing discharge) occurs only in discharge cells at intersections of “rows” applied with the scanning pulse SP with “columns” applied with the pixel data pulse at the high voltage to extinguish the wall charges formed in the discharge cells. This selective writing discharge causes the discharge cells in which the selective erasure discharge occurred to transition to the “non-light emitting cells,” while the discharge cells in which the selective erasure discharge did not occur maintain the “light-emitting cell” state.

[0122] In the pixel data writing process Wc illustrated in FIGS. 13 and 15, discharge cells belonging to each of the i-th display line to the j-th display line of the PDP 10 are set into the “light emitting cell” or “non-light emitting cell” state in accordance with pixel data. On the other hand, all discharge cells belonging to each of the remaining display lines, i.e., the first display line to the (i−1)th display line and the (j+1)th display line to the n-th display line are forcedly set to the “non-light emitting cells.”

[0123] In the next light emission sustain process Ic, the first sustain driver 7 and the second sustain driver 8 alternately apply the sustain pulses IPX, IPY of positive polarity to the row electrodes X1-Xn and Y1-Yn, as shown in FIG. 15. In this event, the number of times the sustain pulses IP should be applied in the light emission sustain process Ic in each subfield SF1-SF4 as illustrated in FIG. 13 are as follows:

[0124] SF1: 2

[0125] SF2: 4

[0126] SF3: 8

[0127] SF4: 16

[0128] In this way, only the discharge cells in which the wall charges remain, i.e., the “light emitting cells” discharge each time the sustain pulses IPX, IPY are applied thereto to sustain the light emitting state associated with the sustain discharges for the number of times (period) the sustain pulses are applied.

[0129] Then, in the erasure process E at the end of each subfield, the second sustain driver 8 applies the row electrodes Y1-Yn with the erasure pulse EP to simultaneously discharge all the discharge cells for erasure. This results in complete extinction of wall charges which have remained in the respective discharge cells.

[0130] As described above, when the plasma display device is supplied with a video signal corresponding to an image which includes black display lines as represented by the image PC2, the PDP 10 performs the gradation driving (driving mode B) as illustrated in FIGS. 13 and 15. The driving mode B thus performed provides an intermediate luminance display at 16 gradation levels for a luminance range from “0” to “30” as is the case where the aforementioned selective writing address method is employed. In this event, discharge cells belonging to the black display lines are simultaneously applied with the scanning pulse SP and the pixel data pulse group DP0 at a high voltage, as shown in FIG. 15, to produce an erasure discharge, forcing the discharge cells to transition to the “non-light emitting cell” state. Thus, as is the case where the selective writing address method as described above is employed, the operation for writing pixel data into the black display lines is omitted, thereby reducing a time required for performing each pixel data writing process Wc.

[0131] In essence, in the present invention, pixel data is sequentially written into each of pixel cells on every display line belonging to a region other than a black display region comprised of the black display lines. On the other hand, the writing of pixel data is stopped for each of pixel cells on the display lines belonging to the black display region, or these cells are simultaneously set into the “non-light emitting cell” state. Since this results in a reduction in time spent for each pixel data writing process in one field, a light emitting period (number of times) allocated to the light emission sustain process Ic within each subfield is increased by the reduction in time for the pixel data writing process Wc as mentioned above, thereby making it possible to increase the luminance of the overall displayed image.

[0132] While the foregoing embodiment has been described for a video signal, as an input to the plasma display device, which carries an image including black display lines in upper and lower portions of a screen, as represented by the image PC2, similar effects can be produced as well for a video signal which includes black display lines in other portions.

[0133] It should be noted that the plasma display panel driving method according to the present invention can also be applied to a plasma display device which has another configuration than the plasma display device as illustrated in FIG. 5.

[0134]
FIG. 16 is a block diagram illustrating another configuration of a plasma display device for driving a PDP to display in a gradation representation in accordance with the plasma display panel driving method according to the present invention.

[0135] A PDP 10′ comprises m column electrodes D1-Dm serving as upper address electrodes on the screen, m column electrodes D1′-Dm′ serving as lower address electrodes on the screen, and n row electrodes X1-Xn and n row electrodes Y1-Yn which are arranged to intersect these column electrodes. A Pair of these row electrodes X, Y form a row electrode corresponding to one display line in the PDP 10. The column electrodes D and the row electrodes X, Y are covered with a dielectric layer defining a discharge space, and a discharge cell corresponding to one pixel is formed at an intersection of each row electrode pair with each column electrode.

[0136] A synchronization detector circuit 1 generates a vertical synchronization detecting signal V when it detects a vertical synchronization signal from an input video signal, and supplies the signal V to a drive control circuit 2. Further, the synchronization detector circuit 1 generates a horizontal synchronization detecting signal H when it detects a horizontal synchronization signal from the input video signal, and supplies the signal H to each of the drive control circuit 2 and a black display region discriminating circuit 90.

[0137] An A/D converter 3 samples the input video signal for conversion to a 4-bit pixel data PD, for example, representative of a luminance level for each pixel, and supplied the pixel data PD to each of the black display region discriminating circuit 90 and a data converting circuit 50.

[0138] The black display region discriminating circuit 90 accumulates the pixel data PD, in each of display line groups comprised of a plurality of display lines adjacent to each other, corresponding to the display line group. Then, the black display region discriminating circuit 90 determines that the display line group belongs to a black display region having a luminance level “0” when the result of accumulation for the display line is “0.” Also, the black display region discriminating circuit 90 determines a display line group belongs to a black display region including a caption when the result of accumulating pixel data PD corresponding to the display line group is larger than “0” and smaller than a predetermined value. Further, the black display region discriminating circuit 90 determines that a display line group belongs to a normal image display region when the result of accumulating pixel data PD corresponding to the display line group is larger than the predetermined value. Then, the black display region discriminating circuit 90 supplies a drive control circuit 20 with a black display region discriminating signal EZ which indicates the determination result corresponding to each display line group. In this event, the drive control circuit 20 detects a black display region including a caption from one screen based on the black display region discriminating signal EZ, and supplies the data converting circuit 50 with a caption region detecting signal CP at logical level “1” when detected and at logical level “0” when not detected. The data converting circuit 50 uses a conversion table in accordance with the logical level of the caption region detecting signal CP to convert 4-bit pixel data PD supplied from the A/D converter 3 to a 15-bit drive pixel data GD which is supplied to a memory 40.

[0139]
FIG. 17 is a block diagram illustrating an exemplary internal configuration of the data converting circuit 50.

[0140] In FIG. 17, a data converting circuit 51 converts the 4-bit pixel data PD to 15-bit drive pixel data GDa in accordance with a conversion table as shown in FIG. 18, and supplies the 15-bit drive pixel data GDa to a selector 52. A data converting circuit 53 converts the 4-bit pixel data PD to 15-bit drive pixel data GDb in accordance with a conversion table as shown in FIG. 19, and supplies the 15-bit drive pixel data GDb to a selector 52. The selector 52 selects the drive pixel data GDa from the drive pixel data GDa and GDb when it is supplied with the caption region detecting signal CP at logical level “0” and supplies the selected drive pixel data GDa to the memory 40 as drive pixel data GD. On the other hand, the selector selects drive pixel data GDb when it is supplied with the caption region detecting signal CP at logical level “1” and supplies the selected drive pixel data GDb to the memory 40 as drive pixel data GD.

[0141] Specifically, when a black display region including a caption exists in one screen, the data converting circuit 50 converts 4-bit pixel data PD belonging to the black display region converts to 15-bit drive pixel data GD in accordance with the conversion table as shown in FIG. 19. On the other hand, when a black display region including a caption as mentioned above does not exist in one screen, the data converting circuit 50 converts 4-bit pixel data PD to 15-bit drive pixel data GD in accordance with the conversion table as shown in FIG. 18.

[0142] The drive control circuit 20 supplies the memory 40 with a write signal for writing the pixel data PD. Further, the drive control circuit 20 supplies the memory 40 with a read address and a read signal for sequentially reading pixel data written into the memory 40 from those belonging to a first display line at the top of the screen to those belonging to a k-th display line in a central region of the screen. In parallel with this, the drive control circuit 20 supplies the memory 40 with a read address and a read signal for sequentially reading pixel data written into the memory 40 from those belonging to an n-th display line at the bottom of the screen to those belonging to a (k+1)th display line in the central region of the screen.

[0143] The memory 40 sequentially stores the drive pixel data GD in response to the write signal supplied from the drive control circuit 20. Then, as the writing has been completed for one screen, i.e., from drive pixel data GD11 corresponding to the pixel at the first row, first column to drive pixel data GDnm corresponding to a pixel at n-th row, m-th column, the memory 40 performs a read operation as follows.

[0144] It should be noted that in the memory 40, each of drive pixel data GD11-GDnm are divided into respective bit digits as follows:

[0145] DB111-DB1nm: first bits of respective GD11-GDnm;

[0146] DB211-DB2nm: second bits of respective GD11-GDnm;

[0147] DB311-DB3nm: third bits of respective GD11-GDnm;

[0148] DB411-DB4nm: fourth bits of respective GD11-GDnm;

[0149] DB511-DB5nm: fifth bits of respective GD11-Gnm;

[0150] DB611-DB6nm: sixth bits of respective GD11-GDnm;

[0151] DB711-DB7nm: seventh bits of respective GD11-GDnm;

[0152] DB811-DB8nm: eighth bits of respective GD11-GDnm;

[0153] DB911-DB9nm: ninth bits of respective GD11-GDnm;

[0154] DB1011-DB10nm: tenth bits of respective GD11-GDnm;

[0155] DB1111-DB11nm: eleventh bits of respective GD11-GDnm;

[0156] DB1211-DB12nm: twelfth bits of respective GD11-GDnm;

[0157] DB1311-DB13nm: thirteenth bits of respective GD11-GDnm;

[0158] DB1411-DB14nm: fourteenth bits of respective GD11-GDnm;

[0159] DB1511-DB15nm: fifteenth bits of respective GD11-GDm and they are regarded as drive pixel data bits DB1-DB15.

[0160] The memory 40 first reads the drive pixel data bits DB111-DB1km, for every display line, corresponding to each of the first display line to the k-th display line in the upper half of the screen within the drive pixel data bits DB111-DB1nm in the order of the first display line to the k-th display line, and supplies the drive pixel data bits DB111-DB111-DB1km to the upper address driver 61. In parallel with this read operation, the memory 40 reads the drive pixel data bits DB1(k+1)1-DB1nm for every display line, corresponding to the (k+1)th display line to the n-th display line in the lower half of the screen within the drive pixel data bits DB111-DB1nm in the order of the n-th display line to the (k+11)th display line, and supplies the drive pixel data bits DB1(k+1)1-DB1nm, to the lower address driver 62. Next, the memory 40 reads the drive pixel data bits DB211-DB2km, for every display line, corresponding to the first display line to the k-th display line in the upper half of the screen within the drive pixel data bits DB211-DB2nm in the order of the first display line to the k-th display line, and supplies the drive pixel data bits DB211DB2km to the upper address driver 61. In parallel with this read operation, the memory 40 reads the drive pixel data bits DB2(k+1)1-DB2nm, for every display line, corresponding to the (k+1)th display line to the n-th display line in the lower half of the screen within the drive pixel data bits DB211-DB2nm in the order of the nth display line to the (k+1)th display line, and supplies the drive pixel data bits DB2(k+1)1-DB2nm to the lower address driver 62.

[0161] Then, the memory 40 sequentially performs the read operation as described above in a similar manner for each of the drive pixel data bits DB3-DB15.

[0162] The drive control circuit 20 selects a light emission driving format in accordance with the black display region discriminating signal EZ from the light emission driving formats illustrated in FIGS. 20 to 22. Specifically, when the plasma display device is supplied with a video signal corresponding to an image which does not include any black display region within one screen as represented by the image PC1, the drive control circuit 20 selects the first light emission driving format illustrated in FIG. 20 from the formats illustrated in FIGS. 20 to 22. Alternatively, when the plasma display device is supplied with a video signal corresponding to an image which has a black display region (indicated by hatchings) within one screen as represented by the image PC2, the driver control circuit 20 selects the second light emission driving format illustrated in FIG. 21 from the formats illustrated in FIGS. 20 to 22. Further alternatively, when the plasma display device is supplied with a video signal corresponding to an image which has a black display region JZ including a caption within one screen as represented by the image PC3, the drive control circuit 20 selects the third light emission driving format illustrated in FIG. 22 from the formats illustrated in FIGS. 20 to 22.

[0163] In the light emission driving formats illustrated in FIGS. 20 to 22, one field display period is divided into 15 subfields SF1-SF15, and the pixel data writing process Wc and the light emission sustain process Ic are performed in each of the subfields. The simultaneous reset process Rc is performed only in the first subfield SF1, and the erasure process E is performed only in the last subfield SF15.

[0164] The drive control circuit 20 generates a variety of timing signals for driving the PDP 10′ to display in gradation representation in accordance with the light emission driving format selected in the manner described above. Then, the drive control circuit 20 supplies each of the timing signals to each of the upper address driver 61, lower address driver 62, upper first sustain driver 71, lower first sustain driver 72, upper second sustain driver 81 and lower second sustain driver 82.

[0165] These drivers apply a variety of driving pulses to the column electrodes D and the row electrodes X, Y of the PDP 10′ in response to the variety of timing signals supplied from the drive control circuit 20.

[0166]
FIG. 23 is a waveform chart showing application timings at which each of the above drivers applies the variety of driving pulses to the column electrodes and the row electrode pairs of the PDP 10′ in accordance with the first light emission driving format illustrated in FIG. 20.

[0167] In FIG. 23, first, in the simultaneous reset process Rc of the first subfield SF1, each of the upper first sustain driver 71 and the lower first sustain driver 72 generates the reset pulse RPX of negative polarity, and simultaneously applies the reset pulse RPX to each of the row electrodes X1-Xn. Simultaneously, each of the upper second sustain driver 81 and the lower second sustain driver 82 generates the reset pulse RPy of positive polarity, and simultaneously applies the reset pulse RPY to all the row electrodes Y1-Yn. The application of these reset pulses RPX and RPY causes all the discharge cells in the PDP 10′ to be reset or discharged to forcedly form a wall charge in each of the discharge cells. Such an operation initializes all the discharge cells in the PDP 10′ to a “light emitting cell” state.

[0168] In each pixel data writing process Wc, each of the upper address driver 61 and the lower address driver 62 generates a pixel data pulse having a voltage corresponding to a logical level of the drive pixel data bit DB supplied from the memory 40. In this event, the drive pixel data bits DB11-DBkm corresponding to each of the first display line to the k-th display line in the upper half of the screen are read from the memory 40 every display line in the order of the first display line to the k-th display line within each of the drive pixel data bits DB11-DBnm. Therefore, the upper address driver 61 sequentially applies the column electrodes D1-Dm with pixel data pulse groups DP1-DPk, each comprised of m pixel data pulses, corresponding to each of the first display line to the k-th display line as shown in FIG. 23. Also, in parallel with the above read operation, the drive pixel data bits DB(k+1)1-DBnm corresponding to each of the (k+1)th display line to the n-th display line in the lower half of the screen are read from the memory 40 every display line in the order of the n-th display line to the (k+1)th display line within each of the drive pixel data bits DB11-DBnm. Therefore, the lower address driver 62 sequentially applies the column electrodes D1′-Dm′ with pixel data pulse groups DPn-DPk+1, each comprised of m pixel data pulses, corresponding to each of the n-th display line to the (k+1)th display line as shown in FIG. 23.

[0169] Further, in the pixel data writing process Wc, at the timing at which each of the pixel data pulse group DP1-DPk is applied, the upper second sustain driver 81 generates the scanning pulse SP of negative polarity and sequentially applies the scanning pulse SP to the row electrodes Yi-Yk, as shown in FIG. 23. Simultaneously with the operation of applying the scanning pulse SP, the lower second sustain driver 82 generates the scanning pulse SP of negative polarity at the same timing at which each of the pixel data pulse groups DPn-DP(k+1) is applied and sequentially applies the scanning pulse SP to the row electrodes Yn-Y(k+1), as shown in FIG. 23.

[0170] In the pixel data writing process Wc, the discharge (selective writing discharge) occurs only in discharge cells at intersections of “rows” applied with the scanning pulse SP with “columns” applied with the pixel data pulse at a high voltage to extinguish the wall charges formed in the discharge cells. This selective writing discharge as described causes the discharge cells initialized to the “light emitting cell” state in the simultaneous reset process Rc to transition to the “non-light emitting cells.” On the other hand, the selective writing discharge as described above does not occur in discharge cells which have been applied with the pixel data pulse at a low voltage, so that these discharge cells are maintained in the initialized state in the simultaneous reset process Rc, i.e., the “light emitting cell” state.

[0171] In the next light emission sustain process Ic, each of the upper first sustain driver 71, lower first sustain driver 72, upper second sustain driver 81, and lower second sustain driver 82 alternately applies the row electrodes X1-Xn and Y1-Yn with sustain pulses IPX and IPY of positive polarity as illustrated in FIG. 23. In this event, the number of times (period) the sustain pulses IP are applied in the light emission sustaining process Ic in each of the subfields SF1-SF15 as illustrated in FIG. 20 is two, as described in FIG. 20. Thus, the discharge cells in which the wall charges remain, i.e., the “light emitting cells” discharge to sustain light emission each time they are applied with the sustain pulses IPX and IPY to sustain the light emitting state associated with the sustain discharge for the number of times (period) as mentioned above.

[0172] A sequence of operations involved in the pixel data writing process Wc and the light emission sustain process Ic are performed in each of the subfields SF1-SF15.

[0173] Then, in the erasure process E in the subfield SF15 at the end of one field, each of the upper second sustain driver 81 and the lower second sustain driver 82 applies the row electrodes Y1-Yn with the erasure pulse EP. This result in the erasure discharge produced in all the discharge cells to completely extinguish the wall charges which have remained in the respective discharge cells.

[0174] As described above, a sequence of operations in the subfields SF1-SF15 are repetitively performed to provide a view at an intermediate luminance corresponding to a total number of times of sustain discharges produced in the light emission sustain process Ic in each of the subfields SF. In this event, whether or not the sustain discharge as described above is produced in the light emission sustain process Ic in each subfield is determined depending on whether or not the selective erasure discharge is produced in the pixel data writing process Wc in the subfield. Here, according to drive pixel data GD in FIG. 18, the selective erasure discharge is produced in the pixel data writing process Wc only in one of the subfields SF1-SF15 within one field, as indicated by black circles in FIG. 18. Therefore, the wall charges formed in the simultaneous reset process Rc in the first subfield SF1 remain until the selective erasure discharge occurs, thereby allowing each of the discharge cells to sustain the “light emitting cell” state. In other words, the sustain discharge, causing light emission, is produced in the light emission sustain process Ic in each of the subfields (indicated by white circles) intervening therebetween.

[0175] Therefore, according to the gradation driving sequence in accordance with the first light emission driving format illustrated in FIG. 20 using the drive pixel data GD illustrated in FIG. 18, an intermediate display luminance representation can be provided at 16 gradation levels, each of which has the following luminance:

[0176] {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30}.

[0177] Alternatively, when the plasma display panel is supplied with a video signal corresponding to an image having a black display region (indicated by hatchings) in one screen as represented by the image PC2, the drive control circuit 20 selects the second light emission driving format illustrated in FIG. 21 from the formats illustrated in FIGS. 20 to 22.

[0178]
FIG. 24 is a waveform chart showing application timings at which a variety of driving pulses are applied to the column electrodes and the row electrode pairs of the PDP 10′ in accordance with the second light emission driving format illustrated in FIG. 21. Since the timings at which the driving pulses are applied in the simultaneous rest process Rc and the pixel data writing process Wc within the subfield SF1 in FIG. 24 are identical to those shown in FIG. 23, description thereon is omitted.

[0179] First, in the pixel data writing process Wc in each of the subfields SF2-SF15, the drive control circuit 20 detects display lines belonging to a black display region based on the black display region discriminating signal EZ. Then, the drive control circuit 20 stops supplying the variety of drivers as mentioned above with a timing signal for prompting them to apply each of the display lines belonging to the black display region with the scanning pulse SP and the pixel data pulse groups DP. Therefore, when the plasma display panel is supplied with a video signal corresponding to an image as represented by the image PC2, the upper address driver 61 sequentially applies the column electrodes D1-Dm only with the pixel data pulse groups DPi-DPk from among the pixel data pulse groups DP1-DPk corresponding to each of the first display line to the k-th display line, except for DP1-DP(i−1) as shown in FIG. 24. The lower address driver 62 in turn sequentially applies the column electrodes D1′-Dm ′ only with the pixel data pulse groups DPj-DP(k+1) from among the pixel data pulse groups DPn-DP(k+1) corresponding to each of the n-th display line to the (k+1)th display line, except for DPn-DP(j+1), as shown in FIG. 24.

[0180] Further, in the pixel data writing process Wc, at the timing at which each of the pixel data pulse group DPi-DPk is applied, the upper second sustain driver 81 generates the scanning pulse SP of negative polarity and sequentially applies the scanning pulse SP to the row electrodes Yi-Yk, as shown in FIG. 24. Additionally, in parallel with the operation of applying the scanning pulse SP, the lower second sustain driver 82 generates the scanning pulse SP of negative polarity at the same timing at which each of the pixel data pulse groups DPj-DP(k+1) is applied and sequentially applies the scanning pulse SP to the row electrodes Yj-Y(k+1), as shown in FIG. 24.

[0181] In the pixel data writing process Wc, the selective erasure discharge occurs only in discharge cells at intersections of “rows” applied with the scanning pulse SP with “columns” applied with the pixel data pulse at a high voltage to extinguish the wall charges formed in the discharge cells. This selective erasure discharge as described causes the discharge cells initialized to the “light emitting cell” state in the simultaneous reset process Rc to transition to the “non-light emitting cells.” On the other hand, the selective writing discharge as described above does not occur in discharge cells which have been applied with the pixel data pulse at a low voltage, so that these discharge cells are maintained in the initialized state in the simultaneous reset process Rc, i.e., the “light emitting cell” state.

[0182] Then, in each light emission sustain process Ic, each of the upper first sustain driver 71, lower first sustain driver 72, upper second sustain driver 81, and lower second sustain driver 82 alternately applies the row electrodes X1-Xn and Y1-Yn with sustain pulses IPX and IPY of positive polarity as illustrated in FIG. 24. In this event, the number of times the sustain pulses IP are applied in the light emission sustaining process Ic in each of the subfields SF1-SF15 is four, as described in FIG. 21. Thus, the discharge cells in which the wall charges remain, i.e., the “light emitting cells” discharge to sustain light emission each time they are applied with the sustain pulses IPX and IPY to sustain the light emitting state associated with the sustain discharge for the number of times as mentioned above.

[0183] A sequence of operations involved in the pixel data writing process Wc and the light emission sustain process Ic are performed in each of the subfields SF2-SF15.

[0184] Then, only in the erasure process E in the subfield SF15 at the end of one field, each of the upper second sustain driver 81 and the lower second sustain driver 82 applies the row electrodes Y1-Yn with the erasure pulse EP as shown in FIG. 24. This results in the erasure discharge produced in all the discharge cells to completely extinguish the wall discharges which have remained in the respective discharge cells.

[0185] As described above, a sequence of operations in the subfields SF1-SF15 illustrated in FIG. 21 are repetitively performed to provide a view at an intermediate luminance corresponding to a total number of times of sustain discharges produced in the light emission sustain process Ic in each of the subfields SF. In this event, whether or not the sustain discharge as described above is produced in the light emission sustain process Ic in each subfield is determined depending on whether or not the selective erasure discharge is produced in the pixel data writing process Wc in the subfield. Here, according to the drive pixel data GD in FIG. 18, the selective erasure discharge is produced in the pixel data writing stage Wc only in one of the subfields SF1-SF15 within one field, as indicated by black circles in FIG. 18. Therefore, the wall charges formed in the simultaneous reset process Rc in the first subfield SF1 are held until the selective erasure discharge occurs, thereby prompting each of the discharge cells to emit light in the light emission sustain process Ic in each of the subfields (indicated by white circles) intervening therebetween. In this event, the wall charge is extinguished once the selective erasure discharge is produced, so that no light is emitted in any of the light emission sustain processes Ic subsequent thereto. Here, all pixel data PD corresponding to the black display regions (first to i-th display lines and j-th to n-th display lines) indicated by hatchings in the image PC2 have a luminance level “0.” Therefore, once the selective erasure discharge is produced in the subfield SF1 as illustrated in FIG. 21, pixel data need not be written into the first to i-th display lines and the j-th to n-th display lines included in the black display regions in the subfields subsequent thereto. Since this results in a reduction in time spent for each pixel data writing process Wc in each of the subfields SF2-SF15 in FIG. 21, the number of times of light emission allocated to each light emission sustain process Ic is increased to “4,” as shown in FIG. 21, by the reduction in time for the pixel data writing process Wc.

[0186] Therefore, according to the gradation driving sequence in accordance with the second light emission driving format illustrated in FIG. 21 using the drive pixel data GD illustrated in FIG. 18, an intermediate display luminance representation can be provided at 16 gradation levels, each of which has the following luminance, higher than those provided by the gradation driving in accordance with the first light emission driving format illustrated in FIG. 20:

[0187] {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60}.

[0188] Alternatively, when the plasma display panel is supplied with a video signal corresponding to an image having a black display region JZ including a caption in one screen as represented by the image PC3, the gradation driving is performed in accordance with the third light emission driving format as illustrated in FIG. 22.

[0189] In the third light emission driving format, since the operations in each of the subfields SF1-SF7 and SF9-SF15, except for the subfield SF8, are identical, description thereon is omitted.

[0190] In the pixel data writing process Wc in the subfield SF8 in the third light emission driving format, pixel data is written into all the display lines in a manner similar to the subfield SF1 to stop light emission associated with a display of a caption at this time. In this event, pixel data PD representing the black display region JZ including a caption as represented by the image PC3 is converted to 15-bit drive pixel data GD which has only a first bit set at logical level “1” or only an eighth bit set at logical level “1” in accordance with the data conversion table as shown in FIG. 19. Here, since pixel data PD corresponding to a portion free of the caption within the black display region JZ (a portion at luminance level “0”) is “0000,” the pixel data is converted to 15-bit drive pixel data GD which has only a first bit set at logical level “1” by the data conversion table shown in FIG. 19. Therefore, since the selective erasure discharge has been produced in the pixel data writing process Wc in the first subfield SF1, no sustain discharge is produced in the light emission sustain process Ic in any of the subfields SF1-SF15. In other words, the pixel data is in a black display state at luminance level “0.” On the other hand, pixel data PD corresponding to the caption itself in the black display region JZ is other than “0000,” the pixel data PD is converted to 15-bit drive pixel data GD which has only the eight bit set at logical level “1” by the data conversion table shown in FIG. 19. Thus, until the selective erasure discharge is produced in the subfield SF8 as indicated by a black circle in FIG. 19, a sustain discharge associated with light emission is produced in the light emission sustain process Ic in each of the subfields SF1-SF7, as indicated by white circles in FIG. 19. This results in the caption displayed at luminance level “28.”

[0191] In this event, the pixel data writing process Wc in each of the subfields SF2-SF7 and SF9-SF15 omits the pixel data write operation for the black display region in a manner similar to the second light emission driving format illustrated in FIG. 21. Accordingly, the number of times of light emission allocated to each light emission sustain process Ic is increased to “4,” similar to the second light emission driving format illustrated in FIG. 21, by the reduction in time for the pixel data writing process Wc, thereby providing a higher intermediate display luminance.

[0192] In the foregoing embodiment, a black display region included in one screen is detected based on an input image signal to stop a pixel data write operation for the detected black display region, thereby reducing a time required for performing each pixel data writing process Wc. Alternatively, the time required for performing each pixel data writing process Wc may be reduced by choosing a less number of gradation levels for previously set upper and lower display regions on the screen than a central display region at the center of screen.

[0193] In this event, the data converting circuit 50 converts pixel data PD representative of an upper display region Gup and a lower display region GDW in a screen as illustrated in FIG. 25 to 15-bit drive pixel data GD in accordance with the data conversion table shown in FIG. 19. On the other hand, the data converting circuit 50 converts pixel data PD representative of a central display region GCN at the center in the screen as illustrated in FIG. 25 to 15-bit drive pixel data GD in accordance with the data conversion table shown in FIG. 18.

[0194] Then, the gradation driving is performed for the PDP 10′, as shown in FIGS. 22 to 24.

[0195] According to the driving sequence as described, for the central display region GCN at the center of the screen as illustrated in FIG. 25, the plasma display device is driven to provide a display with a larger number of gradation levels equal to 16 as follows:

[0196] {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60}

[0197] On the other hand, the upper display region GUP and the lower display region GDW in the screen as illustrated in FIG. 25, the plasma display device is driven to provide a display with a smaller number of gradation levels equal to two as follows:

[0198] {0, 28}

[0199] In other words, for an image whose central display region is only to be monitored, the number of gradation levels is reduced for an upper and a lower display region on the screen to reduce a time required for performing each pixel data writing process Wc. Thus, the number of times light is emitted for the central display region is increased by the reduction in the time for the pixel data writing process Wc to realize a high luminance display.

[0200] Alternatively, the plasma display device may be configured such that the high luminance number driving is performed for the central display region as described above, while a first driving sequence for performing the low gradation number driving and a second driving sequence for driving the entire screen with the same number of gradation levels as shown in FIGS. 20 to 22 may be selectively performed for the upper and lower display regions in accordance with a manipulation of the user. Further alternatively, the plasma display device may be configured such that the first driving sequence is performed when it is supplied with a video signal representative of an image which includes black display regions, as mentioned above, in an upper and a lower portion of the screen, while the second driving sequence is automatically performed when it is supplied with a video signal representative of an image which does not include any black display region.

[0201] Also, in the foregoing embodiment, pixel data of every display line is sequentially written into each of display lines belonging to a black display region as represented by the image PC3 or to the upper display region Gup and the lower display region GDW in FIG. 21. However, since these upper display region Gup and lower display region GDW as well as the black display region do not require a high image quality, the same pixel data may be used so that the pixel data is simultaneously written into a plurality of display lines.

[0202]
FIG. 26 is a waveform chart showing an exemplary driving method which is modified in view of the aspect mentioned above.

[0203] In FIG. 26, pixel data is simultaneously written into a first and a second display line belonging to an upper display region Gup, using a pixel data pulse DP12, in the pixel data writing process Wc in the subfield SF1. Also, pixel data is simultaneously written into an n-th and an (n−1)th display line belonging to the lower display region GDw, using a pixel data pulse DPn1.

[0204] According to this driving method, it is possible to further reduce the time required for the pixel data writing process Wc.

[0205] Also, in the foregoing embodiment, the time required for performing the pixel data writing process Wc is reduced by stopping a select operation for setting discharge cells belonging to a black display line or a low gradation level number driven line into the “light emitting cell” state or the “non-light emitting cell” state, or collectively setting the discharge cells into the “non-light emitting cell” state. Then, the number of times of light emission allocated to the light emission sustain process Ic in each subfield is increased by the reduction in time. Alternatively, the number of subfields allocated to one field display period may be increased in accordance with the reduction in time to increase the number of display gradation levels for a higher image quality.

[0206] For example, in place of the second driving format which divides one field display period into four subfields as illustrated in FIG. 8, a light emission driving format is employed to divide one field period into five subfields SF1-SF5, in accordance with the reduction in time, in which light is emitted in each light emission sustain process Ic the following numbers of times:

[0207] SF1: 1

[0208] SF2: 2

[0209] SF3: 4

[0210] SF4: 8

[0211] SF5: 16

[0212] In this way, since an increase in the number of subfields resulting from the utilization of the reduction in time provides an increased number of display gradation levels, the image quality can be improved.

[0213] As described above in detail, in the present invention, pixel data of every display line is sequentially written into pixel cells on display lines belonging to a region other than a black display region on the screen, while the writing of pixel data is stopped for pixel cells on display lines belonging to the black display region, or the pixel cells are simultaneously set into the non-light emitting cell state.

[0214] Therefore, according to the present invention, since a time spent for each pixel data writing process in one field is reduced, the quality of a displayed image can be improved by increasing a light emission period (number of times) allocated to each light emission sustain process or by increasing the number of subfields in one field by the reduction in time.

Display panel driving method

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