Patent Grant
7317431
The present invention relates to a driving method for a display panel in which pixel cells serving as pixels are arranged on respective display lines.
Recently, where two-dimensional image display panels are concerned, plasma display panels (hereinafter called ‘PDP’), in which a plurality of discharge cells are arranged in the form of a matrix, have been attracting attention. The subfield method is known as a driving method for displaying an image corresponding with a video input signal on the PDP. The subfield method divides a single-field display period into a plurality of subfields and causes each of the discharge cells to selectively discharge light in each subfield in accordance with the luminance level represented by the video input signal. Accordingly, an intermediate luminance corresponding with the total light emission period within the single-field period is visible (or perceived).
The light emission drive sequence shown in
According to the light emission pattern shown in
However, with this driving method, because there are restrictions on the number of subfields, there is a shortage in the number of grayscales. In order to compensate for the shortage in the number of grayscales, multiple grayscale processing such as error diffusion and dither processing is performed on the video input signal.
Error diffusion processing converts the video input signal into 8-bit pixel data, for example, for each pixel. The upper 6 bits of the pixel data is treated as display data and the remaining lower two bits of the pixel data is treated as error data. Then, the error data of the pixel data are weighted and added based on the respective peripheral pixels and the resultant is reflected in the display data. As a result of this operation, a pseudo-representation of the luminance of the lower two bits of the original pixel is provided by the peripheral pixels, and, consequently, a luminance grayscale representation of the 8 bits of pixel data is possible by means of the six bits of display data. Further, dither processing is performed on the six-bit error-diffusion-processed pixel data obtained by the error diffusion processing. In dither processing, a single pixel unit is rendered from a plurality of adjoining pixels, and dither coefficients consisting of different coefficient values are allocated and added to the error-diffusion-processed pixel data corresponding with the respective pixels in the single pixel unit. As a result of the addition of the dither coefficients, when viewed in the single pixel unit, the luminance of the 8-bit original data can be represented by only the upper four bits of the dither-added pixel data. Therefore, the upper four bits of the dither-added pixel data are extracted and allocated to each of the 15 different light emission patterns shown in
However, when a dither coefficient addition is performed regularly on the pixel data by means of dither processing and so forth, a pseudo pattern which is completely independent of the video input signal, i.e. a so-called dither pattern, is sometimes observed, which compromises the quality of the displayed image.
An object of the present invention is to provide a display panel driving method capable of creating a favorable image display in which dither patterns are suppressed.
According to one aspect of the present invention, there is provided an improved method of grayscale-driving a display panel in accordance with pixel data derived from a video signal. The display panel includes a plurality of display lines, with a plurality of pixel cells serving as pixels being arranged on each display line. A display period of a single field of the video signal is divided into a plurality of subfields. The method includes dividing one of the subfields into M lower subfields. M is an integer greater than one. M groups of display lines are prepared by sequentially taking every M display lines from the display lines. First to Mth address steps are performed in the M lower subfields respectively and sequentially. Each address step sets the pixel cells belonging to the display lines of the display line group concerned, to a drive mode determined by the pixel data. A first light emission step is performed to cause the pixel cells whose drive mode is a lit mode, to emit light directly before or after the address step concerned. Another subfield is divided into N lower subfields. N is smaller than M. N groups of address steps are prepared from the first to Mth address steps. Each address step group includes one or more address steps, and at least one address step group includes a plurality of address steps. The N address step groups are performed in the N lower subfields respectively and sequentially. A second light emission step is performed to cause the pixel cells whose drive mode is the lit mode, to emit light directly before or after the address step group concerned.
These and other objects, aspects and advantages of the present invention will become apparent to those skilled in the art from the following detailed description and appended claims when read and understood in conjunction with the attached drawings.
A description of a drive device for driving a plasma display panel (PDP) based on a driving method according to one embodiment of the present invention will now be provided with reference to
The PDP 100 includes a front-side substrate (not shown) that functions as a display surface, and a rear-side substrate (not shown) that is disposed in a position opposite the front-side substrate. A discharge space filled with discharge gas is defined between the front-side substrate and rear-side substrate. Belt-shaped row electrodes X1 to Xn and row electrodes Y1 to Yn are alternately arranged in parallel to each other and provided on the front-side substrate. Belt-shaped column electrodes D1 to Dm arranged to cross over the row electrodes are provided on the rear-side substrate. The row electrodes X1 to Xn and Y1 to Yn are arranged such that the first to nth display lines of the PDP 100 are defined by n pairs of row electrodes X1 and Y1. Discharge cells G serving as pixels are formed at the intersection points (including the discharge space) between the row electrode pairs and column electrodes. That is, (n×m) discharge cells G(1,1) to G(n,m) are formed in a matrix shape on the PDP 100.
A pixel data conversion circuit 1 converts a video input signal into 6-bit pixel data PD, for example, for each pixel, and then supplies this pixel data PD to a multiple grayscale processing circuit 2. The multiple grayscale processing circuit 2 includes a line dither offset value generation circuit 21, an adder 22, and a lower bit discard circuit 23.
The line dither offset value generation circuit 21 first generates eight line dither offset values LD with the values ‘0’ to ‘7’ respectively to match eight display line groups of the PDP 100. The first to nth display lines of the PDP 100 are separated by eight lines and grouped as shown below:
the (8N-7)th display line group consisting of the 1st, 9th, 17th, . . . , (n-7)th display lines;
the (8N-6)th display line group consisting of the 2nd, 10th, 18th, . . . , and (n-6)th display lines;
the (8N-5)th display line group consisting of the 3rd, 11th, 19th, . . . , and (n-5)th display lines;
the (8N-4)th display line group consisting of the 4th, 12th, 20th, . . . , and (n-4)th display lines;
the (8N-3)th display line group consisting of the 5th, 13th, 21st, . . . , and (n-3)th display lines;
the (8N-2)th display line group consisting of the 6th, 14th, 22nd, . . . , and (n-2)th display lines;
the (8N-1)th display line group consisting of the 7th, 15th, 23rd, . . . , and (n-1)th display lines; and
the (8N)th display line group consisting of the 8th, 16th, 24th, . . . , and nth display lines.
Here, N is a natural number equal to or less than (1/8)·n.
The line dither offset value generation circuit 21 repeatedly executes, for each field and with 8 fields forming one cycle, the alteration of allocation of the line dither offset values LD to the display line groups, as shown in
Specifically, as shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
The line dither offset value generation circuit 21 provides the adder 22 with the line dither offset values LD allocated to the display lines belonging to discharge cells corresponding with pixel data PD supplied by the pixel data conversion circuit 1.
The adder 22 provides the lower bit discard circuit 23 with line-offset-added pixel data LF, which is prepared by adding the line dither offset values LD to pixel data PD supplied by the pixel data conversion circuit 1. The lower bit discard circuit 23 discards the lower three bits of the line-offset-added pixel data LF and then supplies the remaining three upper bits of this data LF to the drive data conversion circuit 3 as multiple grayscale pixel data MD.
A drive data conversion circuit 3 converts multiple grayscale pixel data MD into 4-bit pixel drive data GD in accordance with a data conversion table shown in
The memory 4 sequentially captures and stores the 4-bit pixel drive data GD. Each time the memory 4 finishes the writing of one image-frame (n rows×m columns) of pixel drive data GD1,1 to GDn,m, the memory 4 divides the pixel drive data GD1,1 to GDn,m into bit digits (0th to 3rd bits) and reads one display line's worth of this data at a time in correspondence with the subfields SF0 to SF3 respectively. The memory 4 supplies m pixel drive data bits corresponding to one display line to a column electrode driver circuit 5 as the pixel drive data bits DB1 to DBm.
That is, in the subfield SF0, the memory 4 reads only the 0th bit of each of the pixel drive data GD1,1 to GDn,m one display line at a time, and supplies the respective 0th bits to the column electrode driver circuit 5 as the pixel drive data bits DB1 to DBm. In the next subfield (i.e., subfield SF1), the memory 4 reads, one display line at a time, only the respective first bits of pixel drive data GD1,1 to GDn,m and supplies these first bits to the column electrode driver circuit 5 as the pixel drive data bits DB1 to DBm. Next, in the subfield SF2, the memory 4 reads only the respective second bits of the pixel drive data GD1,1 to GDn,m one display line at a time and supplies these second bits to the column electrode driver circuit 5 as pixel drive data bits DB1 to DBm. Subsequently, in the subfield SF3, the memory 4 reads only the respective third bits of the pixel drive data GD1,1 to GDn,m one display line at a time and supplies these third bits to the column electrode driver circuit 5 as pixel drive data bits DB1 to DBm.
A drive control circuit 6 generates various timing signals for grayscale-driving the PDP 100 in accordance with the light emission drive sequences shown in the following drawings:
The drive control circuit 6 supplies these timing signals to the column electrode driver circuit 5, the row electrode Y driver circuit 7 and the row electrode X driver circuit 8 respectively. A series of driving shown in
The column electrode driver circuit 5, the row electrode Y driver circuit 7, and the row electrode X driver circuit 8 generate various drive pulses (not shown) to drive the PDP 100 as described below in accordance with the timing signals supplied by the drive control circuit 6, and apply these drive pulses to the column electrodes D1 to Dm, row electrodes X1 to Xn, and row electrodes Y1 to Yn of the PDP 100, respectively.
It should be noted that in the light emission drive sequence shown in
The leading subfield SF0 sequentially executes a reset step R and an address step W0. The reset step R causes all the discharge cells G(1,1) to G(n,m) of the PDP 100 to perform a reset discharge all together and initializes the discharge cells G(1,1) to G(n,m) in a lit mode (state in which a wall charge of a predetermined amount is formed). In the address step W0, the discharge cells G arranged on the first to nth display lines of the PDP 100 are selectively made to perform an erase discharge in accordance with the pixel drive data GD as shown in
Each of the subfields SF1 to SF3 is further divided into eight subfields SF11, to SF18, SF21 to SF28, and SF31 to SF38 respectively. Address steps W1 to W8 are executed in the subfields SF11, to SF18, SF21 to SF28, and SF31 to SF38 respectively.
In the address step W1, only discharge cells that are arranged in the (8N-7)th display lines (i.e., the 1st, 9th, 17th, . . . , and (n-7)th display lines) among all the discharge cells G(1,1) to G(n,m) in the PDP 100, are selectively caused to perform an erasure discharge in accordance with the pixel drive data. As a result, discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until immediately before the address step W1. That is, the address step W1 sets the discharge cells arranged on the (8N-7)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W2, only the discharge cells arranged on the (8N-6)th display lines (i.e., the 2nd, 10th, 18th, . . . , and (n-6)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data. As a result, discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until immediately before the address step W2. That is, the address step W2 sets the discharge cells arranged on the (8N-6)th display lines to either the unlit mode or the lit mode in accordance with the pixel drive data.
In the address step W3, only discharge cells arranged on the (8N-5)th display lines (i.e., the 3rd, 11th, 19th, . . . , and (n-5)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data. As a result, discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W3. That is, the address step W3 sets the discharge cells arranged on the (8N-5)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W4, only discharge cells arranged on the (8N-4)th display lines (i.e., the 4th, 12th, 20th, . . . , and (n-4)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data. As a result, discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W4. That is, the address step W4 sets the discharge cells arranged on the (8N-4)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W5, only discharge cells arranged on the (8N-3)th display lines (i.e., the 5th, 13th, 21st, . . . , and (n-3)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data. As a result, discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W5. That is, the address step W5 sets the discharge cells arranged on the (8N-3)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W6, only discharge cells arranged on the (8N-2)th display lines (i.e., the 6th, 14th, 22nd, . . . , and (n-2)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data. As result, discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W6. That is, the address, step W6 sets the discharge cells arranged on the (8N-2)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W7, only discharge cells arranged on the (8N-1)th display lines (i.e., the 7th, 15th, 23rd, . . . , and (n-1)th display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data. Discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W7. That is, the address step W7 sets the discharge cells arranged on the (8N-1)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W8, only discharge cells arranged on the (8N)th display lines (i.e., the 8th, 16th, 24th, . . . , and nth display lines) are selectively made to perform an erasure discharge in accordance with the pixel drive data. Discharge cells in which an erasure discharge is induced are set to the unlit mode, and discharge cells in which an erasure discharge is not induced retain the state up until directly before the address step W8. That is, the address step W8 sets the discharge cells arranged on the (8N)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the light emission drive sequence shown in
the address step W6 in the subfields SF11, SF21, SF31 respectively;
the address step W3 in the subfields SF12, SF22, SF32 respectively;
the address step W8 in the subfields SF13, SF23, SF33 respectively;
the address step W5 in the subfields SF14, SF24, SF34 respectively;
the address step W2 in the subfields SF15, SF25, SF35 respectively;
the address step W7 in the subfields SF16, SF26g SF36 respectively;
the address step W4 in the subfields SF17, SF27, SF37 respectively; and
the address step W1 in the subfields SF18, SF28, SF38 respectively.
In the light emission drive sequence shown in
the address step W2 in the subfields SF11, SF21, SF31 respectively;
the address step W7 in the subfields SF12, SF22, SF32 respectively;
the address step W4 in the subfields SF13, SF23, SF33 respectively;
the address step W1 in the subfields SF14, SF24, SF34 respectively;
the address step W6 in the subfields SF151 SF25, SF35 respectively;
the address step W3 in the subfields SF16, SF26, SF36 respectively;
the address step W8 in the subfields SF17, SF27, SF37 respectively; and
the address step W5 in the subfields SF18, SF28, SF38 respectively.
In the light emission drive sequence shown in
the address step W8 in the subfields SF11, SF21, SF31 respectively;
the address step W5 in the subfields SF12, SF22, SF32 respectively;
the address step W2 in the subfields SF13, SF23, SF33 respectively;
the address step W7 in the subfields SF14, SF24, SF34 respectively;
the address step W4 in the subfields SF15, SF25, SF35 respectively;
the address step W1 in the subfields SF16, SF26, SF36 respectively;
the address step W6 in the subfields SF17, SF27, SF37 respectively; and
the address step W3 in the subfields SF18, SF28, SF38 respectively.
In the light emission drive sequence shown in
the address step W4 in the subfields SF11, SF21, SF31 respectively;
the address step W1 in the subfields SF12, SF22, SF32 respectively;
the address step W6 in the subfields SF13, SF23, SF33 respectively;
the address step W3 in the subfields SF14, SF24, SF34 respectively;
the address step W8 in the subfields SF15, SF25, SF35 respectively;
the address step W5 in the subfields SF16, SF26, SF36 respectively;
the address step W2 in the subfields SF17, SF27, SF37 respectively; and
the address step W7 in the subfields SF18, SF28, SF38 respectively.
In the light emission drive sequence shown in
the address step W3 in the subfields SF11, SF21, SF31 respectively;
the address step W8 in the subfields SF12, SF22, SF32 respectively;
the address step W5 in the subfields SF13, SF23, SF33 respectively;
the address step W2 in the subfields SF14, SF24, SF34 respectively;
the address step W7 in the subfields SF15, SF25, SF35 respectively;
the address step W4 in the subfields SF16, SF26, SF36 respectively;
the address step W1 in the subfields SF17, SF27, SF37 respectively; and
the address step W6 in the subfields SF18, SF28, SF38 respectively.
In the light emission drive sequence shown in
the address step W7 in the subfields SF11, SF21, SF31 respectively;
the address step W4 in the subfields SF12, SF22, SF32 respectively;
the address step W1 in the subfields SF13, SF23, SF33 respectively;
the address step W6 in the subfields SF14, SF24, SF34 respectively;
the address step W3 in the subfields SF15, SF25, SF35 respectively;
the address step W8 in the subfields SF16, SF26, SF36 respectively;
the address step W5 in the subfields SF17, SF27, SF37 respectively; and
the address step W2 in the subfields SF18, SF28, SF38 respectively.
In the light emission drive sequence shown in
the address step W5 in the subfields SF11, SF21, SF31 respectively;
the address step W2 in the subfields SF12, SF22, SF32 respectively;
the address step W7 in the subfields SF13, SF23, SF33 respectively;
the address step W4 in the subfields SF14, SF24, SF34 respectively;
the address step W1 in the subfields SF15, SF25, SF35 respectively;
the address step W6 in the subfields SF16, SF26, SF36 respectively;
the address step W3 in the subfields SF17, SF27, SF37 respectively; and
the address step W8 in the subfields SF18, SF28, SF38 respectively.
Further, in the light emission drive sequence shown in
the address step W1 in the subfields SF11, SF21, SF31 respectively;
the address step W6 in the subfields SF12, SF22, SF32 respectively;
the address step W3 in the subfields SF13, SF23, SF33 respectively;
the address step W8 in the subfields SF14, SF24, SF34 respectively;
the address step W5 in the subfields SF15, SF25, SF35 respectively;
the address step W2 in the subfields SF16, SF26, SF36 respectively;
the address step W7 in the subfields SF17, SF27, SF37 respectively; and
the address step W4 in the subfields SF18, SF28, SF38 respectively.
In each of the subfields SF11to SF18, SF21to SF28, and SF31 to SF38, directly before the respective address steps W1 to W8, a sustain step I, which causes only the discharge cells set to the lit mode to discharge light continuously over the period ‘1’, is executed.
In the final subfield SF4, only the sustain step I, which causes the discharge cells set to the lit mode to discharge light continuously over the period ‘1’, is executed.
The drive control circuit 6 performs light emission driving as shown in
When ‘1000’ pixel drive data GD, which represents the lowest luminance, is supplied, a light emission display based on first grayscale driving is executed. Because the 0th bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by the black circles) is induced in the discharge cells in the address step W0 of the subfield SF0, and the discharge cells become the unlit mode. According to the driving scheme shown in
In other words, in the first grayscale driving in accordance with the ‘1000’ pixel drive data GD, each discharge cell retains the unlit state in the course of a single field display period, thereby achieving the luminance level (brightness level) 0 as shown in
When ‘0100’ pixel drive data GD representing a luminance one level higher than that of the ‘1000’ pixel drive data is supplied, a light emission display based on second grayscale driving is implemented. Because the first bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by overlapping circles) is induced in the discharge cells in the address steps W1 to W8 of the subfield SF1. Because discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0, sustained discharge light emission is implemented continuously in the sustain steps I that exist in the interval up until the erasure discharge is induced. For example, in the light emission drive sequence shown in
Address step W6, which performs erasure discharge on the (8N-7)th display line group, is executed in the subfield SF11;
Address step W3, which performs erasure discharge on the (8N-6)th display line group, is executed in the subfield SF12;
Address step W8, which performs erasure discharge on the (8N-5)th display line group, is executed in the subfield SF13;
Address step W5, which performs erasure discharge on the (8N-4)th display line group, is executed in the subfield SF14;
Address step W2, which performs erasure discharge on the (8N-3)th display line group, is executed in the subfield SF15;
Address step W7, which performs erasure discharge on the (8N-2)th display line group, is executed in the subfield SF16;
Address step W4, which performs erasure discharge on the (8N-1)th display line group, is executed in the subfield SF17; and
Address step W1, which performs erasure discharge on the (8N)th display line group, is executed in the subfield SF18.
Accordingly, as indicated by the white and overlapping circles in
That is, in the second grayscale driving in accordance with the ‘0100’ pixel drive data GD, the discharge cells arranged on each display line are each driven at a luminance level corresponding with the period of the light emission produced by the sustained discharge induced in the course of a single field display period, as shown in
the discharge cells arranged on the (8N-7)th display line are at the luminance level ‘8’;
the discharge cells arranged on the (8N-6)th display lines are at the luminance level ‘5’;
the discharge cells arranged on the (8N-5)th display lines are at the luminance level ‘2’;
the discharge cells arranged on the (8N-4)th display lines are at the luminance level ‘7’;
the discharge cells arranged on the (8N-3)th display lines are at the luminance level ‘4’;
the discharge cells arranged on the (8N-2)th display lines are at the luminance level ‘1’;
the discharge cells arranged on the (8N-1)th display lines are at the luminance level ‘6’; and
the discharge cells arranged on the (8N)th display lines are at the luminance level ‘3’.
When ‘0010’ pixel drive data GD representing a luminance one level higher than that of the ‘0100’ pixel drive data is supplied, a light emission display based on third grayscale driving is performed. Because the second bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by overlapping circles) is induced in each discharge cell in the address steps W1 to W8 of the subfield SF2. The discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0, so that sustained discharge light emission is executed continuously in the sustain steps I that exist during the interval up until the erasure discharge is induced. For example, in the light emission drive sequence shown in
address step W6, which performs erasure discharge on the (8N-7)th display line group, is executed in the subfield SF21;
address step W3, which performs erasure discharge on the (8N-6)th display line group, is executed in the subfield SF22;
address step W8, which performs erasure discharge on the (8N-5)th display line group, is executed in the subfield SF23;
address step W5, which performs erasure discharge on the (8N-4)th display line group, is executed in the subfield SF24;
address step W2, which performs erasure discharge on the (8N-3)th display line group, is executed in the subfield SF25;
address step W7, which performs erasure discharge on the (8N-2)th display line group, is executed in the subfield SF26;
address step W4, which performs erasure discharge on the (8N-1)th display line group, is executed in the subfield SF27; and
address step W1, which performs erasure discharge on the (8N)th display line group, is executed in the subfield SF28.
Accordingly, as indicated by the white and overlapping circles in
Subfields SF11 to SF18 and the subfields SF21 to SF28 for the (8N-7)th display line;
Subfields SF11 to SF18 and the subfields SF21 to SF25 for the (8N-6)th display line;
Subfields SF11 to SF18 and the subfields SF21 to SF22 for the (8N-5)th display line;
Subfields SF11 to SF18 and the subfields SF21 to SF27 for the (8N-4)th display line;
Subfields SF11 to SF18 and the subfields SF21 to SF24 for the (8N-3)th display line;
Subfields SF11 to SF18 and the subfield SF21 for the (8N-2)th display line;
Subfields SF11 to SF18 and the subfields SF21 to SF26 for the (8N-1)th display line; and
Subfields SF11 to SF18 and the subfields SF21 to SF23 for the (8N)th display line.
That is, in the third grayscale driving in accordance with the ‘0010’ pixel drive data GD, the discharge cells arranged on each display line are each driven at a luminance level corresponding with the period of the light emission produced by the sustained discharge induced in the course of a single field display period, as shown in
the discharge cells arranged on the (8N-7)th display lines are at the luminance level ‘16’;
the discharge cells arranged on the (8N-6)th display lines are at the luminance level ‘13’;
the discharge cells arranged on the (8N-5)th display lines are at the luminance level ‘10’;
the discharge cells arranged on the (8N-4)th display lines are at the luminance level ‘15’;
the discharge cells arranged on the (8N-3)th display lines are at the luminance level ‘12’;
the discharge cells arranged on the (8N-2)th display lines are at the luminance level ‘9’;
the discharge cells arranged on the (8N-1)th display lines are at the luminance level ‘14’; and
the discharge cells arranged on the (8N)th display lines are at the luminance level ‘11’.
When ‘0001’ pixel drive data GD representing a luminance one level higher than that of the ‘0010’ pixel drive data is supplied, a light emission display based on fourth grayscale driving is performed as detailed below. Because the third bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by overlapping circles) is induced in each discharge cell in the address steps W1 to W8 of the subfield SF3. The discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0, so that sustained discharge light emission is executed continuously in the sustain steps I that exist during the interval up until the erasure discharge is induced. For example, in the light emission drive sequence shown in
Address step W6, which performs erasure discharge on the (8N-7)th display line group, is executed in the subfield SF31;
Address step W3, which performs erasure discharge on the (8N-6)th display line group, is executed in the subfield SF32;
Address step W8, which performs erasure discharge on the (8N-5)th display line group, is executed in the subfield SF33;
Address step W5, which performs erasure discharge on the (8N-4)th display line group, is executed in the subfield SF34;
Address step W2, which performs erasure discharge on the (8N-3)th display line group, is executed in the subfield SF35;
Address step W7, which performs erasure discharge on the (8N-2)th display line group, is executed in the subfield SF36;
Address step W4, which performs erasure discharge on the (8N-1)th display line group, is executed in the subfield SF37; and
Address step W1, which performs erasure discharge on the (8N)th display line group, is executed in the subfield SF38.
Accordingly, as indicated by the white and overlapping circles in
Subfields SF11 to SF28 and the subfields SF31 to SF38 for the (8N-7)th display line;
Subfields SF11 to SF28 and the subfields SF31 to SF35 for the (8N-6)th display line;
Subfields SF11 to SF28 and the subfields SF31 to SF32 for the (8N-5)th display line;
Subfields SF11 to SF28 and the subfields SF31 to SF37 for the (8N-4)th display line;
Subfields SF11 to SF28 and the subfields SF31 to SF34 for the (8N-3)th display line;
Subfields SF11 to SF28 and the subfield SF31 for the (8N-2)th display line;
Subfields SF11 to SF28 and the subfields SF31 to SF36 for the (8N-1)th display line;
Subfields SF11 to SF28 and the subfields SF31 to SF33 for the (8N)th display line.
That is, in the fourth grayscale driving in accordance with the ‘0001’ pixel drive data GD, the discharge cells each emit light at a luminance level corresponding with the period of the light emission produced by the sustained discharge induced in the course of a single field display period, as shown in FIG. 15. Specifically,
the discharge cells arranged on the (8N-7)th display lines are at the luminance level ‘24’;
the discharge cells arranged on the (8N-6)th display lines are at the luminance level ‘21’;
the discharge cells arranged on the (8N-5)th display lines are at the luminance level ‘18’;
the discharge cells arranged on the (8N-4)th display lines are at the luminance level ‘23’;
the discharge cells arranged on the (8N-3)th display lines are at the luminance level ‘20’;
the discharge cells arranged on the (8N-2)th display lines are at the luminance level ‘17’;
the discharge cells arranged on the (8N-1)th display lines are at the luminance level ‘22’; and
the discharge cells arranged on the (8N)th display lines are at the luminance level ‘19’.
When ‘0000’ pixel drive data GD representing the highest luminance is supplied, a light emission display based on the fifth grayscale driving is implemented. Because all the bits of the pixel drive data GD are logic level 0, erasure discharge is not induced at all during the single field display period. Accordingly, the discharge cells discharge light continuously in the sustain steps I of the subfields SF11 to SF18, SF21 to SF28, SF31 to SF38, and SF4.
That is, in the fifth grayscale driving in accordance with the ‘0000’ pixel drive data GD, the discharge cells each emit light at a luminance level corresponding with the period of the light emission produced by the sustained discharge induced in the course of a single field display period as shown in
the discharge cells arranged on the (8N-7)th display lines are at the luminance level ‘25’;
the discharge cells arranged on the (8N-6)th display lines are at the luminance level ‘25’;
the discharge cells arranged on the (8N-5)th display lines are at the luminance level ‘25’;
the discharge cells arranged on the (8N-4)th display lines are at the luminance level ‘25’;
the discharge cells arranged on the (8N-3)th display lines are at the luminance level ‘25’;
the discharge cells arranged on the (8N-2)th display lines are at the luminance level ‘25’;
the discharge cells arranged on the (8N-1)th display lines are at the luminance level ‘25’; and
the discharge cells arranged on the (8N)th display lines are at the luminance level ‘25’.
Therefore, in the above described driving, the first to fifth grayscale driving that is capable of representing luminance corresponding to five levels is executed in accordance with five different pixel drive data GD, namely, ‘1000’, ‘0100’, ‘0010’, ‘0001’, and ‘0000’. Here, different luminance weightings are applied to eight adjacent display lines, and the eight adjacent display lines are driven at different luminance levels determined by the respective luminance weightings, in each of the first to fifth grayscale driving.
For example, the following luminance weightings (‘1’ to ‘8’) are allocated to the eight adjacent display lines in the driving according to the light emission drive sequence for the first field shown in
The following luminance weightings are allocated to the eight adjacent display lines in the driving according to the light emission drive sequence for the second field shown in
The following luminance weightings are allocated to the eight adjacent display lines in the driving according to the light emission drive sequence for the third field shown in
The following luminance weightings are allocated to the eight adjacent display lines in the driving according to the light emission drive sequence for the fourth field shown in
The following luminance weightings are allocated to the eight adjacent display lines in the driving according to the light emission drive sequence for the fifth field shown in FIG. 6E:
The following luminance weightings are allocated to the eight adjacent display lines in the driving according to the light emission drive sequence for the sixth field shown in
The following luminance weightings are allocated to the eight adjacent display lines in the driving according to the light emission drive sequence for the seventh field shown in
The following luminance weightings are allocated to the eight adjacent display lines in the driving according to the light emission drive sequence for the eighth field shown in
As indicated by the light emission drive patterns shown in:
The actual drive operation executed in accordance with the video input signal will be described by taking the driving in the first field shown in
When the 6-bit pixel data PD corresponding with each column of discharge cells belonging to the eight adjacent display lines are all ‘010100’, the line dither offset value generation circuit 21 adds the line dither offset values LD shown in
The lower bit discard circuit 23 discards the lower 3 bits of each of these line-offset-added pixel data LF, thereby obtaining the remaining upper 3 bits of data as the multiple grayscale pixel data MD. That is, as shown in
These multiple grayscale pixel data MD are converted into 4-bit pixel drive data GD by the drive data conversion circuit 3. Specifically,
Therefore, as a result of the light emission drive patterns shown in
discharge cells arranged on the (8N-7)th display line: the luminance level ‘16’;
discharge cells arranged on the (8N-6)th display line: the luminance level ‘13’;
discharge cells arranged on the (8N-5)th display line: the luminance level ‘18’;
discharge cells arranged on the (8N-4)th display line: the luminance level ‘15’;
discharge cells arranged on the (8N-3)th display line: the luminance level ‘20’;
discharge cells arranged on the (8N-2)th display line: the luminance level ‘17’;
discharge cells arranged on the (8N-1)th display line: the luminance level ‘14’; and
discharge cells arranged on the (8N)th display line: the luminance level ‘19’.
Consequently, the luminance level produced by averaging the luminance levels of the eight display lines is observed.
As described above, the plasma display device shown in
In the line dither processing, the bias of the luminance difference between adjacent display lines of the PDP 100 should be substantially uniform. To this end, the bias is limited to lie within a predetermined value in this embodiment. For example, when ‘010100’ pixel data PD is supplied, the bias of the luminance difference is ‘2’, as shown in
the luminance difference between the (8N-7)th and (8N-6)th display lines is ‘3’;
the luminance difference between the (8N-6)th and (8N-5)th display lines is ‘5’;
the luminance difference between the (8N-5)th and (8N-4)th display lines is ‘3’;
the luminance difference between the (8N-4)th and (8N-3)th display lines is ‘5’;
the luminance difference between the (8N-3)th and (8N-2)th display lines is ‘3’;
the luminance difference between the (8N-2)th and (8N-1)th display lines is ‘3’; and
the luminance difference between the (8N-1)th and (8N)th display lines is ‘5’.
It should be noted that when other pixel data PD ate supplied, the bias of the luminance difference between the adjacent display lines is equal to or less than ‘2’ in this embodiment.
For example, according to the light emission drive patterns shown in
In this manner, when the line dither processing is executed, the bias of the luminance differences between adjacent display lines is restricted in a predetermined range, so that a high quality dither-processed image with a smaller luminance bias is expressed.
Further, in the line dither processing according to this embodiment, the first to eighth fields of the video input signal constitute one cycle, and the weighting of the line dither processing for each of the eight adjacent display lines is changed for each field as shown in
That is, the allocation of the following line dither processes to the respective display lines is changed for each field:
First line dither processing, which adds a ‘0’ line dither offset value LD to the pixel data PD and performs light emission driving corresponding with an ‘8’ luminance weighting;
Second line dither processing, which adds a ‘1’ line dither offset value LD to the pixel data PD and performs light emission driving corresponding with a ‘7’ luminance weighting;
Third line dither processing, which adds a ‘2’ line dither offset value LD to the pixel data PD and performs light emission driving corresponding with a ‘6’ luminance weighting;
Fourth line dither processing, which adds a ‘3’ line dither offset value LD to the pixel data PD and performs light emission driving corresponding with a ‘5’ luminance weighting;
Fifth line dither processing, which adds a ‘4’ line dither offset value LD to the pixel data PD and performs light emission driving corresponding with a ‘4’ luminance weighting;
Sixth line dither processing, which adds a ‘5’ line dither offset value LD to the pixel data PD and performs light emission driving corresponding with a ‘3’ luminance weighting;
Seventh line dither processing, which adds a ‘6’ line dither offset value LD to the pixel data PD and performs light emission driving corresponding with a ‘2’ luminance weighting; and
Eighth line dither processing, which adds a ‘7’ line dither offset value LD to the pixel data PD and performs light emission driving corresponding with a ‘1’ luminance weighting.
As shown in
In the second field, the first to eighth line dither processes are allocated to the display lines as follows:
In the third field, the first to eighth line dither processes are allocated to the display lines as follows:
In the fourth field, the first to eighth line dither processes are allocated to the display lines as follows:
In the fifth field, the first to eighth line dither processes are allocated to the display lines as follows:
In the sixth field, the first to eighth line dither processes are allocated to the display lines as follows:
In the seventh field, the first to eighth line dither processes are allocated to the display lines as follows:
In the eighth field, the first to eighth line dither processes are allocated to the display lines as follows:
In this embodiment, the respective line dither processing is applied alternately to upper and lower display in the screen for each field.
For example, in
Accordingly, there is a low probability of the viewer of the picture displayed on the screen of the PDP 100 continuously gazing at the pixels emitting light with the same luminance while casting his or her eyes over the screen. Therefore, a favorable dither display in which pseudo contours are not readily observed is implemented.
In the driving as described above, the subfield SF1 bears a low-luminance grayscale, the subfield SF2 bears a medium-luminance grayscale, and the subfield SF3 bears a high-luminance grayscale. The subfields SF1, SF2 and SF3 are further divided into the eight subfields SF11 to SF18, SF21 to SF28, and SF31 to SF38 respectively, as shown in
When driving is performed by allocating a light emission period corresponding with the weighting of the subfield to each of the subfields SF1 to SF3, the light emission period to be allocated to the subfield SF1 bearing the low-luminance grayscale is short, and therefore cases where the subfield SF1 cannot be divided into eight sometimes arise.
That is, the drive control circuit 6 supplies, to the column electrode driver circuit 5, the row electrode Y driver circuit 7 and the row electrode X driver circuit 8, various timing signals for grayscale-driving of the PDP 100 in accordance with the light emission drive sequences shown in the following figures in the following fields of the video input signal:
Further, the drive control circuit 6 repeatedly executes a series of driving shown in
Further, in the light emission drive sequence shown in
The leading subfield SF0 sequentially executes a reset step R and an address step W0. The reset step R causes all the discharge cells G(1,1) to G(n,m) of the PDP 100 to perform a reset discharge all together and initializes the discharge cells G(1,1) to G(n,m) in the lit mode (state in which a wall charge of a predetermined amount is formed). In the address step W0, the discharge cells G arranged on the first to nth display lines of the PDP 100 are selectively made to perform an erase discharge in accordance with the pixel drive data GD as shown in
As shown in
In the address step W1, only those discharge cells that are arranged on the (8N-7)th display lines, namely the 1st, 9th, 17th, . . . , and (n-7)th display lines, among all the discharge cells G(1,1) to G(n,m) formed in the PDP 100, are selectively caused to perform an erasure discharge in accordance with the pixel drive data. As a result, the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until immediately before the address step W1. That is, the address step W1 sets the discharge cells arranged on the (8N-7)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W2, only those discharge cells arranged on the (8N-6)th display lines, namely the 2nd, 10th, 18th, . . . , and (n-6)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data. As a result, the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until immediately before the address step W2. That is, the address step W2 sets the discharge cells arranged on the (8N-6)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In address step W3, only discharge cells arranged on the (8N-5)th display lines, namely the 3rd, 11th, 19th, . . . , and (n-5)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data. As a result, the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W3. Thus, the address step W3 sets the discharge cells arranged on the (8N-5)th display lines to either the unlit or the lit mode in accordance with the pixel drive data.
In address step W4, only discharge cells arranged on the (8N-4)th display lines, namely the 4th, 12th, 20th, . . . , and (n-4)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data. As a result, the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W4. Thus, the address step W4 sets the discharge cells arranged on the (8N-4)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W5, only those discharge cells arranged on the (8N-3)th display lines, namely the 5th, 13th, 21st, . . . , and (n-3)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data. As a result, the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W5. That is, the address step W5 sets the discharge cells arranged on the (8N-3)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W6, only those discharge cells arranged on the (8N-2)th display lines, namely the 6th, 14th, 22nd, . . . , and (n-2)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data. As a result, the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W6. Thus, the address step W6 sets the discharge cells arranged on the (8N-2)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W7, only the discharge cells arranged on the (8N-1)th display lines, namely the 7th, 15th, 23rd, . . . , and (n-1)th display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data. As a result, the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W7. That is, the address step W7 sets the discharge cells arranged on the (8N-1)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W8, only the discharge cells arranged on the (8N)th display lines, namely the 8th, 16th, 24th, . . . , and nth display lines, are selectively made to perform the erasure discharge in accordance with the pixel drive data. As a result, the discharge cells in which the erasure discharge is induced are set to the unlit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W8. Thus, the address step W8 sets the discharge cells arranged on the (8N)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
Here, in the light emission drive sequence shown in
the sustain step I and the address steps W6 and W3 are executed in sequence in the subfield SF11;
the sustain step I and the address steps W8 and W5 are executed in sequence in the subfield SF12;
the sustain step I and the address steps W2 and W7 are executed in sequence in the subfield SF13;
the sustain step I and the address steps W4 and W1 are executed in sequence in the subfield SF14;
the sustain step I and the address step W6 are executed in sequence in the subfields SF21 and SF31;
the sustain step I and the address step W3 are executed in sequence in the subfields SF22 and SF32;
the sustain step I and the address step W8 are executed in sequence in the subfields SF23 and SF33;
the sustain step I and the address step W5 are executed in sequence in the subfields SF24 and SF34;
the sustain step I and the address step W2 are executed in sequence in the subfields SF25 and SF35;
the sustain step I and the address step W7 are executed in sequence in the subfields SF26 and SF36;
the sustain step I and the address step W4 are executed in sequence in the subfields SF27 and SF37; and
the sustain step I and the address step W1 are executed in sequence in the subfields SF28 and SF38.
In the light emission drive sequence shown in
the sustain step I and the address steps W2 and W7 are executed in sequence in the subfield SF11;
the sustain step I and the address steps W4 and W1 are executed in sequence in the subfield SF12;
the sustain step I and the address steps W6 and W3 are executed in sequence in the subfield SF13;
the sustain step I and the address steps W8 and W5 are executed in sequence in the subfield SF14;
the sustain step I and the address step W2 are executed in sequence in the subfields SF2, and SF31;
the sustain step I and the address step W7 are executed in sequence in the subfields SF22 and SF32;
the sustain step I and the address step W4 are executed in sequence in the subfields SF23 and SF33;
the sustain step I and the address step W1 are executed in sequence in the subfields SF24 and SF34;
the sustain step I and the address step W6 are executed in sequence in the subfields SF25 and SF35;
the sustain step I and the address step W3 are executed in sequence in the subfields SF26 and SF36;
the sustain step I and the address step W8 are executed in sequence in the subfields SF27 and SF37; and
the sustain step I and the address step W5 are executed in sequence in the subfields SF28 and SF38.
In the light emission drive sequence shown in
the sustain step I and the address steps W8 and W5 are executed in sequence in the subfield SF11;
the sustain step I and the address steps W2 and W7 are executed in sequence in the subfield SF12;
the sustain step I and the address steps W4 and W1 are executed in sequence in the subfield SF13;
the sustain step I and the address steps W6 and W3 are executed in sequence in the subfield SF14;
the sustain step I and the address step W8 are executed in sequence in the subfields SF21 and SF31;
the sustain step I and the address step W5 are executed in sequence in the subfields SF22 and SF32;
the sustain step I and the address step W2 are executed in sequence in the subfields SF23 and SF33;
the sustain step I and the address step W7 are executed in sequence in the subfields SF24 and SF34;
the sustain step I and the address step W4 are executed in sequence in the subfields SF25 and SF35;
the sustain step I and the address step W1 are executed in sequence in the subfields SF26 and SF36;
the sustain step I and the address step W6 are executed in sequence in the subfields SF27 and SF37; and
the sustain step I and the address step W3 are executed in sequence in the subfields SF28 and SF38.
In the light emission drive sequence shown in
the sustain step I and the address steps W4 and W1 are executed in sequence in the subfield SF11;
the sustain step I and the address steps W6 and W3 are executed in sequence in the subfield SF12;
the sustain step I and the address steps W8 and W5 are executed in sequence in the subfield SF13;
the sustain step I and the address steps W2 and W7 are executed in sequence in the subfield SF14;
the sustain step I and the address step W4 are executed in sequence in the subfields SF21 and SF31;
the sustain step I and the address step W1 are executed in sequence in the subfields SF22 and SF32;
the sustain step I and the address step W6 are executed in sequence in the subfields SF23 and SF33;
the sustain step I and the address step W3 are executed in sequence in the subfields SF24 and SF34;
the sustain step I and the address step W8 are executed in sequence in the subfields SF25 and SF35;
the sustain step I and the address step W5 are executed in sequence in the subfields SF26 and SF36;
the sustain step I and the address step W2 are executed in sequence in the subfields SF27 and SF37; and
the sustain step I and the address step W7 are executed in sequence in the subfields SF28 and SF38.
In the light emission drive sequence shown in
the sustain step I and the address steps W3 and W8 are executed in sequence in the subfield SF11;
the sustain step I and the address steps W5 and W2 are executed in sequence in the subfield SF12;
the sustain step I and the address steps W7 and W4 are executed in sequence in the subfield SF13;
the sustain step I and the address steps W1 and W6 are executed in sequence in the subfield SF14;
the sustain step I and the address step W3 are executed in sequence in the subfields SF21 and SF31;
the sustain step I and the address step W8 are executed in sequence in the subfields SF22 and SF32;
the sustain step I and the address step W5 are executed in sequence in the subfields SF23 and SF33;
the sustain step I and the address step W2 are executed in sequence in the subfields SF24 and SF34;
the sustain step I and the address step W7 are executed in sequence in the subfields SF25 and SF35;
the sustain step I and the address step W4 are executed in sequence in the subfields SF26 and SF36;
the sustain step I and the address step W1 are executed in sequence in the subfields SF27 and SF37; and
the sustain step I and the address step W6 are executed in sequence in the subfields SF28 and SF38.
In the light emission drive sequence shown in
the sustain step I and the address steps W7 and W4 are executed in sequence in the subfield SF11;
the sustain step I and the address steps W1 and W6 are executed in sequence in the subfield SF12;
the sustain step I and the address steps W3 and W8 are executed in sequence in the subfield SF13;
the sustain step I and the address steps W5 and W2 are executed in sequence in the subfield SF14;
the sustain step I and the address step W7 are executed in sequence in the subfields SF21 and SF31;
the sustain step I and the address step W4 are executed in sequence in the subfields SF22 and SF32;
the sustain step I and the address step W1 are executed in sequence in the subfields SF23 and SF33;
the sustain step I and the address step W6 are executed in sequence in the subfields SF24 and SF34;
the sustain step I and the address step W3 are executed in sequence in the subfields SF25 and SF35;
the sustain step I and the address step W8 are executed in sequence in the subfields SF26 and SF36;
the sustain step I and the address step W5 are executed in sequence in the subfields SF27 and SF37; and
the sustain step I and the address step W2 are executed in sequence in the subfields SF28 and SF38.
In the light emission drive sequence shown in
the sustain step I and the address steps W5 and W2 are executed in sequence in the subfield SF11;
the sustain step I and the address steps W7 and W4 are executed in sequence in the subfield SF12;
the sustain step I and the address steps W1 and W6 are executed in sequence in the subfield SF13;
the sustain step I and the address steps W3 and W8 are executed in sequence in the subfield SF14;
the sustain step I and the address step W5 are executed in sequence in the subfields SF21 and SF31;
the sustain step I and the address step W2 are executed in sequence in the subfields SF22 and SF32;
the sustain step I and the address step W7 are executed in sequence in the subfields SF23 and SF33;
the sustain step I and the address step W4 are executed in sequence in the subfields SF24 and SF34;
the sustain step I and the address step W1 are executed in sequence in the subfields SF25 and SF35;
the sustain step I and the address step W6 are executed in sequence in the subfields SF26 and SF36;
the sustain step I and the address step W3 are executed in sequence in the subfields SF27 and SF37; and
the sustain step I and the address step W8 are executed in sequence in the subfields SF28 and SF38.
In the light emission drive sequence shown in
the sustain step I and the address steps W1 and W6 are executed in sequence in the subfield SF11;
the sustain step I and the address steps W3 and W8 are executed in sequence in the subfield SF12;
the sustain step I and the address steps W5 and W2 are executed in sequence in the subfield SF13;
the sustain step I and the address steps W7 and W4 are executed in sequence in the subfield SF14;
the sustain step I and the address step W1 are executed in sequence in the subfields SF21 and SF31;
the sustain step I and the address step W6 are executed in sequence in the subfields SF22 and SF32;
the sustain step I and the address step W3 are executed in sequence in the subfields SF23 and SF33;
the sustain step I and the address step W8 are executed in sequence in the subfields SF24 and SF34;
the sustain step I and the address step W5 are executed in sequence in the subfields SF25 and SF35;
the sustain step I and the address step W2 are executed in sequence in the subfields SF26 and SF36;
the sustain step I and the address step W7 are executed in sequence in the subfields SF27 and SF37; and
the sustain step I and the address step W4 are executed in sequence in the subfields SF28 and SF38.
Further, only the sustain step I, in which only the discharge cells set to the lit mode are made to discharge light continuously over period ‘1’, is executed in the final subfield SF4.
The drive control circuit 6 performs light emission driving as shown in
When ‘1000’ pixel drive data GD, which represents the lowest luminance, is supplied, a light emission display based on first grayscale driving as detailed below, is executed. Because the 0th bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by the black circles) is induced in the discharge cells in the address step W0 of the subfield SF0, and the discharge cells make the transition to the unlit mode. In the driving operations shown in
In other words, in the first grayscale driving in accordance with the ‘1000’ pixel drive data GD, each discharge cell retains an unlit state throughout a single field display period, so that driving at the luminance level 0 is implemented as shown in
Next, when the pixel drive data GD ‘0100’ representing a luminance one level higher than that of the pixel drive data ‘1000’ is supplied, a light emission display based on second grayscale driving is implemented as detailed below. Because the first bit of the pixel drive data GD is logic level 1, an erasure discharge (indicated by overlapping circles) is induced in the discharge cells in the address steps W1 to W8 of the subfield SF1. The discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0 so that sustained discharge light emission is implemented continuously in sustain steps I that exist in the interval up until the erasure discharge is induced. Therefore, for example, in the light emission drive sequence shown in
That is, in the second grayscale driving according to the ‘0100’ pixel drive data GD, the discharge cells arranged on each display line are each driven to emit light at a luminance level that corresponds with the period of the light emission generated by the sustained discharge induced during the single field display period. Specifically, as shown in
the discharge cells arranged on the (8N-6)th display line are at luminance level ‘3’;
the discharge cells arranged on the (8N-5)th display line are at luminance level ‘1’;
the discharge cells arranged on the (8N-4)th display line are at luminance level ‘4’;
the discharge cells arranged on the (8N-3)th display line are at luminance level ‘2’;
the discharge cells arranged on the (8N-2)th display line are at luminance level ‘1’;
the discharge cells arranged on the (8N-1)th display line are at luminance level ‘3’; and
the discharge cells arranged on the (8N)th display line are at luminance level ‘2’.
When the pixel drive data GD ‘0010’ representing a luminance one level higher than that of the pixel drive data ‘0100’ is supplied, a light emission display based on third grayscale driving is implemented as detailed below. Because the second bit of the pixel drive data GD is logic level 1, the erasure discharge (indicated by overlapping circles) is induced in the discharge cells in address steps W1 to W8 of the subfield SF2. The discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0 so that sustained discharge light emission is implemented continuously in sustain steps I that exist in the interval up until the erasure discharge is induced. For example, in the light emission drive sequence shown in
Thus, in the third grayscale driving according to the ‘0010’ pixel driving data GD, the discharge cells arranged on the respective display lines are each driven at a luminance level that corresponds with the period of the light emission generated by the sustained discharge induced during the single field display period, that is, as shown in
the discharge cells arranged on the (8N-7)th display line are at luminance level ‘12’;
the discharge cells arranged on the (8N-6)th display line are at luminance level ‘9’;
the discharge cells arranged on the (8N-5)th display line are at luminance level ‘6’;
the discharge cells arranged on the (8N-4)th display line are at luminance level ‘11’;
the discharge cells arranged on the (8N-3)th display line are at luminance level ‘8’;
the discharge cells arranged on the (8N-2)th display line are at luminance level ‘5’;
the discharge cells arranged on the (8N-1)th display line are at luminance level ‘10’; and
the discharge cells arranged on the (8N)th display line are at luminance level ‘7’.
When ‘0001’ pixel drive data GD representing a luminance one level higher than that of the ‘0010’ pixel drive data is supplied, a light emission display based on fourth grayscale driving is performed as detailed below. Because the third bit of the pixel drive data GD is logic level 1, the erasure discharge (indicated by overlapping circles) is induced in each discharge cell in the address steps W1 to W8 of the subfield SF3. The discharge cells are initialized in the lit mode in the reset step R of the leading subfield SF0, and then sustained discharge light emission is executed continuously in sustain steps I that exist during the interval up until the erasure discharge is induced. For example, in the light emission drive sequence shown in
Thus, in the fourth grayscale driving in accordance with the ‘0001’ pixel drive data GD, the discharge cells each emit light at a luminance level corresponding with the period of the light emission generated by the sustained discharge induced in the course of a single field display period, that is, as shown in
the discharge cells arranged on the (8N-7)th display line are at luminance level ‘20’;
the discharge cells arranged on the (8N-6)th display line are at luminance level ‘17’;
the discharge cells arranged on the (8N-5)th display line are at luminance level ‘14’;
the discharge cells arranged on the (8N-4)th display line are at luminance level ‘19’;
the discharge cells arranged on the (8N-3)th display line are at luminance level ‘16’;
the discharge cells arranged on the (8N-2)th display line are at luminance level ‘13’;
the discharge cells arranged on the (8N-1)th display line are at luminance level ‘18’; and
the discharge cells arranged on the (8N)th display line are at luminance level ‘15’.
When ‘0000’ pixel drive data GD representing the highest luminance is supplied, a light emission display based on the fifth grayscale driving is implemented as detailed below. Because all the bits of the pixel drive data GD are logic level 0, the erasure discharge is not induced at all during the single field display period. Accordingly, the discharge cells discharge light continuously in the sustain steps I of the subfields SF11 to SF14, SF21 to SF28, SF31 to SF38, and SF4.
Thus, in the fifth grayscale driving in accordance with the ‘0000’ pixel drive data GD, the discharge cells each emit light at a luminance level corresponding with the period of the light emission generated by the sustained discharge induced in the course of a single field display period. Specifically, as shown in
In the line dither processing of this embodiment, the line dither offset values LD are added to the pixel data PD. Accordingly, when a certain display line is driven with kth grayscale driving (k=1, 2, 3, 4, 5), the adjacent display lines are driven with kth grayscale driving or (k+1)th grayscale driving. As shown in
As described above, in the drive shown in
Therefore, according to this driving, even when the period to be allocated to the subfield bearing the low luminance grayscale is short compared with the other subfields, a high-quality line dither display in which the difference in luminance between all the adjacent display lines of the PDP 100 is substantially uniform can be implemented similarly to the drive shown in
In this embodiment, in order to set each of the discharge cells to either the lit mode or unlit mode in accordance with the pixel data, so-called selective erasure addressing is adopted, in which all the discharge cells are preset to the lit mode and discharge cells are then selectively made to make the transition to the unlit mode in accordance with pixel data.
However, the present invention can also be applied to a case of adopting so-called selective write addressing, in which all the discharge cells are preset to the unlit mode and discharge cells are selectively made to make the transition to the lit mode in accordance with pixel data.
When selective write addressing is adopted, the drive data conversion circuit 3 shown in
In the light emission drive sequence shown in
After the execution of this subfield SF4, the subfields SF31 to SF38, SF21 to SF28, and SF11 to SF14, are executed in sequence. The address steps W1 to W8 are executed as detailed below in the subfields SF3 to SF1.
In the address step W1, only those discharge cells that are arranged on the (8N-7)th display lines, namely the 1st, 9th, 17th, . . . , and (n-7)th display lines, among all the discharge cells G(1,1) to G(n,m) formed in the PDP 100, are selectively caused to perform a write discharge in accordance with the pixel drive data. As a result, the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until immediately before the address step W1. Thus, the address step W1 sets the discharge cells arranged on the (8N-7)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W4, only those discharge cells arranged on the (8N-4)th display lines, namely the 4th, 12th, 20th, . . . , and (n-4)th display lines, are selectively made to perform a write discharge in accordance with the pixel drive data. As a result, the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until directly before the address step W4. Thus, the address step W4 sets the discharge cells arranged on the (8N-4)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W7, only discharge cells arranged on the (8N-1)th display line, namely the 7th, 15th, 23rd, . . . , and (n-1)th display lines, are selectively made to perform a write discharge in accordance with the pixel drive data. As a result, the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until directly before the address step W7. Thus, the address step W7 sets the discharge cells arranged on the (8N-1)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W2, only the discharge cells arranged on the (8N-6)th display lines, namely the 2nd, 10th, 18th, . . . , and (n-6)th display lines, are selectively made to perform the write discharge in accordance with the pixel drive data. As a result, the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until immediately before the address step W2. Thus, the address step W2 sets the discharge cells arranged on the (8N-6)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W5, only the discharge cells arranged on the (8N-3)th display lines, namely the 5th, 13th, 21st, . . . , and (n-3)th display lines, are selectively made to perform the write discharge in accordance with the pixel drive data. As a result, the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until directly before the address step W5. Thus, the address step W5 sets the discharge cells arranged on the (8N-3)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W8, only the discharge cells arranged on the (8N)th display lines, namely the 8th, 16th, 24th, . . . , and nth display lines, are selectively made to perform the write discharge in accordance with the pixel drive data. As a result, the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until directly before the address step W8. Thus, the address step W8 sets the discharge cells arranged on the (8N)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W3, only the discharge cells arranged on the (8N-5)th display lines, namely the 3rd, 11th, 19th, . . . , and (n-5)th display lines, are selectively made to perform the write discharge in accordance with the pixel drive data. As a result, the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the erasure discharge is not induced retain the state up until directly before the address step W3. Thus, the address step W3 sets the discharge cells arranged on the (8N-5)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the address step W6, only the discharge cells arranged on the (8N-2)th display lines, namely the 6th, 14th, 22nd, . . . , and (n-2)th display lines, are selectively made to perform the write discharge in accordance with the pixel drive data. As a result, the discharge cells in which the write discharge is induced are set to the lit mode, and the discharge cells in which the write discharge is not induced retain the state up until directly before the address step W6. Thus, the address step W6 sets the discharge cells arranged on the (8N-2)th display lines to either the unlit or lit mode in accordance with the pixel drive data.
In the light emission drive sequence shown in
The sustain step I, in which only those discharge cells in the lit mode are made to emit light by performing a sustained discharge continuously over the light emission period ‘1’, is executed directly after the address steps W1 to W8.
Whether or not the write discharge should be induced in the address steps W1 to W8 of the respective subfields SF1 to SF4 is determined by the bits of the pixel drive data GD shown in
Although, in the driving shown in
For example, the subfield SF1 may be divided:
This application is based on a Japanese patent application No. 2003-190284 filed on Jul. 2, 2003, and the entire disclosure thereof is incorporated herein by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-190284 | Jul 2003 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6747669 | Yamaguchi et al. | Jun 2004 | B1 |
| 6836263 | Naka et al. | Dec 2004 | B2 |
| 7057773 | Ilbery | Jun 2006 | B2 |
| Number | Date | Country |
|---|---|---|
| 2000-227778 | Aug 2000 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20050057452 A1 | Mar 2005 | US |
